diff options
123 files changed, 22164 insertions, 16696 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index d2896598b..add5f9d75 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer +children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -191,13 +203,14 @@ predType=tournament [system.cpu.checker] type=O3Checker -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu dtb=system.cpu.checker.dtb eventq_index=0 exitOnError=false @@ -205,6 +218,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -221,10 +235,35 @@ updateOnError=true warnOnlyOnLoadError=true workload= +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[9] + [system.cpu.checker.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.dtb.walker @@ -232,32 +271,69 @@ walker=system.cpu.checker.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[7] [system.cpu.checker.isa] type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[8] [system.cpu.checker.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.itb.walker @@ -265,9 +341,10 @@ walker=system.cpu.checker.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[6] [system.cpu.checker.tracer] type=ExeTracer @@ -308,10 +385,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -319,6 +421,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -673,24 +776,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -698,6 +837,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -746,7 +886,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index ccd250823..43698041c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,25 +10,20 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 6176053500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6184767500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6220839500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6236327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6779610500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0 -warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 -warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 51874115000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 2476169247000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2490093200000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2491309014500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2512521404000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2513043156000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2517323856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 +warn: 2518814467000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2519896624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2519897721500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2520452967000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index a9e6de1f3..a26501a59 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:07:43 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:47:40 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.checker.isa: ISA system set to: 0x645a800 0x645a800 + 0: system.cpu.isa: ISA system set to: 0x645a800 0x645a800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525131633500 because m5_exit instruction encountered +Exiting @ tick 2526146947500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e81d47f63..1902f9930 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525132 # Number of seconds simulated -sim_ticks 2525131633500 # Number of ticks simulated -final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526147 # Number of seconds simulated +sim_ticks 2526146947500 # Number of ticks simulated +final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63748 # Simulator instruction rate (inst/s) -host_op_rate 82026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2669254242 # Simulator tick rate (ticks/s) -host_mem_usage 403420 # Number of bytes of host memory used -host_seconds 946.01 # Real time elapsed on the host -sim_insts 60305678 # Number of instructions simulated -sim_ops 77596684 # Number of ops (including micro ops) simulated +host_inst_rate 57077 # Simulator instruction rate (inst/s) +host_op_rate 73443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2390895648 # Simulator tick rate (ticks/s) +host_mem_usage 424332 # Number of bytes of host memory used +host_seconds 1056.57 # Real time elapsed on the host +sim_insts 60306154 # Number of instructions simulated +sim_ops 77597242 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813149 # Number of write requests accepted -system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue -system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943580 # Per bank write bursts -system.physmem.perBankRdBursts::1 943152 # Per bank write bursts -system.physmem.perBankRdBursts::2 939288 # Per bank write bursts -system.physmem.perBankRdBursts::3 939310 # Per bank write bursts -system.physmem.perBankRdBursts::4 943113 # Per bank write bursts -system.physmem.perBankRdBursts::5 943139 # Per bank write bursts -system.physmem.perBankRdBursts::6 939134 # Per bank write bursts -system.physmem.perBankRdBursts::7 938551 # Per bank write bursts -system.physmem.perBankRdBursts::8 944000 # Per bank write bursts -system.physmem.perBankRdBursts::9 943392 # Per bank write bursts -system.physmem.perBankRdBursts::10 938425 # Per bank write bursts -system.physmem.perBankRdBursts::11 937973 # Per bank write bursts -system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943534 # Per bank write bursts -system.physmem.perBankRdBursts::14 939230 # Per bank write bursts -system.physmem.perBankRdBursts::15 938669 # Per bank write bursts -system.physmem.perBankWrBursts::0 6703 # Per bank write bursts -system.physmem.perBankWrBursts::1 6464 # Per bank write bursts -system.physmem.perBankWrBursts::2 6595 # Per bank write bursts -system.physmem.perBankWrBursts::3 6634 # Per bank write bursts -system.physmem.perBankWrBursts::4 6559 # Per bank write bursts -system.physmem.perBankWrBursts::5 6792 # Per bank write bursts -system.physmem.perBankWrBursts::6 6793 # Per bank write bursts -system.physmem.perBankWrBursts::7 6730 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6539 # Per bank write bursts -system.physmem.perBankWrBursts::11 6181 # Per bank write bursts -system.physmem.perBankWrBursts::12 7151 # Per bank write bursts -system.physmem.perBankWrBursts::13 6766 # Per bank write bursts -system.physmem.perBankWrBursts::14 7035 # Per bank write bursts -system.physmem.perBankWrBursts::15 6897 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096836 # Number of read requests accepted +system.physmem.writeReqs 813120 # Number of write requests accepted +system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943071 # Per bank write bursts +system.physmem.perBankRdBursts::2 939289 # Per bank write bursts +system.physmem.perBankRdBursts::3 939279 # Per bank write bursts +system.physmem.perBankRdBursts::4 943119 # Per bank write bursts +system.physmem.perBankRdBursts::5 943242 # Per bank write bursts +system.physmem.perBankRdBursts::6 939090 # Per bank write bursts +system.physmem.perBankRdBursts::7 938633 # Per bank write bursts +system.physmem.perBankRdBursts::8 943981 # Per bank write bursts +system.physmem.perBankRdBursts::9 943506 # Per bank write bursts +system.physmem.perBankRdBursts::10 938534 # Per bank write bursts +system.physmem.perBankRdBursts::11 937721 # Per bank write bursts +system.physmem.perBankRdBursts::12 943933 # Per bank write bursts +system.physmem.perBankRdBursts::13 943406 # Per bank write bursts +system.physmem.perBankRdBursts::14 939034 # Per bank write bursts +system.physmem.perBankRdBursts::15 938886 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6452 # Per bank write bursts +system.physmem.perBankWrBursts::2 6617 # Per bank write bursts +system.physmem.perBankWrBursts::3 6618 # Per bank write bursts +system.physmem.perBankWrBursts::4 6551 # Per bank write bursts +system.physmem.perBankWrBursts::5 6799 # Per bank write bursts +system.physmem.perBankWrBursts::6 6798 # Per bank write bursts +system.physmem.perBankWrBursts::7 6724 # Per bank write bursts +system.physmem.perBankWrBursts::8 7121 # Per bank write bursts +system.physmem.perBankWrBursts::9 6870 # Per bank write bursts +system.physmem.perBankWrBursts::10 6536 # Per bank write bursts +system.physmem.perBankWrBursts::11 6184 # Per bank write bursts +system.physmem.perBankWrBursts::12 7152 # Per bank write bursts +system.physmem.perBankWrBursts::13 6752 # Per bank write bursts +system.physmem.perBankWrBursts::14 7039 # Per bank write bursts +system.physmem.perBankWrBursts::15 6901 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525130505500 # Total gap between requests +system.physmem.totGap 2526145872500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.readPktSize::6 154590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59131 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -145,616 +145,621 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation -system.physmem.totQLat 365453646000 # Total ticks spent queuing -system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks -system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation +system.physmem.totQLat 365142496500 # Total ticks spent queuing +system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks +system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing -system.physmem.readRowHits 14986798 # Number of row buffer hits during reads -system.physmem.writeRowHits 93332 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing +system.physmem.readRowHits 14986658 # Number of row buffer hits during reads +system.physmem.writeRowHits 93339 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes -system.physmem.avgGap 158713.50 # Average gap between requests +system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes +system.physmem.avgGap 158777.68 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -767,50 +772,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54900302 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149434 # Transaction distribution -system.membus.trans_dist::ReadResp 16149434 # Transaction distribution +system.membus.throughput 54877277 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149448 # Transaction distribution +system.membus.trans_dist::ReadResp 16149448 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59131 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution -system.membus.trans_dist::ReadExReq 131448 # Transaction distribution -system.membus.trans_dist::ReadExResp 131448 # Transaction distribution +system.membus.trans_dist::Writeback 59102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution +system.membus.trans_dist::ReadExReq 131427 # Transaction distribution +system.membus.trans_dist::ReadExResp 131427 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630489 # Total data (bytes) +system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138628065 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -818,7 +823,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285786 # Throughput (bytes/s) +system.iobus.throughput 48266379 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -928,40 +933,82 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14384927 # Number of BP lookups -system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits +system.cpu.branchPred.lookups 14756776 # Number of BP lookups +system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions. +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986834 # DTB read hits +system.cpu.checker.dtb.read_hits 14986903 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227416 # DTB write hits +system.cpu.checker.dtb.write_hits 11227441 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994141 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229607 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994210 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229632 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214250 # DTB hits +system.cpu.checker.dtb.hits 26214344 # DTB hits system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26223748 # DTB accesses -system.cpu.checker.itb.inst_hits 61479661 # ITB inst hits +system.cpu.checker.dtb.accesses 26223842 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.inst_hits 61480126 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -971,43 +1018,85 @@ system.cpu.checker.itb.flush_tlb 4 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 4683 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses -system.cpu.checker.itb.hits 61479661 # DTB hits +system.cpu.checker.itb.inst_accesses 61484599 # ITB inst accesses +system.cpu.checker.itb.hits 61480126 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61484134 # DTB accesses -system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484599 # DTB accesses +system.cpu.checker.numCycles 77883033 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51182106 # DTB read hits -system.cpu.dtb.read_misses 64421 # DTB read misses -system.cpu.dtb.write_hits 11699698 # DTB write hits -system.cpu.dtb.write_misses 15824 # DTB write misses +system.cpu.dtb.read_hits 51181584 # DTB read hits +system.cpu.dtb.read_misses 65031 # DTB read misses +system.cpu.dtb.write_hits 11699885 # DTB write hits +system.cpu.dtb.write_misses 15694 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6560 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51246527 # DTB read accesses -system.cpu.dtb.write_accesses 11715522 # DTB write accesses +system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246615 # DTB read accesses +system.cpu.dtb.write_accesses 11715579 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62881804 # DTB hits -system.cpu.dtb.misses 80245 # DTB misses -system.cpu.dtb.accesses 62962049 # DTB accesses -system.cpu.itb.inst_hits 11522583 # ITB inst hits -system.cpu.itb.inst_misses 11276 # ITB inst misses +system.cpu.dtb.hits 62881469 # DTB hits +system.cpu.dtb.misses 80725 # DTB misses +system.cpu.dtb.accesses 62962194 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 11524718 # ITB inst hits +system.cpu.itb.inst_misses 11477 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -1016,114 +1105,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4956 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11533859 # ITB inst accesses -system.cpu.itb.hits 11522583 # DTB hits -system.cpu.itb.misses 11276 # DTB misses -system.cpu.itb.accesses 11533859 # DTB accesses -system.cpu.numCycles 474898657 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536195 # ITB inst accesses +system.cpu.itb.hits 11524718 # DTB hits +system.cpu.itb.misses 11477 # DTB misses +system.cpu.itb.accesses 11536195 # DTB accesses +system.cpu.numCycles 477111575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1151,437 +1240,436 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued -system.cpu.iq.rate 0.258806 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued +system.cpu.iq.rate 0.257621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221761 # number of nop insts executed -system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475005 # Number of branches executed -system.cpu.iew.exec_stores 12211635 # Number of stores executed -system.cpu.iew.exec_rate 0.254432 # Inst execution rate -system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47031033 # num instructions producing a value -system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value +system.cpu.iew.exec_nop 221300 # number of nop insts executed +system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed +system.cpu.iew.exec_branches 11821026 # Number of branches executed +system.cpu.iew.exec_stores 12211427 # Number of stores executed +system.cpu.iew.exec_rate 0.253266 # Inst execution rate +system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47016858 # num instructions producing a value +system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456059 # Number of instructions committed -system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456535 # Number of instructions committed +system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385723 # Number of memory references committed -system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.refs 27385855 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 9961071 # Number of branches committed +system.cpu.commit.branches 10305769 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. -system.cpu.commit.function_calls 991207 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69188185 # Number of committed integer instructions. +system.cpu.commit.function_calls 991209 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240665808 # The number of ROB reads -system.cpu.rob.rob_writes 195946920 # The number of ROB writes -system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305678 # Number of Instructions Simulated -system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated -system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547244885 # number of integer regfile reads -system.cpu.int_regfile_writes 87532646 # number of integer regfile writes -system.cpu.fp_regfile_reads 8511 # number of floating regfile reads -system.cpu.fp_regfile_writes 2972 # number of floating regfile writes -system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads -system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution +system.cpu.rob.rob_reads 242914035 # The number of ROB reads +system.cpu.rob.rob_writes 195975439 # The number of ROB writes +system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306154 # Number of Instructions Simulated +system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated +system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548607877 # number of integer regfile reads +system.cpu.int_regfile_writes 87541392 # number of integer regfile writes +system.cpu.fp_regfile_reads 8324 # number of floating regfile reads +system.cpu.fp_regfile_writes 2920 # number of floating regfile writes +system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980798 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980909 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits -system.cpu.icache.overall_hits::total 10457750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses -system.cpu.icache.overall_misses::total 1061214 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits +system.cpu.icache.overall_hits::total 10459956 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses +system.cpu.icache.overall_misses::total 1061258 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses 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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61057.328845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63993.011163 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62425.679151 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1702,13 +1790,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643483 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643250 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21507454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643762 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.409015 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1716,154 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miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks -system.cpu.dcache.writebacks::total 607897 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks +system.cpu.dcache.writebacks::total 607582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065008 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065008 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249031 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249031 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1887,16 +1975,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 5b8c35474..518b7284a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -224,10 +236,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -235,6 +272,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -589,24 +627,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -614,6 +688,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -624,7 +699,7 @@ eventq_index=0 [system.cpu1] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -650,6 +725,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fetchBufferSize=64 @@ -668,6 +744,7 @@ interrupts=system.cpu1.interrupts isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -750,7 +827,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -762,10 +839,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -773,9 +875,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.fuPool] type=FUPool @@ -1107,7 +1210,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -1127,24 +1230,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -1152,9 +1291,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1791,7 +1931,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 8a51f6391..a00c0b470 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:17:38 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:56:34 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6856800 0x6856800 + 0: system.cpu1.isa: ISA system set to: 0x6856800 0x6856800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1104766159000 because m5_exit instruction encountered +Exiting @ tick 2605645191500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3b2b0bf59..2d523b33d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.104766 # Number of seconds simulated -sim_ticks 1104766159000 # Number of ticks simulated -final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605645 # Number of seconds simulated +sim_ticks 2605645191500 # Number of ticks simulated +final_tick 2605645191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77156 # Simulator instruction rate (inst/s) -host_op_rate 99328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1383749494 # Simulator tick rate (ticks/s) -host_mem_usage 406496 # Number of bytes of host memory used -host_seconds 798.39 # Real time elapsed on the host -sim_insts 61600257 # Number of instructions simulated -sim_ops 79301805 # Number of ops (including micro ops) simulated +host_inst_rate 69894 # Simulator instruction rate (inst/s) +host_op_rate 90000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2899968268 # Simulator tick rate (ticks/s) +host_mem_usage 430484 # Number of bytes of host memory used +host_seconds 898.51 # Real time elapsed on the host +sim_insts 62800764 # Number of instructions simulated +sim_ops 80866121 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory -system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 392704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4367548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 428032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5265336 # Number of bytes read from this memory +system.physmem.bytes_read::total 131566132 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 392704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 428032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 820736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282176 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7311312 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6136 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6688 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82299 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302287 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257980 # Number of read requests accepted -system.physmem.writeReqs 823516 # Number of write requests accepted -system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue -system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 391105 # Per bank write bursts -system.physmem.perBankRdBursts::1 391040 # Per bank write bursts -system.physmem.perBankRdBursts::2 387008 # Per bank write bursts -system.physmem.perBankRdBursts::3 386856 # Per bank write bursts -system.physmem.perBankRdBursts::4 391768 # Per bank write bursts -system.physmem.perBankRdBursts::5 391357 # Per bank write bursts -system.physmem.perBankRdBursts::6 387221 # Per bank write bursts -system.physmem.perBankRdBursts::7 386642 # Per bank write bursts -system.physmem.perBankRdBursts::8 391438 # Per bank write bursts -system.physmem.perBankRdBursts::9 391160 # Per bank write bursts -system.physmem.perBankRdBursts::10 385906 # Per bank write bursts -system.physmem.perBankRdBursts::11 385319 # Per bank write bursts -system.physmem.perBankRdBursts::12 390977 # Per bank write bursts -system.physmem.perBankRdBursts::13 390642 # Per bank write bursts -system.physmem.perBankRdBursts::14 386557 # Per bank write bursts -system.physmem.perBankRdBursts::15 386235 # Per bank write bursts -system.physmem.perBankWrBursts::0 7173 # Per bank write bursts -system.physmem.perBankWrBursts::1 7194 # Per bank write bursts -system.physmem.perBankWrBursts::2 7298 # Per bank write bursts -system.physmem.perBankWrBursts::3 7217 # Per bank write bursts -system.physmem.perBankWrBursts::4 7815 # Per bank write bursts -system.physmem.perBankWrBursts::5 7451 # Per bank write bursts -system.physmem.perBankWrBursts::6 7359 # Per bank write bursts -system.physmem.perBankWrBursts::7 7185 # Per bank write bursts -system.physmem.perBankWrBursts::8 7499 # Per bank write bursts -system.physmem.perBankWrBursts::9 7507 # Per bank write bursts -system.physmem.perBankWrBursts::10 6838 # Per bank write bursts -system.physmem.perBankWrBursts::11 6616 # Per bank write bursts -system.physmem.perBankWrBursts::12 7156 # Per bank write bursts -system.physmem.perBankWrBursts::13 6834 # Per bank write bursts -system.physmem.perBankWrBursts::14 7291 # Per bank write bursts -system.physmem.perBankWrBursts::15 7179 # Per bank write bursts +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824193 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46480054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 150713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1676187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2020742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50492727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 150713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314984 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1643423 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2805951 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1643423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46480054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 150713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1682711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3176746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53298678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302287 # Number of read requests accepted +system.physmem.writeReqs 824193 # Number of write requests accepted +system.physmem.readBursts 15302287 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 824193 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976879168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2467200 # Total number of bytes read from write queue +system.physmem.bytesWritten 7418176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131566132 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7311312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38550 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 708272 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956326 # Per bank write bursts +system.physmem.perBankRdBursts::1 956081 # Per bank write bursts +system.physmem.perBankRdBursts::2 952133 # Per bank write bursts +system.physmem.perBankRdBursts::3 952389 # Per bank write bursts +system.physmem.perBankRdBursts::4 956868 # Per bank write bursts +system.physmem.perBankRdBursts::5 956262 # Per bank write bursts +system.physmem.perBankRdBursts::6 951633 # Per bank write bursts +system.physmem.perBankRdBursts::7 951532 # Per bank write bursts +system.physmem.perBankRdBursts::8 956738 # Per bank write bursts +system.physmem.perBankRdBursts::9 956585 # Per bank write bursts +system.physmem.perBankRdBursts::10 951315 # Per bank write bursts +system.physmem.perBankRdBursts::11 950633 # Per bank write bursts +system.physmem.perBankRdBursts::12 956323 # Per bank write bursts +system.physmem.perBankRdBursts::13 956319 # Per bank write bursts +system.physmem.perBankRdBursts::14 951484 # Per bank write bursts +system.physmem.perBankRdBursts::15 951116 # Per bank write bursts +system.physmem.perBankWrBursts::0 7149 # Per bank write bursts +system.physmem.perBankWrBursts::1 7007 # Per bank write bursts +system.physmem.perBankWrBursts::2 7292 # Per bank write bursts +system.physmem.perBankWrBursts::3 7274 # Per bank write bursts +system.physmem.perBankWrBursts::4 7928 # Per bank write bursts +system.physmem.perBankWrBursts::5 7489 # Per bank write bursts +system.physmem.perBankWrBursts::6 7090 # Per bank write bursts +system.physmem.perBankWrBursts::7 7095 # Per bank write bursts +system.physmem.perBankWrBursts::8 7536 # Per bank write bursts +system.physmem.perBankWrBursts::9 7648 # Per bank write bursts +system.physmem.perBankWrBursts::10 6979 # Per bank write bursts +system.physmem.perBankWrBursts::11 6633 # Per bank write bursts +system.physmem.perBankWrBursts::12 7251 # Per bank write bursts +system.physmem.perBankWrBursts::13 7189 # Per bank write bursts +system.physmem.perBankWrBursts::14 7290 # Per bank write bursts +system.physmem.perBankWrBursts::15 7059 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1104765054500 # Total gap between requests +system.physmem.totGap 2605643958000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 105 # Read request sizes (log2) -system.physmem.readPktSize::3 6094848 # Read request sizes (log2) +system.physmem.readPktSize::2 109 # Read request sizes (log2) +system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 163027 # Read request sizes (log2) +system.physmem.readPktSize::6 163362 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66680 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66909 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1182621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1128295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1080999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3674790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2650191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2638240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2645126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 56320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 21310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 21179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -161,579 +161,620 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 556 0.78% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 523 0.74% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 304 0.43% 75.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 266 0.38% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 142 0.20% 76.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 425 0.60% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 119 0.17% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 139 0.20% 77.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 90 0.13% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 153 0.22% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 51 0.07% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 550 0.78% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 38 0.05% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 222 0.31% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 29 0.04% 78.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 108 0.15% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 16 0.02% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 57 0.08% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 19 0.03% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 237 0.33% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 12 0.02% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 45 0.06% 79.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 10 0.01% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 54 0.08% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 16 0.02% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 29 0.04% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 27 0.04% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 2 0.00% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 17 0.02% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 5 0.01% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 28 0.04% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 22 0.03% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 178 0.25% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 2 0.00% 80.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 13 0.02% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 3 0.00% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 19 0.03% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 20 0.03% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 13 0.02% 81.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 19 0.03% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 20 0.03% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.02% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 3 0.00% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 93 0.13% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 4 0.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 15 0.02% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 12 0.02% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 4 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 80 0.11% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 5 0.01% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 21 0.03% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 25 0.04% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 3 0.00% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 5 0.01% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 24 0.03% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 4 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 11 0.02% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 94 0.13% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 1 0.00% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 12 0.02% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 4 0.01% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 79 0.11% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 3 0.00% 82.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 3 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 2 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 32 0.05% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 4 0.01% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 266 0.38% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 25 0.04% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 67 0.09% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8775 3 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 85 0.12% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 19 0.03% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9287 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 13 0.02% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 69 0.10% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 2 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 92 0.13% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 80 0.11% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 87 0.12% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 2 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10695 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 16 0.02% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.11% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 80 0.11% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 2 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11463 1 0.00% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 10 0.01% 84.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 70 0.10% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 175 0.25% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 22 0.03% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 37 0.05% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 80 0.11% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 161 0.23% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 8 0.01% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13703 1 0.00% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 12 0.02% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 2 0.00% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 2 0.00% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 25 0.04% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14151 1 0.00% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 180 0.25% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 23 0.03% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 2 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 22 0.03% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 213 0.30% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 85.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 15 0.02% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 2 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 5 0.01% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15943 1 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 4 0.01% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16199 3 0.00% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16327 1 0.00% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 278 0.39% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 6 0.01% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 6 0.01% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 16 0.02% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 2 0.00% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 4 0.01% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 216 0.30% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 4 0.01% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 28 0.04% 86.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 6 0.01% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18112-18119 2 0.00% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 20 0.03% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 175 0.25% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 21 0.03% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 2 0.00% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 11 0.02% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 12 0.02% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 2 0.00% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 153 0.22% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 2 0.00% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 76 0.11% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19776-19783 4 0.01% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19847 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 33 0.05% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 20 0.03% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 171 0.24% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 75 0.11% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 17 0.02% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 3 0.00% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 73 0.10% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21568-21575 1 0.00% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 2 0.00% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 12 0.02% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22080-22087 1 0.00% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22208-22215 2 0.00% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 88 0.12% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 2 0.00% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 73 0.10% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22663 3 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 94 0.13% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.09% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 18 0.03% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 2 0.00% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23744-23751 1 0.00% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 82 0.12% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 73 0.10% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 24 0.03% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24512-24519 1 0.00% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 150 0.21% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 1 0.00% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 25 0.04% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 68 0.10% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 86 0.12% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25536-25543 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 20 0.03% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 14 0.02% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 3 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 69 0.10% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 2 0.00% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 93 0.13% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 75 0.11% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 84 0.12% 89.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27072-27079 1 0.00% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 14 0.02% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27335 2 0.00% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 75 0.11% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 77 0.11% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27719 1 0.00% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27847 1 0.00% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 16 0.02% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 1 0.00% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28103 1 0.00% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 8 0.01% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 2 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 75 0.11% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 176 0.25% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 20 0.03% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29056-29063 2 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 31 0.04% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29383 3 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 76 0.11% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 149 0.21% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 90.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 2 0.00% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 7 0.01% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 23 0.03% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 175 0.25% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 2 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 6 0.01% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 19 0.03% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 4 0.01% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31367 1 0.00% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 24 0.03% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 2 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 210 0.30% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31815 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 5 0.01% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 5 0.01% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 2 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 275 0.39% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 4 0.01% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 5 0.01% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 21 0.03% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33671 4 0.01% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 214 0.30% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 20 0.03% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 2 0.00% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 21 0.03% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 167 0.24% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 18 0.03% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 7 0.01% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35456-35463 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35520-35527 1 0.00% 92.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 147 0.21% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35975 1 0.00% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 73 0.10% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36160-36167 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 29 0.04% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36416-36423 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 20 0.03% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 174 0.25% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 72 0.10% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 7 0.01% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 17 0.02% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37696-37703 2 0.00% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 76 0.11% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 72 0.10% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 83 0.12% 93.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 77 0.11% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 93 0.13% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39360-39367 1 0.00% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.09% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 10 0.01% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 17 0.02% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40007 2 0.00% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40128-40135 1 0.00% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 82 0.12% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40263 1 0.00% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 23 0.03% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40896-40903 1 0.00% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 150 0.21% 94.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41024-41031 1 0.00% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41088-41095 1 0.00% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 2 0.00% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 70 0.10% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41536-41543 1 0.00% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41671 1 0.00% 94.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 82 0.12% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41792-41799 1 0.00% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 16 0.02% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 13 0.02% 94.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 66 0.09% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 92 0.13% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 75 0.11% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 86 0.12% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 74 0.10% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 2 0.00% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 73 0.10% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 3 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 16 0.02% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 9 0.01% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44608-44615 2 0.00% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 74 0.10% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 4 0.01% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 173 0.24% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 1 0.00% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 96.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 19 0.03% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 34 0.05% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 76 0.11% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 150 0.21% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 8 0.01% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 9 0.01% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 17 0.02% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 174 0.25% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 22 0.03% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 2 0.00% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 3 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 21 0.03% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 208 0.29% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 12 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 4 0.01% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 10 0.01% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2000 2.82% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49280-49287 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50048-50055 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50183 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50304-50311 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation 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10 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 14 0.02% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 93 0.10% 63.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 22 0.02% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 7 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 109 0.12% 64.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 11 0.01% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 9 0.01% 64.04% # Bytes accessed per row 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15 0.02% 65.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 4 0.00% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 300 0.33% 66.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 4 0.00% 66.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 14 0.02% 66.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 2 0.00% 66.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 89 0.10% 66.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 2 0.00% 66.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 8 0.01% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 160 0.17% 66.44% # Bytes accessed per row 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0.01% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 9 0.01% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8135 1 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 397 0.43% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8327 1 0.00% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8391 1 0.00% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 85 0.09% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8519 1 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8583 2 0.00% 67.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 6 0.01% 67.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8775 1 0.00% 67.93% # Bytes accessed per row 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+system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 148 0.16% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 453 0.49% 90.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42112-42119 3 0.00% 90.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 24 0.03% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 1 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 142 0.15% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42560-42567 1 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 2 0.00% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 76 0.08% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 275 0.30% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 88 0.10% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 89 0.10% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 3 0.00% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 6 0.01% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43968-43975 2 0.00% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 468 0.51% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 137 0.15% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 25 0.03% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44736-44743 1 0.00% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 78 0.09% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 2 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 347 0.38% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 91 0.10% 92.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 1 0.00% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45504-45511 1 0.00% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 81 0.09% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45760-45767 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46016-46023 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 326 0.36% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 68 0.07% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46400-46407 1 0.00% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 144 0.16% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 21 0.02% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 330 0.36% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 2 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 85 0.09% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 2 0.00% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.43% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 77 0.08% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 140 0.15% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 56 0.06% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 70 0.08% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5010 5.47% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50112-50119 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50247 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation -system.physmem.totQLat 151784626000 # Total ticks spent queuing -system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks -system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::51776-51783 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52032-52039 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91629 # Bytes accessed per row activation +system.physmem.totQLat 370859657500 # Total ticks spent queuing +system.physmem.totMemAccLat 464833837500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76318685000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17655495000 # Total ticks spent accessing banks +system.physmem.avgQLat 24296.78 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.70 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30453.48 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.87 # Data bus utilization in percentage -system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing -system.physmem.readRowHits 6167948 # Number of row buffer hits during reads -system.physmem.writeRowHits 98004 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes -system.physmem.avgGap 156007.30 # Average gap between requests -system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.busUtil 2.95 # Data bus utilization in percentage +system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 12.21 # Average write queue length when enqueuing +system.physmem.readRowHits 15189856 # Number of row buffer hits during reads +system.physmem.writeRowHits 98161 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.68 # Row buffer hit rate for writes +system.physmem.avgGap 161575.49 # Average gap between requests +system.physmem.pageHitRate 99.40 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.44 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -743,308 +784,308 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62368825 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306736 # Transaction distribution -system.membus.trans_dist::ReadResp 7306736 # Transaction distribution -system.membus.trans_dist::WriteReq 767886 # Transaction distribution -system.membus.trans_dist::WriteResp 767886 # Transaction distribution -system.membus.trans_dist::Writeback 66680 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution -system.membus.trans_dist::ReadExReq 138080 # Transaction distribution -system.membus.trans_dist::ReadExResp 137692 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54229250 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352579 # Transaction distribution +system.membus.trans_dist::ReadResp 16352579 # Transaction distribution +system.membus.trans_dist::WriteReq 769165 # Transaction distribution +system.membus.trans_dist::WriteResp 769165 # Transaction distribution +system.membus.trans_dist::Writeback 66909 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35978 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14191 # Transaction distribution +system.membus.trans_dist::ReadExReq 138286 # Transaction distribution +system.membus.trans_dist::ReadExResp 137908 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384274 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13828 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1977266 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4377428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34655060 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392545 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27656 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68902967 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17766916 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20191657 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 141302185 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141302185 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1488154000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11766000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17661743000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4847485258 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 34183780195 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72740 # number of replacements -system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use -system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. +system.l2c.tags.replacements 73073 # number of replacements +system.l2c.tags.tagsinuse 53003.397460 # Cycle average of tags in use +system.l2c.tags.total_refs 1874154 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 138227 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.558523 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37718.016524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.174616 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4163.072469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2965.510583 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.620056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4041.319246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4099.683602 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575531 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65179 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8680 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53038 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994553 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18564692 # Number of tag accesses -system.l2c.tags.data_accesses 18564692 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits -system.l2c.Writeback_hits::total 581363 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2082 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 140 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48345 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58632 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106977 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22002 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4348 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 385872 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31083 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5052 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589425 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256959 # number of demand (read+write) hits -system.l2c.demand_hits::total 1509630 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22002 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4348 # number of overall hits -system.l2c.overall_hits::cpu0.inst 385872 # number of overall hits -system.l2c.overall_hits::cpu0.data 214889 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31083 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5052 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589425 # number of overall hits -system.l2c.overall_hits::cpu1.data 256959 # number of overall hits -system.l2c.overall_hits::total 1509630 # number of overall hits +system.l2c.tags.occ_percent::cpu0.inst 0.063523 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045250 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061666 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808768 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9065 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52647 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18858156 # Number of tag accesses +system.l2c.tags.data_accesses 18858156 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 22538 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4343 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 393811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 33531 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5781 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 608221 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201520 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435370 # number of ReadReq hits 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of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 213519 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 33531 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5781 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 608221 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260777 # number of demand (read+write) hits +system.l2c.demand_hits::total 1542521 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22538 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4343 # number of overall hits +system.l2c.overall_hits::cpu0.inst 393811 # number of overall hits +system.l2c.overall_hits::cpu0.data 213519 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 33531 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5781 # number of overall hits +system.l2c.overall_hits::cpu1.inst 608221 # number of overall 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# number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10174 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 769 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 591 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1360 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63376 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77189 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140565 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6278 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69669 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 13 # number of demand (read+write) misses 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cycles +system.l2c.overall_mshr_uncacheable_latency::total 184809236629 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030339 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017311 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.831882 # mshr miss rate for UpgradeReq accesses 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+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097077 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000576 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015037 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010807 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097077 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62624.185603 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64978.710593 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63169.691897 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.441012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.003150 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10046.641734 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.247074 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10034.830795 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.537500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57556.376578 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66635.430152 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62541.992246 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58014.137163 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66510.305611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62637.695892 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 88019.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 211750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61572.105788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58014.137163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 112875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63201.956358 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66510.305611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62637.695892 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1235,67 +1276,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136617428 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146120255 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) +system.toL2Bus.throughput 58740655 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2741580 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2741579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769165 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769165 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583255 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35242 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18671 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259438 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259438 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073661 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13619 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56672 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1230417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15509 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 76068 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8087268 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25596864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34696353 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90204 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39355008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48247560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 134188 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148160681 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148160681 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4896624 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4922304939 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1803966688 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1516604948 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9296947 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34267946 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46298079 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution -system.iobus.trans_dist::WriteReq 7945 # Transaction distribution -system.iobus.trans_dist::WriteResp 7945 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer6.occupancy 2771620829 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 3258153300 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 9753444 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer9.occupancy 42798427 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 47398269 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322887 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322887 # Transaction distribution +system.iobus.trans_dist::WriteReq 8066 # Transaction distribution +system.iobus.trans_dist::WriteResp 8066 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1312,17 +1353,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384274 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32661906 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17692 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1339,27 +1380,27 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148551 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 2392545 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123503073 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503073 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4429000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -1390,44 +1431,86 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 5998612 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits +system.iobus.respLayer0.occupancy 2376208000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 41458010805 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.branchPred.lookups 6118154 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4670367 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295970 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3816631 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2949053 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.268486 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 684315 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28445 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8906772 # DTB read hits -system.cpu0.dtb.read_misses 28714 # DTB read misses -system.cpu0.dtb.write_hits 5141355 # DTB write hits -system.cpu0.dtb.write_misses 5491 # DTB write misses +system.cpu0.dtb.read_hits 8969635 # DTB read hits +system.cpu0.dtb.read_misses 28952 # DTB read misses +system.cpu0.dtb.write_hits 5211846 # DTB write hits +system.cpu0.dtb.write_misses 5698 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1738 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 275 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8935486 # DTB read accesses -system.cpu0.dtb.write_accesses 5146846 # DTB write accesses +system.cpu0.dtb.perms_faults 590 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8998587 # DTB read accesses +system.cpu0.dtb.write_accesses 5217544 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14048127 # DTB hits -system.cpu0.dtb.misses 34205 # DTB misses -system.cpu0.dtb.accesses 14082332 # DTB accesses -system.cpu0.itb.inst_hits 4217878 # ITB inst hits -system.cpu0.itb.inst_misses 5102 # ITB inst misses +system.cpu0.dtb.hits 14181481 # DTB hits +system.cpu0.dtb.misses 34650 # DTB misses +system.cpu0.dtb.accesses 14216131 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 4279077 # ITB inst hits +system.cpu0.itb.inst_misses 5117 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1436,545 +1519,549 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1212 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1385 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses -system.cpu0.itb.hits 4217878 # DTB hits -system.cpu0.itb.misses 5102 # DTB misses -system.cpu0.itb.accesses 4222980 # DTB accesses -system.cpu0.numCycles 69399845 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4284194 # ITB inst accesses +system.cpu0.itb.hits 4279077 # DTB hits +system.cpu0.itb.misses 5117 # DTB misses +system.cpu0.itb.accesses 4284194 # DTB accesses +system.cpu0.numCycles 70223968 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11927082 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32438478 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6118154 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3633368 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7610656 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1458202 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60559 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20342851 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5497 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47160 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1383184 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4277582 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 158526 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2073 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42423154 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988026 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.369139 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34819772 82.08% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 571665 1.35% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825898 1.95% 85.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 684492 1.61% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 779946 1.84% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 566234 1.33% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 677676 1.60% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 358556 0.85% 92.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3138915 7.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42423154 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087123 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461929 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12476093 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21540045 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6871897 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 553157 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 981962 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 949644 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64975 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40551006 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213850 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 981962 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13051542 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5910563 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13528575 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6803012 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2147500 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39435352 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 334 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 441883 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1170709 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 119 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39847910 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 180543493 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 163844376 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4138 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31495709 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8352200 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 460642 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 417076 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5513022 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7756413 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5773431 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120554 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1217575 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37342460 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 905810 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37712626 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 83166 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6296628 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13228023 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256791 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42423154 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888963 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506683 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27070740 63.81% 63.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5892236 13.89% 77.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3160742 7.45% 85.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2473733 5.83% 90.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2116122 4.99% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 945480 2.23% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 519157 1.22% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188675 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56269 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42423154 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27921 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 464 0.04% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839960 77.98% 80.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208811 19.39% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22686320 60.16% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48095 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9430202 25.01% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5532744 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued -system.cpu0.iq.rate 0.536728 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37712626 # Type of FU issued +system.cpu0.iq.rate 0.537034 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1077156 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028562 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119034571 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44552771 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34849273 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8516 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4702 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38770775 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4456 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316259 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1371122 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2677 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13108 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538058 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149551 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5893 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 981962 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4290254 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 101346 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38366333 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 82356 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7756413 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5773431 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 579216 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40773 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5894 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13108 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150282 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117544 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267826 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37333576 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9286892 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117147 # number of nop insts executed -system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4855012 # Number of branches executed -system.cpu0.iew.exec_stores 5401246 # Number of stores executed -system.cpu0.iew.exec_rate 0.531281 # Inst execution rate -system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18314277 # num instructions producing a value -system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value +system.cpu0.iew.exec_nop 118063 # number of nop insts executed +system.cpu0.iew.exec_refs 14771553 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4961106 # Number of branches executed +system.cpu0.iew.exec_stores 5484661 # Number of stores executed +system.cpu0.iew.exec_rate 0.531636 # Inst execution rate +system.cpu0.iew.wb_sent 37138785 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34853166 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18592793 # num instructions producing a value +system.cpu0.iew.wb_consumers 35689861 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496314 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520954 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6112781 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 649019 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232084 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41441192 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.767334 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727698 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29493448 71.17% 71.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5926009 14.30% 85.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1935659 4.67% 90.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1007052 2.43% 92.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 761622 1.84% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 520069 1.25% 95.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 411110 0.99% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 222523 0.54% 97.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1163700 2.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23685352 # Number of instructions committed -system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41441192 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24076968 # Number of instructions committed +system.cpu0.commit.committedOps 31799237 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11431143 # Number of memory references committed -system.cpu0.commit.loads 6279002 # Number of loads committed -system.cpu0.commit.membars 229688 # Number of memory barriers committed -system.cpu0.commit.branches 4246153 # Number of branches committed +system.cpu0.commit.refs 11620664 # Number of memory references committed +system.cpu0.commit.loads 6385291 # Number of loads committed +system.cpu0.commit.membars 231891 # Number of memory barriers committed +system.cpu0.commit.branches 4352331 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489419 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28144226 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499126 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1163700 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75718589 # The number of ROB reads -system.cpu0.rob.rob_writes 75736714 # The number of ROB writes -system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23604610 # Number of Instructions Simulated -system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated -system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads -system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads -system.cpu0.fp_regfile_writes 904 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13200315 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451289 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392190 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 77320455 # The number of ROB reads +system.cpu0.rob.rob_writes 76807713 # The number of ROB writes +system.cpu0.timesIdled 366523 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27800814 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5141023759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23996226 # Number of Instructions Simulated +system.cpu0.committedOps 31718495 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23996226 # Number of Instructions Simulated +system.cpu0.cpi 2.926459 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.926459 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341710 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341710 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174280890 # number of integer regfile reads +system.cpu0.int_regfile_writes 34606104 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3371 # number of floating regfile reads +system.cpu0.fp_regfile_writes 930 # number of floating regfile writes +system.cpu0.misc_regfile_reads 79193882 # number of misc regfile reads +system.cpu0.misc_regfile_writes 501030 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399855 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.561575 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3845551 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 400367 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.605065 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7054920250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.561575 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999144 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4608911 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4608911 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits -system.cpu0.icache.overall_hits::total 3792228 # number of overall hits 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-system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for 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12167.221883 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276315 # number of replacements -system.cpu0.dcache.tags.tagsinuse 459.475838 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9261350 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276827 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.455371 # Average number of references to valid blocks. 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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 45818436 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45818436 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5876487 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5876487 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3229447 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3229447 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139508 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139508 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137243 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137243 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9105934 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9105934 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9105934 # number of overall hits +system.cpu0.dcache.overall_hits::total 9105934 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392643 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392643 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584583 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584583 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8921 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8921 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7758 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7758 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977226 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977226 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977226 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977226 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519657990 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5519657990 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80059065889 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80059065889 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91816480 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 91816480 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49938268 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 49938268 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85578723879 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85578723879 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85578723879 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85578723879 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269130 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6269130 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4814030 # number of WriteReq accesses(hits+misses) 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+system.cpu0.dcache.ReadReq_miss_rate::total 0.062631 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329159 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.329159 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060103 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060103 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053503 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053503 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178399 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178399 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178399 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178399 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14057.701245 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14057.701245 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50523.744032 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50523.744032 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10292.173523 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10292.173523 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6437.002836 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6437.002836 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43282.216539 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43282.216539 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43282.216539 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9306 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7994 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 611 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 137 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.230769 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 58.350365 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks -system.cpu0.dcache.writebacks::total 256502 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255436 # number of writebacks +system.cpu0.dcache.writebacks::total 255436 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203336 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203336 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453472 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453472 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656808 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656808 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656808 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656808 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189307 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189307 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131111 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131111 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8437 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320418 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320418 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320418 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2405173678 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2405173678 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5317055578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5317055578 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69940520 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69940520 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34423732 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34423732 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7722229256 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7722229256 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7722229256 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7722229256 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13428836532 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13428836532 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1202345879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1202345879 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631182411 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631182411 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030197 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030197 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056842 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056842 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053503 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053503 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.149192 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.149192 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40553.848098 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40553.848098 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8289.738059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8289.738059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4437.191544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4437.191544 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24100.485166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24100.485166 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1982,38 +2069,80 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8777296 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits +system.cpu1.branchPred.lookups 9295999 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7633656 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 416141 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5924050 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5051274 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.267241 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 796895 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43453 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42697243 # DTB read hits -system.cpu1.dtb.read_misses 36228 # DTB read misses -system.cpu1.dtb.write_hits 6821056 # DTB write hits -system.cpu1.dtb.write_misses 10680 # DTB write misses +system.cpu1.dtb.read_hits 42971577 # DTB read hits +system.cpu1.dtb.read_misses 38230 # DTB read misses +system.cpu1.dtb.write_hits 6978417 # DTB write hits +system.cpu1.dtb.write_misses 10824 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2766 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42733471 # DTB read accesses -system.cpu1.dtb.write_accesses 6831736 # DTB write accesses +system.cpu1.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43009807 # DTB read accesses +system.cpu1.dtb.write_accesses 6989241 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49518299 # DTB hits -system.cpu1.dtb.misses 46908 # DTB misses -system.cpu1.dtb.accesses 49565207 # DTB accesses -system.cpu1.itb.inst_hits 7578630 # ITB inst hits -system.cpu1.itb.inst_misses 5358 # ITB inst misses +system.cpu1.dtb.hits 49949994 # DTB hits +system.cpu1.dtb.misses 49054 # DTB misses +system.cpu1.dtb.accesses 49999048 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 7718441 # ITB inst hits +system.cpu1.itb.inst_misses 5545 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2022,114 +2151,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1355 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses -system.cpu1.itb.hits 7578630 # DTB hits -system.cpu1.itb.misses 5358 # DTB misses -system.cpu1.itb.accesses 7583988 # DTB accesses -system.cpu1.numCycles 409868912 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7723986 # ITB inst accesses +system.cpu1.itb.hits 7718441 # DTB hits +system.cpu1.itb.misses 5545 # DTB misses +system.cpu1.itb.accesses 7723986 # DTB accesses +system.cpu1.numCycles 413843853 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19379988 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61315433 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9295999 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5848169 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13365504 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3344948 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69502 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 81000911 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 40728 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1501346 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7716683 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 552961 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117651923 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.637947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.959423 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 104293797 88.65% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 816533 0.69% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 959642 0.82% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1712278 1.46% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1420540 1.21% 92.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586826 0.50% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1954913 1.66% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 421869 0.36% 95.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5485525 4.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117651923 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022463 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.148161 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20970716 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 81766548 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11917801 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 808551 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2188307 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1138241 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 101191 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71099803 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336135 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2188307 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22164827 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33899952 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 43340583 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11475244 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4583010 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67141114 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 681863 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3070840 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 445 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70764915 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 313106059 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 286755701 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6517 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50418755 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20346160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 765693 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 705478 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8425217 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12844634 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8117566 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1057819 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1511606 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61861483 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1182497 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88912346 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94590 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13560397 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36234299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 282991 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117651923 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.755724 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.498826 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86792358 73.77% 73.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9289300 7.90% 81.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4170595 3.54% 85.21% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3605495 3.06% 88.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10372617 8.82% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1993778 1.69% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1066938 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282351 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78491 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117651923 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32498 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 992 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2157,406 +2286,405 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572169 95.70% 96.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 306556 3.87% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14270 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37625981 42.32% 42.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61252 0.07% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43860086 49.33% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7349035 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued -system.cpu1.iq.rate 0.214000 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88912346 # Type of FU issued +system.cpu1.iq.rate 0.214845 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7912215 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088989 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303516932 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76613298 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54268341 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15366 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8022 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96802135 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8156 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 354682 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2862502 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4198 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17495 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1113245 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965664 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675731 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2188307 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26389520 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363046 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63147070 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115346 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12844634 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8117566 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 886491 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65999 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3974 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17495 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203953 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158404 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 362357 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87176512 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43353711 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1735834 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104468 # number of nop insts executed -system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6912361 # Number of branches executed -system.cpu1.iew.exec_stores 7107436 # Number of stores executed -system.cpu1.iew.exec_rate 0.209797 # Inst execution rate -system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29705560 # num instructions producing a value -system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value +system.cpu1.iew.exec_nop 103090 # number of nop insts executed +system.cpu1.iew.exec_refs 50638153 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7380246 # Number of branches executed +system.cpu1.iew.exec_stores 7284442 # Number of stores executed +system.cpu1.iew.exec_rate 0.210651 # Inst execution rate +system.cpu1.iew.wb_sent 86413088 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54275144 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30296614 # num instructions producing a value +system.cpu1.iew.wb_consumers 53882453 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131149 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.562272 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13436842 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899506 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 316660 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 115463616 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.426258 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.378914 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97442898 84.39% 84.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9592965 8.31% 92.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2168696 1.88% 94.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1301481 1.13% 95.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 990246 0.86% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 587576 0.51% 97.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1009945 0.87% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 534541 0.46% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1835268 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38065286 # Number of instructions committed -system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 115463616 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38874177 # Number of instructions committed +system.cpu1.commit.committedOps 49217265 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595591 # Number of memory references committed -system.cpu1.commit.loads 9755506 # Number of loads committed -system.cpu1.commit.membars 190120 # Number of memory barriers committed -system.cpu1.commit.branches 5967745 # Number of branches committed +system.cpu1.commit.refs 16986453 # Number of memory references committed +system.cpu1.commit.loads 9982132 # Number of loads committed +system.cpu1.commit.membars 195521 # Number of memory barriers committed +system.cpu1.commit.branches 6425226 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534627 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43929395 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553319 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1835268 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170668638 # The number of ROB reads -system.cpu1.rob.rob_writes 125130415 # The number of ROB writes -system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995647 # Number of Instructions Simulated -system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated -system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads -system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18630847 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405526 # number of misc regfile writes -system.cpu1.icache.tags.replacements 595825 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 175215898 # The number of ROB reads +system.cpu1.rob.rob_writes 127579322 # The number of ROB writes +system.cpu1.timesIdled 1429072 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296191930 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796799037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38804538 # Number of Instructions Simulated +system.cpu1.committedOps 49147626 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38804538 # Number of Instructions Simulated +system.cpu1.cpi 10.664831 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.664831 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093766 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093766 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391691607 # number of integer regfile reads +system.cpu1.int_regfile_writes 56383706 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5043 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes +system.cpu1.misc_regfile_reads 202850334 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723182 # number of misc regfile writes +system.cpu1.icache.tags.replacements 614906 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.718219 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7054617 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 615418 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.463131 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74929846000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.718219 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974059 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974059 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8173146 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8173146 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits -system.cpu1.icache.overall_hits::total 6935518 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses -system.cpu1.icache.overall_misses::total 641267 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7576785 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7576785 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084636 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084636 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084636 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084636 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084636 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084636 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.847232 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.847232 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 8332076 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8332076 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7054617 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7054617 # number of ReadReq hits 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overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13594.240510 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3570 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 201 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 17.761194 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed 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-system.cpu1.icache.overall_mshr_misses::total 596361 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7105400062 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7105400062 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7105400062 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7105400062 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7105400062 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7105400062 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3356250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3356250 # number of ReadReq MSHR uncacheable cycles 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average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.595458 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.595458 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46567 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46567 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46567 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46567 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46567 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46567 # number of overall MSHR hits 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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360794 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.291027 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12676660 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361148 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.101011 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 58866831 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 58866831 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits 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-system.cpu1.dcache.WriteReq_misses::total 1557491 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13987 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13987 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10584 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10584 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1954702 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1954702 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1954702 # number of overall misses -system.cpu1.dcache.overall_misses::total 1954702 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6036826508 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6036826508 # number of ReadReq miss cycles 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accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14403417 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14403417 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045621 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045621 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273409 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273409 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125382 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125382 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15198.034566 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15198.034566 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51471.767133 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 51471.767133 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9228.068349 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9228.068349 # average LoadLockedReq miss latency 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8.877166 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 115.630952 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 363287 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.536511 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13021437 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363669 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.805738 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70976822000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.536511 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.948313 # Average percentage of cache occupancy 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miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58221587 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58221587 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 85588964443 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 85588964443 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 85588964443 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 85588964443 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8917519 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8917519 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837875 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5837875 # number of WriteReq accesses(hits+misses) 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15225.892656 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15225.892656 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50674.957979 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 50674.957979 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9222.854734 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9222.854734 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5334.089510 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5334.089510 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43434.775971 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 43434.775971 # average overall miss latency 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-system.cpu1.dcache.writebacks::total 324862 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits 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389987 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327819 # number of writebacks +system.cpu1.dcache.writebacks::total 327819 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171130 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171130 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1404670 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1404670 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1454 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1575800 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1575800 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1575800 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1575800 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231332 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231332 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163385 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163385 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10915 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10915 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394717 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394717 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394717 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394717 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2884558137 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2884558137 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7099464771 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7099464771 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89380256 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89380256 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36390413 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36390413 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9984022908 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9984022908 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9984022908 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9984022908 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231255506 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231255506 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25855700445 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25855700445 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195086955951 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195086955951 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025941 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025941 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027987 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111609 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111609 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101064 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101064 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026751 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026751 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026751 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12469.343355 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12469.343355 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43452.365707 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43452.365707 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7026.749686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7026.749686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3333.981951 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3333.981951 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25294.129485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25294.129485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2580,18 +2708,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1519279146805 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519279146805 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1519279146805 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42657 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50405 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 276d3e895..9bc002187 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -224,10 +236,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -235,6 +272,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -589,24 +627,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -614,6 +688,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -662,7 +737,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 41742298b..9dee17aa2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index d1ec33d4f..9a2da36f9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:04:18 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:42:01 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x6dd8800 0x6dd8800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2525131633500 because m5_exit instruction encountered +Exiting @ tick 2526146947500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6bfde3aab..bbb1c38b2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525132 # Number of seconds simulated -sim_ticks 2525131633500 # Number of ticks simulated -final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526147 # Number of seconds simulated +sim_ticks 2526146947500 # Number of ticks simulated +final_tick 2526146947500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76415 # Simulator instruction rate (inst/s) -host_op_rate 98325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3199664494 # Simulator tick rate (ticks/s) -host_mem_usage 402400 # Number of bytes of host memory used -host_seconds 789.19 # Real time elapsed on the host -sim_insts 60305678 # Number of instructions simulated -sim_ops 77596684 # Number of ops (including micro ops) simulated +host_inst_rate 69975 # Simulator instruction rate (inst/s) +host_op_rate 90038 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2931166527 # Simulator tick rate (ticks/s) +host_mem_usage 424336 # Number of bytes of host memory used +host_seconds 861.82 # Real time elapsed on the host +sim_insts 60306154 # Number of instructions simulated +sim_ops 77597242 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093720 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782528 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798600 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59102 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813120 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47320155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1317 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3599838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1497351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1497351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47320155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1317 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813149 # Number of write requests accepted -system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue -system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943580 # Per bank write bursts -system.physmem.perBankRdBursts::1 943152 # Per bank write bursts -system.physmem.perBankRdBursts::2 939288 # Per bank write bursts -system.physmem.perBankRdBursts::3 939310 # Per bank write bursts -system.physmem.perBankRdBursts::4 943113 # Per bank write bursts -system.physmem.perBankRdBursts::5 943139 # Per bank write bursts -system.physmem.perBankRdBursts::6 939134 # Per bank write bursts -system.physmem.perBankRdBursts::7 938551 # Per bank write bursts -system.physmem.perBankRdBursts::8 944000 # Per bank write bursts -system.physmem.perBankRdBursts::9 943392 # Per bank write bursts -system.physmem.perBankRdBursts::10 938425 # Per bank write bursts -system.physmem.perBankRdBursts::11 937973 # Per bank write bursts -system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943534 # Per bank write bursts -system.physmem.perBankRdBursts::14 939230 # Per bank write bursts -system.physmem.perBankRdBursts::15 938669 # Per bank write bursts -system.physmem.perBankWrBursts::0 6703 # Per bank write bursts -system.physmem.perBankWrBursts::1 6464 # Per bank write bursts -system.physmem.perBankWrBursts::2 6595 # Per bank write bursts -system.physmem.perBankWrBursts::3 6634 # Per bank write bursts -system.physmem.perBankWrBursts::4 6559 # Per bank write bursts -system.physmem.perBankWrBursts::5 6792 # Per bank write bursts -system.physmem.perBankWrBursts::6 6793 # Per bank write bursts -system.physmem.perBankWrBursts::7 6730 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6539 # Per bank write bursts -system.physmem.perBankWrBursts::11 6181 # Per bank write bursts -system.physmem.perBankWrBursts::12 7151 # Per bank write bursts -system.physmem.perBankWrBursts::13 6766 # Per bank write bursts -system.physmem.perBankWrBursts::14 7035 # Per bank write bursts -system.physmem.perBankWrBursts::15 6897 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4793780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096836 # Number of read requests accepted +system.physmem.writeReqs 813120 # Number of write requests accepted +system.physmem.readBursts 15096836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813120 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 963731584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2465920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6899264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129431576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6798600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38530 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705302 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4683 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943582 # Per bank write bursts +system.physmem.perBankRdBursts::1 943071 # Per bank write bursts +system.physmem.perBankRdBursts::2 939289 # Per bank write bursts +system.physmem.perBankRdBursts::3 939279 # Per bank write bursts +system.physmem.perBankRdBursts::4 943119 # Per bank write bursts +system.physmem.perBankRdBursts::5 943242 # Per bank write bursts +system.physmem.perBankRdBursts::6 939090 # Per bank write bursts +system.physmem.perBankRdBursts::7 938633 # Per bank write bursts +system.physmem.perBankRdBursts::8 943981 # Per bank write bursts +system.physmem.perBankRdBursts::9 943506 # Per bank write bursts +system.physmem.perBankRdBursts::10 938534 # Per bank write bursts +system.physmem.perBankRdBursts::11 937721 # Per bank write bursts +system.physmem.perBankRdBursts::12 943933 # Per bank write bursts +system.physmem.perBankRdBursts::13 943406 # Per bank write bursts +system.physmem.perBankRdBursts::14 939034 # Per bank write bursts +system.physmem.perBankRdBursts::15 938886 # Per bank write bursts +system.physmem.perBankWrBursts::0 6687 # Per bank write bursts +system.physmem.perBankWrBursts::1 6452 # Per bank write bursts +system.physmem.perBankWrBursts::2 6617 # Per bank write bursts +system.physmem.perBankWrBursts::3 6618 # Per bank write bursts +system.physmem.perBankWrBursts::4 6551 # Per bank write bursts +system.physmem.perBankWrBursts::5 6799 # Per bank write bursts +system.physmem.perBankWrBursts::6 6798 # Per bank write bursts +system.physmem.perBankWrBursts::7 6724 # Per bank write bursts +system.physmem.perBankWrBursts::8 7121 # Per bank write bursts +system.physmem.perBankWrBursts::9 6870 # Per bank write bursts +system.physmem.perBankWrBursts::10 6536 # Per bank write bursts +system.physmem.perBankWrBursts::11 6184 # Per bank write bursts +system.physmem.perBankWrBursts::12 7152 # Per bank write bursts +system.physmem.perBankWrBursts::13 6752 # Per bank write bursts +system.physmem.perBankWrBursts::14 7039 # Per bank write bursts +system.physmem.perBankWrBursts::15 6901 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525130505500 # Total gap between requests +system.physmem.totGap 2526145872500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 36 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154599 # Read request sizes (log2) +system.physmem.readPktSize::6 154590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59131 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1174955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1121426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1077218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3628637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2607777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2593781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2599800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -145,616 +145,621 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11268.950798 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1000.903149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16775.480046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23607 27.41% 27.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14081 16.35% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2628 3.05% 46.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2075 2.41% 49.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1317 1.53% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1250 1.45% 52.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 847 0.98% 53.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 989 1.15% 54.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 557 0.65% 54.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 603 0.70% 55.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 514 0.60% 56.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 583 0.68% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 264 0.31% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 155 0.18% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 634 0.74% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 90 0.10% 58.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.17% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 77 0.09% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 121 0.14% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 516 0.60% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 33 0.04% 59.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 269 0.31% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 22 0.03% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 94 0.11% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 142 0.16% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 22 0.03% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 57 0.07% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 390 0.45% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 120 0.14% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 5 0.01% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 8 0.01% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 107 0.12% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 24 0.03% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 86 0.10% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 27 0.03% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11271.974916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1003.850407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16772.129499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23407 27.18% 27.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14160 16.44% 43.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2694 3.13% 46.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2155 2.50% 49.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1262 1.47% 50.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1178 1.37% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 892 1.04% 53.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1078 1.25% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 591 0.69% 55.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 609 0.71% 55.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 535 0.62% 56.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 547 0.64% 57.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 279 0.32% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 297 0.34% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 152 0.18% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 456 0.53% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 120 0.14% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 137 0.16% 58.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 61 0.07% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 169 0.20% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 508 0.59% 59.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 23 0.03% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 260 0.30% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 13 0.02% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 93 0.11% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 141 0.16% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 16 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 46 0.05% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 16 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 376 0.44% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 11 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 34 0.04% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 70 0.08% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 7 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 29 0.03% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 165 0.19% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 16 0.02% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 8 0.01% 61.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 175 0.20% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.02% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 17 0.02% 61.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008-3015 4 0.00% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 358 0.42% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 61.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.18% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 62.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 15 0.02% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 31 0.04% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 11 0.01% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 15 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 368 0.43% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 15 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 165 0.19% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 92 0.11% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 95 0.11% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 379 0.44% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 10 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 5 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.10% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 21 0.02% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 146 0.17% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 64.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 64 0.07% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 13 0.02% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 283 0.33% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 88 0.10% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 11 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 6 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 153 0.18% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 78 0.09% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 9 0.01% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 368 0.43% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 11 0.01% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 136 0.16% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 306 0.36% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 15 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 9 0.01% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 94 0.11% 61.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 11 0.01% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 22 0.03% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 5 0.01% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 99 0.11% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 8 0.01% 62.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 93 0.11% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 7 0.01% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 21 0.02% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 5 0.01% 62.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 365 0.42% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 12 0.01% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 7 0.01% 62.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 91 0.11% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 13 0.02% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 7 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 5 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 21 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.00% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 11 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 9 0.01% 62.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 161 0.19% 63.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 5 0.01% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 16 0.02% 63.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 409 0.47% 63.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 11 0.01% 63.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 9 0.01% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 13 0.02% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 56 0.07% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 5 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 15 0.02% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 63.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 79 0.09% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 63.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 9 0.01% 63.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 142 0.16% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 3 0.00% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 18 0.02% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.01% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 348 0.40% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 6 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 7 0.01% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 23 0.03% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6471 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 95 0.11% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 17 0.02% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 3 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 100 0.12% 64.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 11 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 7 0.01% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 484 0.56% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 7 0.01% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 86 0.10% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7495 3 0.00% 65.50% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7559 9 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 88 0.10% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 84 0.10% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 11 0.01% 65.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7623 2 0.00% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 27 0.03% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7815 10 0.01% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7879 1 0.00% 65.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 155 0.18% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 8 0.01% 65.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 389 0.45% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 78 0.09% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 130 0.15% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 355 0.41% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 2 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 73 0.08% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9543 1 0.00% 67.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 4 0.00% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 140 0.16% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 2 0.00% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 4 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 272 0.32% 67.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 15 0.02% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 67.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 132 0.15% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.09% 67.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 373 0.43% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 86 0.10% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 77 0.09% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 2 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 144 0.17% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 4 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 340 0.39% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 2 0.00% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.09% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::23552-23559 350 0.41% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 76.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 126 0.15% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 74 0.09% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24199 2 0.00% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 82 0.10% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.32% # Bytes accessed per row activation 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2 0.00% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 345 0.40% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10311 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10375 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 83 0.10% 67.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 68 0.08% 67.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10951 1 0.00% 67.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 39 0.05% 67.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11143 4 0.00% 67.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 396 0.46% 68.36% # Bytes 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activation +system.physmem.bytesPerActivate::12352-12359 1 0.00% 69.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12423 1 0.00% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 83 0.10% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12679 2 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12743 1 0.00% 69.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 81 0.09% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 70 0.08% 69.33% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::33792-33799 276 0.32% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 2 0.00% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 69 0.08% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34119 1 0.00% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 76 0.09% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 3 0.00% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 78 0.09% 84.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34752-34759 1 0.00% 84.53% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::36096-36103 68 0.08% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 82 0.10% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 3 0.00% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 85 0.10% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36800-36807 2 0.00% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 328 0.38% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 78 0.09% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37191 2 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 7 0.01% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 154 0.18% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 389 0.45% 87.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 41 0.05% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38272-38279 2 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38336-38343 1 0.00% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 63 0.07% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 83 0.10% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 332 0.39% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 17 0.02% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 81 0.09% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39552-39559 2 0.00% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 95 0.11% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 463 0.54% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 69 0.08% 88.47% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 16 0.02% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41536-41543 1 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 2 0.00% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 458 0.53% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42176-42183 1 0.00% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 90 0.10% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42304-42311 2 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42432-42439 1 0.00% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 82 0.10% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42624-42631 4 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 17 0.02% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42880-42887 2 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 331 0.38% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 81 0.09% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 64 0.07% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 37 0.04% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 395 0.46% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 150 0.17% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 2 0.00% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 10 0.01% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44608-44615 2 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 81 0.09% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 328 0.38% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 82 0.10% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 2 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 83 0.10% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 69 0.08% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 277 0.32% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46215 3 0.00% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 151 0.18% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 129 0.15% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46656-46663 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46784-46791 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 36 0.04% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 330 0.38% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 81 0.09% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 93.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 82 0.10% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 2 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 74 0.09% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 266 0.31% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 154 0.18% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 2 0.00% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 62 0.07% 94.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 129 0.15% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 4 0.00% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4946 5.74% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49927 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50048-50055 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50183 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50439 4 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50496-50503 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50567 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50624-50631 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50880-50887 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51264-51271 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation -system.physmem.totQLat 365453646000 # Total ticks spent queuing -system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks -system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52288-52295 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86110 # Bytes accessed per row activation +system.physmem.totQLat 365142496500 # Total ticks spent queuing +system.physmem.totMemAccLat 457904364000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75291530000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17470337500 # Total ticks spent accessing banks +system.physmem.avgQLat 24248.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1160.18 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30408.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing -system.physmem.readRowHits 14986798 # Number of row buffer hits during reads -system.physmem.writeRowHits 93332 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.37 # Average write queue length when enqueuing +system.physmem.readRowHits 14986658 # Number of row buffer hits during reads +system.physmem.writeRowHits 93339 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes -system.physmem.avgGap 158713.50 # Average gap between requests +system.physmem.writeRowHitRate 86.57 # Row buffer hit rate for writes +system.physmem.avgGap 158777.68 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.54 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -767,50 +772,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54900302 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149434 # Transaction distribution -system.membus.trans_dist::ReadResp 16149434 # Transaction distribution +system.membus.throughput 54877277 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149448 # Transaction distribution +system.membus.trans_dist::ReadResp 16149448 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59131 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution -system.membus.trans_dist::ReadExReq 131448 # Transaction distribution -system.membus.trans_dist::ReadExResp 131448 # Transaction distribution +system.membus.trans_dist::Writeback 59102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4681 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4683 # Transaction distribution +system.membus.trans_dist::ReadExReq 131427 # Transaction distribution +system.membus.trans_dist::ReadExResp 131427 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885760 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272466 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156882 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16692512 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19090401 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630489 # Total data (bytes) +system.membus.tot_pkt_size::total 138628065 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138628065 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486850000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3609000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17361408000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4731178629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737119450 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -818,7 +823,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285786 # Throughput (bytes/s) +system.iobus.throughput 48266379 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -928,41 +933,83 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921538550 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14384927 # Number of BP lookups -system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits +system.cpu.branchPred.lookups 14756776 # Number of BP lookups +system.cpu.branchPred.condPredicted 11839520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705876 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7667614 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.763270 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72469 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51182106 # DTB read hits -system.cpu.dtb.read_misses 64421 # DTB read misses -system.cpu.dtb.write_hits 11699698 # DTB write hits -system.cpu.dtb.write_misses 15824 # DTB write misses +system.cpu.dtb.read_hits 51181584 # DTB read hits +system.cpu.dtb.read_misses 65031 # DTB read misses +system.cpu.dtb.write_hits 11699885 # DTB write hits +system.cpu.dtb.write_misses 15694 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3476 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2524 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 396 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51246527 # DTB read accesses -system.cpu.dtb.write_accesses 11715522 # DTB write accesses +system.cpu.dtb.perms_faults 1369 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246615 # DTB read accesses +system.cpu.dtb.write_accesses 11715579 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62881804 # DTB hits -system.cpu.dtb.misses 80245 # DTB misses -system.cpu.dtb.accesses 62962049 # DTB accesses -system.cpu.itb.inst_hits 11522583 # ITB inst hits -system.cpu.itb.inst_misses 11276 # ITB inst misses +system.cpu.dtb.hits 62881469 # DTB hits +system.cpu.dtb.misses 80725 # DTB misses +system.cpu.dtb.accesses 62962194 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 11524718 # ITB inst hits +system.cpu.itb.inst_misses 11477 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -971,114 +1018,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2510 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2880 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11533859 # ITB inst accesses -system.cpu.itb.hits 11522583 # DTB hits -system.cpu.itb.misses 11276 # DTB misses -system.cpu.itb.accesses 11533859 # DTB accesses -system.cpu.numCycles 474898657 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536195 # ITB inst accesses +system.cpu.itb.hits 11524718 # DTB hits +system.cpu.itb.misses 11477 # DTB misses +system.cpu.itb.accesses 11536195 # DTB accesses +system.cpu.numCycles 477111575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29753545 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90325732 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14756776 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9065753 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20157040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4656007 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125616 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98208682 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2521 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2698608 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11521342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 709389 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.730167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134100120 86.94% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1306005 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712076 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296227 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2110153 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105630 0.72% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555237 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745864 0.48% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8310260 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154241572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030929 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31783151 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100076545 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1264474 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958594 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172374 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107306930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570435 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33521222 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38625715 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55163536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17589404 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6303518 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102301164 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 457 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4061695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 772 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106380900 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473930729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432790417 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10427 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78723244 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27657655 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170957 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1077143 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12622955 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19717794 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13303938 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1949827 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2475969 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95121483 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987498 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122914150 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18940781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47245549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505193 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154241572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109895599 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14389173 9.33% 80.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6873802 4.46% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5671511 3.68% 88.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12312296 7.98% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806335 1.82% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1696199 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 468469 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128188 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154241572 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62148 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available @@ -1106,437 +1153,436 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367826 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412812 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57963749 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93288 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52506877 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319545 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued -system.cpu.iq.rate 0.258806 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122914150 # Type of FU issued +system.cpu.iq.rate 0.257621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8842790 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409136453 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066186 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85476047 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23300 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131716001 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624558 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4063711 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6653 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30079 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572166 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107729 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30160267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434164 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97330281 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206491 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19717794 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13303938 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415153 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113233 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3362 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30079 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350155 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270547 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120836027 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2078123 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221761 # number of nop insts executed -system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475005 # Number of branches executed -system.cpu.iew.exec_stores 12211635 # Number of stores executed -system.cpu.iew.exec_rate 0.254432 # Inst execution rate -system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47031033 # num instructions producing a value -system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value +system.cpu.iew.exec_nop 221300 # number of nop insts executed +system.cpu.iew.exec_refs 64080526 # number of memory reference insts executed +system.cpu.iew.exec_branches 11821026 # Number of branches executed +system.cpu.iew.exec_stores 12211427 # Number of stores executed +system.cpu.iew.exec_rate 0.253266 # Inst execution rate +system.cpu.iew.wb_sent 119895169 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85486348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47016858 # num instructions producing a value +system.cpu.iew.wb_consumers 87565512 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179175 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18677700 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482305 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536038 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151203395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.514192 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.490223 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122740077 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14637973 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917047 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134429 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622101 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 972992 0.64% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598831 1.06% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 713641 0.47% 98.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2866304 1.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456059 # Number of instructions committed -system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151203395 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456535 # Number of instructions committed +system.cpu.commit.committedOps 77747623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385723 # Number of memory references committed -system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.refs 27385855 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed system.cpu.commit.membars 403571 # Number of memory barriers committed -system.cpu.commit.branches 9961071 # Number of branches committed +system.cpu.commit.branches 10305769 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. -system.cpu.commit.function_calls 991207 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69188185 # Number of committed integer instructions. +system.cpu.commit.function_calls 991209 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2866304 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240665808 # The number of ROB reads -system.cpu.rob.rob_writes 195946920 # The number of ROB writes -system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305678 # Number of Instructions Simulated -system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated -system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547244882 # number of integer regfile reads -system.cpu.int_regfile_writes 87532645 # number of integer regfile writes -system.cpu.fp_regfile_reads 8511 # number of floating regfile reads -system.cpu.fp_regfile_writes 2972 # number of floating regfile writes -system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads -system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution +system.cpu.rob.rob_reads 242914035 # The number of ROB reads +system.cpu.rob.rob_writes 195975439 # The number of ROB writes +system.cpu.timesIdled 1776357 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322870003 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575099289 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306154 # Number of Instructions Simulated +system.cpu.committedOps 77597242 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306154 # Number of Instructions Simulated +system.cpu.cpi 7.911491 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911491 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126398 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548607871 # number of integer regfile reads +system.cpu.int_regfile_writes 87541390 # number of integer regfile writes +system.cpu.fp_regfile_reads 8324 # number of floating regfile reads +system.cpu.fp_regfile_writes 2920 # number of floating regfile writes +system.cpu.misc_regfile_reads 268241142 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173227 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58865094 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658464 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658463 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62740736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85535129 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 210260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148527769 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148527769 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 199672 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129078659 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607582 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246158 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31363 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7917883 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62746624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85500065 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148505909 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148505909 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 195968 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128804200 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474541718 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474711974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550360089 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2550008218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20171491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20466481 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74593037 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74842560 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980798 # number of replacements -system.cpu.icache.tags.tagsinuse 511.579102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10457750 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981310 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.656928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 980909 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574447 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10459956 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.657970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6918965000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574447 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits -system.cpu.icache.overall_hits::total 10457750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061214 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061214 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061214 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061214 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061214 # number of overall misses -system.cpu.icache.overall_misses::total 1061214 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14272429649 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14272429649 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14272429649 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12502670 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12502670 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10459956 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10459956 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10459956 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10459956 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10459956 # number of overall hits +system.cpu.icache.overall_hits::total 10459956 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061258 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061258 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061258 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061258 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061258 # number of overall misses +system.cpu.icache.overall_misses::total 1061258 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14277146640 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14277146640 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14277146640 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14277146640 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14277146640 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521214 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11521214 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11521214 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11521214 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092113 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092113 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092113 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092113 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092113 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092113 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13453.040297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13453.040297 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13453.040297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13453.040297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13453.040297 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6445 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.181548 # average number of cycles each access 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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223398 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092607 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for overall accesses 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accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092504 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092504 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65360.576923 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.515972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63422.125669 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61918.540746 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61057.328845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63993.011163 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62425.679151 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.515972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63467.690735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63242.428641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61057.328845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61602.650471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.935414 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1657,13 +1703,13 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643483 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 643250 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21507454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643762 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.409015 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42602250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993295 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1671,154 +1717,154 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # 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-system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses -system.cpu.dcache.overall_misses::total 3700707 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles 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miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 181002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150242668881 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150242668881 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150242668881 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222062 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256262 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256262 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 24713543 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713543 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713543 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050810 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289882 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13601.527304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13601.527304 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47323.225182 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47323.225182 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13728.748524 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15083.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40611.570870 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40611.570870 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27549 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2688 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 281 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.851562 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.039146 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks -system.cpu.dcache.writebacks::total 607897 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065987 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065987 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385715 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385715 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249005 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249005 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12231 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607582 # number of writebacks +system.cpu.dcache.writebacks::total 607582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350850 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350850 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714158 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1320 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065008 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065008 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065008 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249031 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249031 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4975619608 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11323354786 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146514250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 156998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16298974394 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16298974394 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328293250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26845365872 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209173659122 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047732 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025674 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025674 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12908.096995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45469.659544 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11977.947188 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13083.166667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25688.064848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25688.064848 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1842,16 +1888,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499072952550 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499072952550 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499072952550 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83032 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index bf231cd78..b551f2cf3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus ioca atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,19 +325,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -277,10 +354,34 @@ system=system tracer=system.cpu1.tracer workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -288,6 +389,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -295,24 +397,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -320,6 +457,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -329,7 +467,7 @@ eventq_index=0 [system.cpu2] type=DerivO3CPU -children=branchPred dtb fuPool isa itb tracer +children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -355,6 +493,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu2.dstage2_mmu dtb=system.cpu2.dtb eventq_index=0 fetchBufferSize=64 @@ -373,6 +512,7 @@ interrupts=Null isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu2.istage2_mmu itb=system.cpu2.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -430,10 +570,34 @@ localPredictorSize=2048 numThreads=1 predType=tournament +[system.cpu2.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb +tlb=system.cpu2.dtb + +[system.cpu2.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.dstage2_mmu.stage2_tlb.walker + +[system.cpu2.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu2.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu2.dtb.walker @@ -441,6 +605,7 @@ walker=system.cpu2.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -755,24 +920,59 @@ opLat=3 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu2.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb +tlb=system.cpu2.itb + +[system.cpu2.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.istage2_mmu.stage2_tlb.walker + +[system.cpu2.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu2.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu2.itb.walker @@ -780,6 +980,7 @@ walker=system.cpu2.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -1418,7 +1619,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index d17b0e3b6..41d09e09d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -11,8 +11,16 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 05714643f..21d388ebd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,8 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:23:40 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:05:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index f17311f85..6f0228b0e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,172 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403659 # Number of seconds simulated -sim_ticks 2403658742000 # Number of ticks simulated -final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403670 # Number of seconds simulated +sim_ticks 2403669993000 # Number of ticks simulated +final_tick 2403669993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 228698 # Simulator instruction rate (inst/s) -host_op_rate 293732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9112018126 # Simulator tick rate (ticks/s) -host_mem_usage 403420 # Number of bytes of host memory used -host_seconds 263.79 # Real time elapsed on the host -sim_insts 60328128 # Number of instructions simulated -sim_ops 77483556 # Number of ops (including micro ops) simulated +host_inst_rate 205695 # Simulator instruction rate (inst/s) +host_op_rate 264190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8195476126 # Simulator tick rate (ticks/s) +host_mem_usage 425360 # Number of bytes of host memory used +host_seconds 293.29 # Real time elapsed on the host +sim_insts 60328724 # Number of instructions simulated +sim_ops 77484808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7049296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7062488 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 674944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1353888 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743872 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558256 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 64448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 676736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 184896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1338016 # Number of bytes read from this memory +system.physmem.bytes_read::total 124659200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 184896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 761928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3742720 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298604 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1557912 # Number of bytes written to this memory +system.physmem.bytes_written::total 6758536 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14210 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14221 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110387 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512409 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58498 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324564 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389564 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812452 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768458 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1007 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20914 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58480 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812434 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2938210 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 563261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540117 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648285 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 76922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 556655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51862028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213251 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 76922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557086 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768235 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3478469 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1211546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54675299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13477345 # Number of read requests accepted -system.physmem.writeReqs 446482 # Number of write requests accepted -system.physmem.readBursts 13477345 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446482 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 862550080 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 26812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 76922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1204794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54673785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13478692 # Number of read requests accepted +system.physmem.writeReqs 446310 # Number of write requests accepted +system.physmem.readBursts 13478692 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446310 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862636288 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2865536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109813728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2811448 # Total written bytes from the system interface side +system.physmem.bytesWritten 2859584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109811232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2805660 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401707 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2370 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837716 # Per bank write bursts -system.physmem.perBankRdBursts::1 837382 # Per bank write bursts -system.physmem.perBankRdBursts::2 837561 # Per bank write bursts -system.physmem.perBankRdBursts::3 838016 # Per bank write bursts -system.physmem.perBankRdBursts::4 839132 # Per bank write bursts -system.physmem.perBankRdBursts::5 839847 # Per bank write bursts -system.physmem.perBankRdBursts::6 839973 # Per bank write bursts -system.physmem.perBankRdBursts::7 841200 # Per bank write bursts -system.physmem.perBankRdBursts::8 842679 # Per bank write bursts -system.physmem.perBankRdBursts::9 845377 # Per bank write bursts -system.physmem.perBankRdBursts::10 845421 # Per bank write bursts -system.physmem.perBankRdBursts::11 845910 # Per bank write bursts -system.physmem.perBankRdBursts::12 847235 # Per bank write bursts -system.physmem.perBankRdBursts::13 846991 # Per bank write bursts -system.physmem.perBankRdBursts::14 846262 # Per bank write bursts -system.physmem.perBankRdBursts::15 846643 # Per bank write bursts -system.physmem.perBankWrBursts::0 2727 # Per bank write bursts -system.physmem.perBankWrBursts::1 2580 # Per bank write bursts -system.physmem.perBankWrBursts::2 2569 # Per bank write bursts -system.physmem.perBankWrBursts::3 3046 # Per bank write bursts -system.physmem.perBankWrBursts::4 3472 # Per bank write bursts +system.physmem.mergedWrBursts 401628 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2353 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837730 # Per bank write bursts +system.physmem.perBankRdBursts::1 837377 # Per bank write bursts +system.physmem.perBankRdBursts::2 837570 # Per bank write bursts +system.physmem.perBankRdBursts::3 838005 # Per bank write bursts +system.physmem.perBankRdBursts::4 839135 # Per bank write bursts +system.physmem.perBankRdBursts::5 839829 # Per bank write bursts +system.physmem.perBankRdBursts::6 839954 # Per bank write bursts +system.physmem.perBankRdBursts::7 841188 # Per bank write bursts +system.physmem.perBankRdBursts::8 842692 # Per bank write bursts +system.physmem.perBankRdBursts::9 845268 # Per bank write bursts +system.physmem.perBankRdBursts::10 845422 # Per bank write bursts +system.physmem.perBankRdBursts::11 845904 # Per bank write bursts +system.physmem.perBankRdBursts::12 847097 # Per bank write bursts +system.physmem.perBankRdBursts::13 848027 # Per bank write bursts +system.physmem.perBankRdBursts::14 846853 # Per bank write bursts +system.physmem.perBankRdBursts::15 846641 # Per bank write bursts +system.physmem.perBankWrBursts::0 2732 # Per bank write bursts +system.physmem.perBankWrBursts::1 2567 # Per bank write bursts +system.physmem.perBankWrBursts::2 2586 # Per bank write bursts +system.physmem.perBankWrBursts::3 3040 # Per bank write bursts +system.physmem.perBankWrBursts::4 3458 # Per bank write bursts system.physmem.perBankWrBursts::5 3199 # Per bank write bursts -system.physmem.perBankWrBursts::6 2543 # Per bank write bursts -system.physmem.perBankWrBursts::7 2318 # Per bank write bursts -system.physmem.perBankWrBursts::8 2233 # Per bank write bursts -system.physmem.perBankWrBursts::9 2426 # Per bank write bursts -system.physmem.perBankWrBursts::10 2368 # Per bank write bursts -system.physmem.perBankWrBursts::11 2824 # Per bank write bursts -system.physmem.perBankWrBursts::12 3814 # Per bank write bursts -system.physmem.perBankWrBursts::13 3447 # Per bank write bursts -system.physmem.perBankWrBursts::14 2652 # Per bank write bursts -system.physmem.perBankWrBursts::15 2556 # Per bank write bursts +system.physmem.perBankWrBursts::6 2529 # Per bank write bursts +system.physmem.perBankWrBursts::7 2312 # Per bank write bursts +system.physmem.perBankWrBursts::8 2235 # Per bank write bursts +system.physmem.perBankWrBursts::9 2402 # Per bank write bursts +system.physmem.perBankWrBursts::10 2375 # Per bank write bursts +system.physmem.perBankWrBursts::11 2809 # Per bank write bursts +system.physmem.perBankWrBursts::12 3726 # Per bank write bursts +system.physmem.perBankWrBursts::13 3500 # Per bank write bursts +system.physmem.perBankWrBursts::14 2647 # Per bank write bursts +system.physmem.perBankWrBursts::15 2564 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402623562000 # Total gap between requests +system.physmem.totGap 2402634752000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13441712 # Read request sizes (log2) +system.physmem.readPktSize::3 13443296 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35625 # Read request sizes (log2) +system.physmem.readPktSize::6 35388 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429390 # Write request sizes (log2) +system.physmem.writePktSize::2 429303 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17092 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 971418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 943230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3279616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2365953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2365403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2381873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 51923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17007 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 975684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 953327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 947696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3279847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2361574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2361279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2377764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 51807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -182,30 +178,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -214,312 +210,317 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17825.239135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3190.498487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18342.849091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8610 17.73% 17.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4856 10.00% 27.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 981 2.02% 29.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 733 1.51% 31.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 427 0.88% 32.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 370 0.76% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 272 0.56% 33.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 308 0.63% 34.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 164 0.34% 34.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 164 0.34% 34.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 166 0.34% 35.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 231 0.48% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 82 0.17% 35.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 88 0.18% 35.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 37 0.08% 36.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 306 0.63% 36.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 22 0.05% 36.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 33 0.07% 36.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 21 0.04% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 99 0.20% 37.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 20 0.04% 37.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 170 0.35% 37.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 13 0.03% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 137 0.28% 37.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 12 0.02% 37.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 29 0.06% 37.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 10 0.02% 37.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 139 0.29% 38.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 7 0.01% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 378 0.78% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 6 0.01% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 7 0.01% 38.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 70 0.14% 39.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 3 0.01% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 71 0.15% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 5 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 4 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 4 0.01% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 9 0.02% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 7 0.01% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 39.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 411 0.85% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 1 0.00% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 132 0.27% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 40.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 5 0.01% 40.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 3 0.01% 40.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 73 0.15% 40.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 384 0.79% 41.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 41.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 3 0.01% 41.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 131 0.27% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 8 0.02% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 2 0.00% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 2 0.00% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 68 0.14% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 5 0.01% 42.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 34 0.07% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 42.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 4 0.01% 42.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 263 0.54% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 3 0.01% 42.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 5 0.01% 42.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 131 0.27% 43.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 9 0.02% 43.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 3 0.01% 43.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 4 0.01% 43.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 43.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 4 0.01% 43.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 323 0.67% 44.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 3 0.01% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 7 0.01% 44.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 82 0.17% 44.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 44.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 4 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.01% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 2 0.00% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 292 0.60% 45.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 14 0.03% 45.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 4 0.01% 45.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 65 0.13% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 1 0.00% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 415 0.85% 46.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 291 0.60% 47.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 81 0.17% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 3 0.01% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 128 0.26% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 32 0.07% 49.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 64 0.13% 49.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 375 0.77% 50.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12615 1 0.00% 50.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 65 0.13% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 125 0.26% 50.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13127 1 0.00% 51.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 408 0.84% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 1 0.00% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 64 0.13% 51.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 364 0.75% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 52.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 98 0.20% 53.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 70 0.14% 53.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 256 0.53% 53.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 71 0.15% 54.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 644 1.33% 55.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 73 0.15% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16839 1 0.00% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 65 0.13% 55.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 256 0.53% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 68 0.14% 56.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 96 0.20% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 128 0.26% 57.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 364 0.75% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 64 0.13% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 407 0.84% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 376 0.77% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 127 0.26% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 29 0.06% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 128 0.26% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 3 0.01% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 82 0.17% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 129 0.27% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 414 0.85% 64.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 65 0.13% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 129 0.27% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 291 0.60% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 80 0.16% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 4 0.01% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 128 0.26% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 32 0.07% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 128 0.26% 67.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 377 0.78% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 68 0.14% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 68.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 65 0.13% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 125 0.26% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 410 0.84% 69.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 1 0.00% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 65 0.13% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 363 0.75% 70.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 96 0.20% 71.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 68 0.14% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 256 0.53% 72.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 72 0.15% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 72 0.15% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 63 0.13% 73.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 256 0.53% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 68 0.14% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 96 0.20% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 363 0.75% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 1 0.00% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 410 0.84% 76.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 125 0.26% 77.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 65 0.13% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 68 0.14% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 376 0.77% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 128 0.26% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 65 0.13% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 32 0.07% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 128 0.26% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 4 0.01% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 80 0.16% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 129 0.27% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 65 0.13% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 413 0.85% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 129 0.27% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 292 0.60% 83.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.17% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 3 0.01% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 128 0.26% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 29 0.06% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 127 0.26% 85.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 375 0.77% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 70 0.14% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45376-45383 1 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 406 0.84% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 64 0.13% 88.04% # Bytes accessed per row activation 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row activation +system.physmem.bytesPerActivate::64-71 8642 17.73% 17.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4876 10.00% 27.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 980 2.01% 29.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 745 1.53% 31.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 418 0.86% 32.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 375 0.77% 32.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 281 0.58% 33.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 311 0.64% 34.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 181 0.37% 34.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 171 0.35% 34.83% # Bytes accessed per row activation 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0.04% 37.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 158 0.32% 37.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 20 0.04% 37.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 128 0.26% 37.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 11 0.02% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 28 0.06% 38.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 10 0.02% 38.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 148 0.30% 38.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 9 0.02% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 16 0.03% 38.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 10 0.02% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 383 0.79% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 7 0.01% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 5 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 66 0.14% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 1 0.00% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 3 0.01% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 4 0.01% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 69 0.14% 39.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.58% # Bytes accessed per row activation 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4 0.01% 42.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 4 0.01% 42.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 136 0.28% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 1 0.00% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 2 0.00% 42.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 260 0.53% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 3 0.01% 43.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 4 0.01% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 67 0.14% 43.37% # Bytes accessed per row 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0.00% 44.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 3 0.01% 44.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 1 0.00% 44.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 295 0.61% 45.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 2 0.00% 45.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 10 0.02% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 1 0.00% 45.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 539 1.11% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 1 0.00% 46.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 294 0.60% 47.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9607 1 0.00% 47.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 65 0.13% 47.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.34% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::25344-25351 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 292 0.60% 65.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 65 0.13% 65.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 64 0.13% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 257 0.53% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 128 0.26% 67.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 67.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 31 0.06% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 182 0.37% 67.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 324 0.66% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 69 0.14% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 64 0.13% 68.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 126 0.26% 69.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 341 0.70% 69.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 69 0.14% 69.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30656-30663 1 0.00% 70.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 368 0.75% 70.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 128 0.26% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31111 1 0.00% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 88 0.18% 71.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 82 0.17% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 266 0.55% 72.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 69 0.14% 72.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 69 0.14% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 1 0.00% 73.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 265 0.54% 74.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33984-33991 1 0.00% 74.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 82 0.17% 74.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34240-34247 1 0.00% 74.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 88 0.18% 74.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34432-34439 1 0.00% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 367 0.75% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34880-34887 1 0.00% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35456-35463 1 0.00% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 69 0.14% 76.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 341 0.70% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 126 0.26% 77.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 69 0.14% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 323 0.66% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 182 0.37% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 31 0.06% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 129 0.26% 78.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 64 0.13% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 129 0.26% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 537 1.10% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 82.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 129 0.26% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 293 0.60% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 66 0.14% 83.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 64 0.13% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 1 0.00% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 255 0.52% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 127 0.26% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 30 0.06% 85.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 181 0.37% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 323 0.66% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 69 0.14% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 338 0.69% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 70 0.14% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 65 0.13% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 369 0.76% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 127 0.26% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47552-47559 1 0.00% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 90 0.18% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 82 0.17% 89.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 266 0.55% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 69 0.14% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4685 9.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48746 # Bytes accessed per row activation +system.physmem.totQLat 326451020750 # Total ticks spent queuing +system.physmem.totMemAccLat 407972275750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67393460000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14127795000 # Total ticks spent accessing banks +system.physmem.avgQLat 24219.78 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1048.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30267.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13434104 # Number of row buffer hits during reads -system.physmem.writeRowHits 39465 # Number of row buffer hits during writes +system.physmem.avgWrQLen 0.38 # Average write queue length when enqueuing +system.physmem.readRowHits 13435238 # Number of row buffer hits during reads +system.physmem.writeRowHits 39389 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes -system.physmem.avgGap 172554.83 # Average gap between requests +system.physmem.writeRowHitRate 88.15 # Row buffer hit rate for writes +system.physmem.avgGap 172541.07 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 0.88 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -532,336 +533,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55672581 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13813538 # Transaction distribution -system.membus.trans_dist::ReadResp 13813538 # Transaction distribution -system.membus.trans_dist::WriteReq 432230 # Transaction distribution -system.membus.trans_dist::WriteResp 432230 # Transaction distribution -system.membus.trans_dist::Writeback 17092 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2370 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2370 # Transaction distribution -system.membus.trans_dist::ReadExReq 28046 # Transaction distribution -system.membus.trans_dist::ReadExResp 28046 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 733938 # Packet count per connected master and slave (bytes) +system.membus.throughput 55671057 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13813895 # Transaction distribution +system.membus.trans_dist::ReadResp 13813895 # Transaction distribution +system.membus.trans_dist::WriteReq 432143 # Transaction distribution +system.membus.trans_dist::WriteResp 432143 # Transaction distribution +system.membus.trans_dist::Writeback 17007 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2353 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2353 # Transaction distribution +system.membus.trans_dist::ReadExReq 27827 # Transaction distribution +system.membus.trans_dist::ReadExResp 27827 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731520 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1686036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26883424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26883424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28569460 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 737821 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1682851 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26886592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569443 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735400 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5091480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5829741 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107533696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107533696 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113363437 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817886 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070524 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5806364 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107546368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107546368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113352732 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133814850 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 418359500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416796500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 204500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 205000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607428500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14608293500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1598779620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1594356888 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30359701500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63253 # number of replacements -system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use -system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128649 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.598574 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375574111000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36861.205107 # Average occupied blocks per requestor +system.l2c.tags.replacements 63223 # number of replacements +system.l2c.tags.tagsinuse 50383.450720 # Cycle average of tags in use +system.l2c.tags.total_refs 1749716 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128619 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.603869 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375590593500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36838.052028 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5227.235315 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3840.097341 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5233.374732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3836.748090 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 502.876093 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 689.542033 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.851035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974650 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1682.063126 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1580.426346 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562457 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 504.839969 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 688.402361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.761256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1676.159647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1594.119177 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562104 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079761 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058595 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058544 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010522 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025666 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024115 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768925 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.007703 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010504 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768790 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2645 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6480 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55890 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997833 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683343 # Number of tag accesses -system.l2c.tags.data_accesses 17683343 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8706 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467858 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 176725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2609 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 130025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18749 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 132168 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291173 # number of ReadReq hits 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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.334448 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62561.980200 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62753.451571 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62689.252619 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62897.824206 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62782.538660 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62821.627151 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1026,52 +1001,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58816500 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021450 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021449 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432230 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432230 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1512 # Transaction distribution +system.toL2Bus.throughput 58820773 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019834 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019833 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432143 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432143 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265318 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1491 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80593 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80593 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423002 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52276 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3322226 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26580608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37417965 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64105945 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141275262 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 99532 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2179112263 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1493 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80420 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80420 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831638 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419538 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3318402 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26591040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37381340 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84972 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64078776 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141286926 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 98800 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2177097249 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872836168 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1873558443 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1848885181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1846163669 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10174967 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9980966 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31036489 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30796222 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762826 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13805907 # Transaction distribution -system.iobus.trans_dist::ReadResp 13805907 # Transaction distribution +system.iobus.throughput 48762593 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13806282 # Transaction distribution +system.iobus.trans_dist::ReadResp 13806282 # Transaction distribution system.iobus.trans_dist::WriteReq 2774 # Transaction distribution system.iobus.trans_dist::WriteResp 2774 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 718942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716528 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1087,18 +1062,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 733938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26883424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26883424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27617362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26886592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27618112 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715269 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712856 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1114,14 +1089,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 737821 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107533696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107533696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108271517 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209194 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 735400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107546368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107546368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108281768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209182 # Total data (bytes) system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1133,7 +1108,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 359973000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358766000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1165,459 +1140,501 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13441712000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443296000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 731164000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 728746000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36852557250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36856311500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7990938 # DTB read hits -system.cpu0.dtb.read_misses 6181 # DTB read misses -system.cpu0.dtb.write_hits 6591681 # DTB write hits -system.cpu0.dtb.write_misses 1989 # DTB write misses -system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7990923 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6594140 # DTB write hits +system.cpu0.dtb.write_misses 1982 # DTB write misses +system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5665 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5674 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 119 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 122 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997119 # DTB read accesses -system.cpu0.dtb.write_accesses 6593670 # DTB write accesses +system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7997134 # DTB read accesses +system.cpu0.dtb.write_accesses 6596122 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14582619 # DTB hits -system.cpu0.dtb.misses 8170 # DTB misses -system.cpu0.dtb.accesses 14590789 # DTB accesses -system.cpu0.itb.inst_hits 32323173 # ITB inst hits -system.cpu0.itb.inst_misses 3455 # ITB inst misses +system.cpu0.dtb.hits 14585063 # DTB hits +system.cpu0.dtb.misses 8193 # DTB misses +system.cpu0.dtb.accesses 14593256 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 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(read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8062582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3742769 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43639057 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31833706 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8062582 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3742769 # number of overall hits +system.cpu0.icache.overall_hits::total 43639057 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 476257 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129542 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 310613 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916412 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 476257 # number of demand (read+write) misses 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demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5323987573 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1733546761 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3590440812 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5323987573 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27356277500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28781091750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56137369250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442174490 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339751582 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14781926072 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28798451990 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42120843332 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70919295322 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026749 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014103 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021316 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019469 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049859 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020218 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1738865763 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3571118820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5309984583 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1738865763 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3571118820 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5309984583 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27398396000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28553530500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55951926500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442155991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13334829583 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14776985574 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840551991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41888360083 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70728912074 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033845 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026708 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014093 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021334 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019411 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008015 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050327 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043165 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020321 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011525 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011525 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.686678 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12959.606210 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.544437 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33315.433109 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35310.030029 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34614.428054 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.665513 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11526.466466 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11387.033208 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011511 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011511 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12252.233405 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12964.262413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12731.654924 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33550.229725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35063.744813 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34535.653208 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11126.782658 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11539.351457 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11397.038764 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1628,390 +1645,474 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096419 # DTB read hits -system.cpu1.dtb.read_misses 2083 # DTB read misses -system.cpu1.dtb.write_hits 1418166 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses -system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 2095173 # DTB read hits +system.cpu1.dtb.read_misses 2089 # DTB read misses +system.cpu1.dtb.write_hits 1414657 # DTB write hits +system.cpu1.dtb.write_misses 374 # DTB write misses +system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1771 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098502 # DTB read accesses -system.cpu1.dtb.write_accesses 1418539 # DTB write accesses +system.cpu1.dtb.read_accesses 2097262 # DTB read accesses +system.cpu1.dtb.write_accesses 1415031 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3514585 # DTB hits -system.cpu1.dtb.misses 2456 # DTB misses -system.cpu1.dtb.accesses 3517041 # DTB accesses -system.cpu1.itb.inst_hits 8182058 # ITB inst hits -system.cpu1.itb.inst_misses 1201 # ITB inst misses +system.cpu1.dtb.hits 3509830 # DTB hits +system.cpu1.dtb.misses 2463 # DTB misses +system.cpu1.dtb.accesses 3512293 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 8192124 # ITB inst hits +system.cpu1.itb.inst_misses 1194 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 889 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8183259 # ITB inst accesses -system.cpu1.itb.hits 8182058 # DTB hits -system.cpu1.itb.misses 1201 # DTB misses -system.cpu1.itb.accesses 8183259 # DTB accesses -system.cpu1.numCycles 581387993 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8193318 # ITB inst accesses +system.cpu1.itb.hits 8192124 # DTB hits +system.cpu1.itb.misses 1194 # DTB misses +system.cpu1.itb.accesses 8193318 # DTB accesses +system.cpu1.numCycles 581420474 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7973391 # Number of instructions committed -system.cpu1.committedOps 10123180 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9055145 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304839 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1113920 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9055145 # number of integer instructions -system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 52196104 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9841677 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read +system.cpu1.committedInsts 7979382 # Number of instructions committed +system.cpu1.committedOps 10120569 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9091581 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1987 # Number of float alu accesses +system.cpu1.num_func_calls 304296 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1113753 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9091581 # number of integer instructions +system.cpu1.num_fp_insts 1987 # number of float instructions +system.cpu1.num_int_register_reads 53006739 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9888017 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1409 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3682729 # number of memory refs -system.cpu1.num_load_insts 2189938 # Number of load instructions -system.cpu1.num_store_insts 1492791 # Number of store instructions -system.cpu1.num_idle_cycles 546287151.729317 # Number of idle cycles -system.cpu1.num_busy_cycles 35100841.270683 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060374 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939626 # Percentage of idle cycles +system.cpu1.num_mem_refs 3676771 # number of memory refs +system.cpu1.num_load_insts 2188618 # Number of load instructions +system.cpu1.num_store_insts 1488153 # Number of store instructions +system.cpu1.num_idle_cycles 545340562.414449 # Number of idle cycles +system.cpu1.num_busy_cycles 36079911.585551 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062055 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937945 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4728615 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3846891 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223365 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3153803 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2531568 # Number of BTB hits +system.cpu2.branchPred.lookups 4789734 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3907352 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223904 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3178605 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2529099 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.270328 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413323 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21760 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.566319 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413607 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21727 # Number of incorrect RAS predictions. +system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10972958 # DTB read hits -system.cpu2.dtb.read_misses 22884 # DTB read misses -system.cpu2.dtb.write_hits 3353841 # DTB write hits -system.cpu2.dtb.write_misses 6440 # DTB write misses -system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 10928591 # DTB read hits +system.cpu2.dtb.read_misses 22863 # DTB read misses +system.cpu2.dtb.write_hits 3355192 # DTB write hits +system.cpu2.dtb.write_misses 6501 # DTB write misses +system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2329 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 684 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2326 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 747 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10995842 # DTB read accesses -system.cpu2.dtb.write_accesses 3360281 # DTB write accesses +system.cpu2.dtb.perms_faults 464 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10951454 # DTB read accesses +system.cpu2.dtb.write_accesses 3361693 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14326799 # DTB hits -system.cpu2.dtb.misses 29324 # DTB misses -system.cpu2.dtb.accesses 14356123 # DTB accesses -system.cpu2.itb.inst_hits 4052293 # ITB inst hits -system.cpu2.itb.inst_misses 4591 # ITB inst misses +system.cpu2.dtb.hits 14283783 # DTB hits +system.cpu2.dtb.misses 29364 # DTB misses +system.cpu2.dtb.accesses 14313147 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.itb.inst_hits 4054873 # ITB inst hits +system.cpu2.itb.inst_misses 4512 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1671 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1691 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1038 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4056884 # ITB inst accesses -system.cpu2.itb.hits 4052293 # DTB hits -system.cpu2.itb.misses 4591 # DTB misses -system.cpu2.itb.accesses 4056884 # DTB accesses -system.cpu2.numCycles 88364936 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059385 # ITB inst accesses +system.cpu2.itb.hits 4054873 # DTB hits +system.cpu2.itb.misses 4512 # DTB misses +system.cpu2.itb.accesses 4059385 # DTB accesses +system.cpu2.numCycles 88337048 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9352566 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32517206 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4728615 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2944891 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6861610 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1759869 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50868 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18844594 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 866 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32744 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721068 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 448 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4050852 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289827 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1989 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37074469 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.054164 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.440934 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9388767 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32522302 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4789734 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2942706 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6862489 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1760464 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 49990 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19168441 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 508 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 916 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33389 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 724944 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 411 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4053387 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 290500 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37439208 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.044253 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431681 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30218075 81.51% 81.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 386681 1.04% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516163 1.39% 83.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819367 2.21% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 628808 1.70% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344228 0.93% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1045241 2.82% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229591 0.62% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2886315 7.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30581596 81.68% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385766 1.03% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516570 1.38% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819401 2.19% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 630355 1.68% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341667 0.91% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045652 2.79% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 230362 0.62% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2887839 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37074469 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053512 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367988 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9932859 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19459354 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6244628 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 279238 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1157490 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609849 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53110 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36985250 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 179754 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1157490 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10483306 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6921288 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11074515 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5953553 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1483425 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34895792 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 326661 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 892066 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 111 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37386016 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159700078 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148525933 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3408 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26513636 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10872379 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232480 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208815 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3253838 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6628841 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3905916 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536820 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 771052 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32212739 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505163 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34823222 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55040 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7182108 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19097970 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148083 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37074469 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.939278 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.598547 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37439208 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054221 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368162 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10012366 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19744012 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6199418 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 325352 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1157163 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 610165 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53442 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36995280 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180745 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1157163 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10561732 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6812365 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11427981 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5960297 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1518769 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34903210 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 326244 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 883069 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37436972 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 161085942 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148506742 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3418 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26572380 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10864591 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285670 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261929 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3326002 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6631520 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3908381 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 522508 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 782143 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32221978 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 504989 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34786596 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55958 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7182504 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19112764 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148353 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37439208 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929149 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.590514 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24463826 65.99% 65.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3833492 10.34% 76.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2324654 6.27% 82.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2008652 5.42% 88.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2796278 7.54% 95.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 971248 2.62% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496274 1.34% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144890 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35155 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24741126 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3984374 10.64% 76.73% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2311240 6.17% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1973818 5.27% 88.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2779235 7.42% 95.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 969976 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 499460 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 145124 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34855 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37074469 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37439208 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19545 1.28% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1401661 91.55% 92.82% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109897 7.18% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19410 1.27% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1392857 91.45% 92.72% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110885 7.28% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61115 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19755783 56.73% 56.91% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28013 0.08% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11456328 32.90% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3521577 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8329 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19813633 56.96% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28024 0.08% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11412307 32.81% 89.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3523902 10.13% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34823222 # Type of FU issued -system.cpu2.iq.rate 0.394084 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1531104 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043968 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108328678 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39905127 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28084625 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7572 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4019 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3368 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36289170 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4041 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206363 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34786596 # Type of FU issued +system.cpu2.iq.rate 0.393794 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1523153 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043786 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108613127 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39914727 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28091280 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7607 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3993 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3398 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36297355 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4065 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206023 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533130 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9465 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562980 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1534437 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2089 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9566 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 563640 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5327720 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344503 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5283023 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 345372 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1157490 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5247900 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88519 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32800222 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60619 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6628841 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3905916 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362644 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29757 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2395 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9465 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107959 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89408 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197367 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33908136 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11185478 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 915086 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1157163 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5185391 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88081 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32809694 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61016 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6631520 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3908381 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362677 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29698 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2464 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9566 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107529 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89869 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197398 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33871170 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11141481 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 915426 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82320 # number of nop insts executed -system.cpu2.iew.exec_refs 14673656 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3709694 # Number of branches executed -system.cpu2.iew.exec_stores 3488178 # Number of stores executed -system.cpu2.iew.exec_rate 0.383728 # Inst execution rate -system.cpu2.iew.wb_sent 33508440 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28087993 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16121354 # num instructions producing a value -system.cpu2.iew.wb_consumers 29172590 # num instructions consuming a value +system.cpu2.iew.exec_nop 82727 # number of nop insts executed +system.cpu2.iew.exec_refs 14631897 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3767155 # Number of branches executed +system.cpu2.iew.exec_stores 3490416 # Number of stores executed +system.cpu2.iew.exec_rate 0.383431 # Inst execution rate +system.cpu2.iew.wb_sent 33470061 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28094678 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16123172 # num instructions producing a value +system.cpu2.iew.wb_consumers 29138246 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317864 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552620 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.318040 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553334 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7137877 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357080 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171034 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35916785 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.707415 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.751354 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7139947 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356636 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171258 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36281839 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700541 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.737980 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27161260 75.62% 75.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4227698 11.77% 87.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1252285 3.49% 90.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 635084 1.77% 92.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 561790 1.56% 94.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319405 0.89% 95.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418201 1.16% 96.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311340 0.87% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1029722 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27358624 75.41% 75.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4439139 12.24% 87.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1255970 3.46% 91.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 641270 1.77% 92.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 512644 1.41% 94.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317320 0.87% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 419851 1.16% 96.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 310411 0.86% 97.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1026610 2.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35916785 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20564616 # Number of instructions committed -system.cpu2.commit.committedOps 25408067 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36281839 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20568992 # Number of instructions committed +system.cpu2.commit.committedOps 25416928 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8438647 # Number of memory references committed -system.cpu2.commit.loads 5095711 # Number of loads committed -system.cpu2.commit.membars 94423 # Number of memory barriers committed -system.cpu2.commit.branches 3185422 # Number of branches committed -system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22610745 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295586 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1029722 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8441824 # Number of memory references committed +system.cpu2.commit.loads 5097083 # Number of loads committed +system.cpu2.commit.membars 94345 # Number of memory barriers committed +system.cpu2.commit.branches 3244670 # Number of branches committed +system.cpu2.commit.fp_insts 3331 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22669662 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295973 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1026610 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66910934 # The number of ROB reads -system.cpu2.rob.rob_writes 66293514 # The number of ROB writes -system.cpu2.timesIdled 359960 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51290467 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553935024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20509130 # Number of Instructions Simulated -system.cpu2.committedOps 25352581 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20509130 # Number of Instructions Simulated -system.cpu2.cpi 4.308566 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.308566 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232096 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232096 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157121826 # number of integer regfile reads -system.cpu2.int_regfile_writes 29906145 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22616 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9261107 # number of misc regfile reads -system.cpu2.misc_regfile_writes 242774 # number of misc regfile writes +system.cpu2.rob.rob_reads 67290844 # The number of ROB reads +system.cpu2.rob.rob_writes 66314967 # The number of ROB writes +system.cpu2.timesIdled 359753 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50897840 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553970695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20513640 # Number of Instructions Simulated +system.cpu2.committedOps 25361576 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20513640 # Number of Instructions Simulated +system.cpu2.cpi 4.306259 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.306259 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232220 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232220 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157179181 # number of integer regfile reads +system.cpu2.int_regfile_writes 29907517 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46919 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes +system.cpu2.misc_regfile_reads 66774204 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297147 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2028,10 +2129,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1347589582250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1347589582250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347815916500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347815916500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 3aa171235..789fa7ff8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,7 +96,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -112,6 +122,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fetchBufferSize=64 @@ -130,6 +141,7 @@ interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -224,10 +236,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -235,6 +272,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -589,24 +627,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -614,6 +688,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -624,7 +699,7 @@ eventq_index=0 [system.cpu1] type=DerivO3CPU -children=branchPred dtb fuPool isa itb tracer +children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -650,6 +725,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fetchBufferSize=64 @@ -668,6 +744,7 @@ interrupts=Null isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -725,10 +802,34 @@ localPredictorSize=2048 numThreads=1 predType=tournament +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -736,6 +837,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -1050,24 +1152,59 @@ opLat=3 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -1075,6 +1212,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -1713,7 +1851,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 1059ef88b..5150881aa 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -11,7 +11,23 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 74e20af0b..f047a9e04 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:28:14 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:10:32 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x6aaf400 0x6aaf400 + 0: system.cpu1.isa: ISA system set to: 0x6aaf400 0x6aaf400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 5e74bf3fb..7a8eccd80 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.549345 # Number of seconds simulated -sim_ticks 2549345168000 # Number of ticks simulated -final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550461 # Number of seconds simulated +sim_ticks 2550460850000 # Number of ticks simulated +final_tick 2550460850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76720 # Simulator instruction rate (inst/s) -host_op_rate 98719 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3242754050 # Simulator tick rate (ticks/s) -host_mem_usage 404480 # Number of bytes of host memory used -host_seconds 786.17 # Real time elapsed on the host -sim_insts 60314699 # Number of instructions simulated -sim_ops 77609228 # Number of ops (including micro ops) simulated +host_inst_rate 71467 # Simulator instruction rate (inst/s) +host_op_rate 91959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3022122690 # Simulator tick rate (ticks/s) +host_mem_usage 427404 # Number of bytes of host memory used +host_seconds 843.93 # Real time elapsed on the host +sim_insts 60313440 # Number of instructions simulated +sim_ops 77607116 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 498624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4680272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 301248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4410392 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 498624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 301248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784640 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521380 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494720 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800740 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 504512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5067800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 293824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4027288 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 504512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 293824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786560 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802660 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7791 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68918 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59135 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380345 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813160 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47506524 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62932 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59165 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380361 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373664 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813190 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47485743 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 195589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1835872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 118167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1730010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51387342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 195589 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 118167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484554 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596773 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586315 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47506524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1987013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1579043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51365970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115204 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47485743 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 195589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2432645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 118167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2316325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54054984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293442 # Number of read requests accepted -system.physmem.writeReqs 813160 # Number of write requests accepted -system.physmem.readBursts 15293442 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813160 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978220224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 560064 # Total number of bytes read from write queue -system.physmem.bytesWritten 6909248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131004072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800740 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8751 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 705188 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4685 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955866 # Per bank write bursts -system.physmem.perBankRdBursts::1 955512 # Per bank write bursts -system.physmem.perBankRdBursts::2 954595 # Per bank write bursts -system.physmem.perBankRdBursts::3 954812 # Per bank write bursts -system.physmem.perBankRdBursts::4 955762 # Per bank write bursts -system.physmem.perBankRdBursts::5 955910 # Per bank write bursts -system.physmem.perBankRdBursts::6 954892 # Per bank write bursts -system.physmem.perBankRdBursts::7 954654 # Per bank write bursts -system.physmem.perBankRdBursts::8 956247 # Per bank write bursts -system.physmem.perBankRdBursts::9 955899 # Per bank write bursts -system.physmem.perBankRdBursts::10 954311 # Per bank write bursts -system.physmem.perBankRdBursts::11 954068 # Per bank write bursts -system.physmem.perBankRdBursts::12 956211 # Per bank write bursts -system.physmem.perBankRdBursts::13 955980 # Per bank write bursts -system.physmem.perBankRdBursts::14 955097 # Per bank write bursts -system.physmem.perBankRdBursts::15 954875 # Per bank write bursts -system.physmem.perBankWrBursts::0 6687 # Per bank write bursts -system.physmem.perBankWrBursts::1 6461 # Per bank write bursts -system.physmem.perBankWrBursts::2 6610 # Per bank write bursts -system.physmem.perBankWrBursts::3 6631 # Per bank write bursts -system.physmem.perBankWrBursts::4 6571 # Per bank write bursts -system.physmem.perBankWrBursts::5 6830 # Per bank write bursts -system.physmem.perBankWrBursts::6 6820 # Per bank write bursts -system.physmem.perBankWrBursts::7 6764 # Per bank write bursts -system.physmem.perBankWrBursts::8 7113 # Per bank write bursts -system.physmem.perBankWrBursts::9 6879 # Per bank write bursts -system.physmem.perBankWrBursts::10 6545 # Per bank write bursts -system.physmem.perBankWrBursts::11 6197 # Per bank write bursts -system.physmem.perBankWrBursts::12 7141 # Per bank write bursts -system.physmem.perBankWrBursts::13 6760 # Per bank write bursts -system.physmem.perBankWrBursts::14 7037 # Per bank write bursts -system.physmem.perBankWrBursts::15 6911 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 197812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2583550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2165077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54033198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293488 # Number of read requests accepted +system.physmem.writeReqs 813190 # Number of write requests accepted +system.physmem.readBursts 15293488 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813190 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978237376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 545856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6910336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131006896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6802660 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8529 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 705216 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4690 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955874 # Per bank write bursts +system.physmem.perBankRdBursts::1 955460 # Per bank write bursts +system.physmem.perBankRdBursts::2 954683 # Per bank write bursts +system.physmem.perBankRdBursts::3 954757 # Per bank write bursts +system.physmem.perBankRdBursts::4 955767 # Per bank write bursts +system.physmem.perBankRdBursts::5 955952 # Per bank write bursts +system.physmem.perBankRdBursts::6 954810 # Per bank write bursts +system.physmem.perBankRdBursts::7 954709 # Per bank write bursts +system.physmem.perBankRdBursts::8 956270 # Per bank write bursts +system.physmem.perBankRdBursts::9 955934 # Per bank write bursts +system.physmem.perBankRdBursts::10 954560 # Per bank write bursts +system.physmem.perBankRdBursts::11 953973 # Per bank write bursts +system.physmem.perBankRdBursts::12 956221 # Per bank write bursts +system.physmem.perBankRdBursts::13 955978 # Per bank write bursts +system.physmem.perBankRdBursts::14 955151 # Per bank write bursts +system.physmem.perBankRdBursts::15 954860 # Per bank write bursts +system.physmem.perBankWrBursts::0 6693 # Per bank write bursts +system.physmem.perBankWrBursts::1 6460 # Per bank write bursts +system.physmem.perBankWrBursts::2 6602 # Per bank write bursts +system.physmem.perBankWrBursts::3 6635 # Per bank write bursts +system.physmem.perBankWrBursts::4 6566 # Per bank write bursts +system.physmem.perBankWrBursts::5 6824 # Per bank write bursts +system.physmem.perBankWrBursts::6 6825 # Per bank write bursts +system.physmem.perBankWrBursts::7 6757 # Per bank write bursts +system.physmem.perBankWrBursts::8 7131 # Per bank write bursts +system.physmem.perBankWrBursts::9 6880 # Per bank write bursts +system.physmem.perBankWrBursts::10 6546 # Per bank write bursts +system.physmem.perBankWrBursts::11 6195 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 6763 # Per bank write bursts +system.physmem.perBankWrBursts::14 7046 # Per bank write bursts +system.physmem.perBankWrBursts::15 6906 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2549344036000 # Total gap between requests +system.physmem.totGap 2550459728500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 42 # Read request sizes (log2) +system.physmem.readPktSize::2 44 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154584 # Read request sizes (log2) +system.physmem.readPktSize::6 154628 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754025 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59135 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1194358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1134175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1088302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3688965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2641659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2636525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2648641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59165 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1189211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1129031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1083368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3689725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2647408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2642045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2653706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 51340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,31 +165,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -193,381 +197,396 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11370.889515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1019.409545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16839.040635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23447 27.06% 27.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14187 16.38% 43.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2756 3.18% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2051 2.37% 48.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1336 1.54% 50.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1207 1.39% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 834 0.96% 52.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1069 1.23% 54.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 542 0.63% 54.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 595 0.69% 55.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 544 0.63% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 497 0.57% 56.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 259 0.30% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 256 0.30% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 151 0.17% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 457 0.53% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 109 0.13% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 146 0.17% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 72 0.08% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 245 0.28% 58.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 63 0.07% 58.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 509 0.59% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 238 0.27% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 21 0.02% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 111 0.13% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 24 0.03% 59.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 197 0.23% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 24 0.03% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 41 0.05% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 375 0.43% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 14 0.02% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 36 0.04% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 11 0.01% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 279 0.32% 60.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 8 0.01% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 26 0.03% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 6 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 24 0.03% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 21 0.02% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 7 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 158 0.18% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 8 0.01% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 20 0.02% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 12 0.01% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 221 0.26% 61.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 10 0.01% 61.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 7 0.01% 61.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 86 0.10% 61.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 7 0.01% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 12 0.01% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 13 0.02% 61.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 93 0.11% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 145 0.17% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 10 0.01% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 20 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 16 0.02% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 418 0.48% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 6 0.01% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 13 0.02% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 5 0.01% 62.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 16 0.02% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 22 0.03% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 16 0.02% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 10 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 214 0.25% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 6 0.01% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 10 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 2 0.00% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 11 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 11 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 9 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 326 0.38% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 11 0.01% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 81 0.09% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 14 0.02% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 6 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 112 0.13% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 3 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 16 0.02% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 7 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 3 0.00% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.01% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 12 0.01% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 585 0.68% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 5 0.01% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 9 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 3 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 63 0.07% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 2 0.00% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 10 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 4 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 9 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 6 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 18 0.02% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 188 0.22% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 4 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 12 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 264 0.30% 65.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 8 0.01% 65.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 14 0.02% 65.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 15 0.02% 65.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 4 0.00% 65.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 8 0.01% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 3 0.00% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 139 0.16% 65.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 8 0.01% 65.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 78 0.09% 65.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 7 0.01% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 491 0.57% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 73 0.08% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 137 0.16% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 1 0.00% 66.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 257 0.30% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 183 0.21% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 1 0.00% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 57 0.07% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 569 0.66% 67.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 64 0.07% 67.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 98 0.11% 67.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 68 0.08% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 311 0.36% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 192 0.22% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 384 0.44% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12359 1 0.00% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 130 0.15% 69.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 71 0.08% 69.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 69.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 66 0.08% 69.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 202 0.23% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 137 0.16% 69.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 4 0.00% 69.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 238 0.27% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 69.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 326 0.38% 70.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14535 1 0.00% 70.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 131 0.15% 70.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 64 0.07% 70.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 86806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11348.833952 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1015.155739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16835.722240 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23589 27.17% 27.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14167 16.32% 43.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2667 3.07% 46.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2091 2.41% 48.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1355 1.56% 50.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1138 1.31% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 864 1.00% 52.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1120 1.29% 54.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 549 0.63% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 610 0.70% 55.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 512 0.59% 56.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 456 0.53% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 243 0.28% 56.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 296 0.34% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 156 0.18% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 592 0.68% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 118 0.14% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 142 0.16% 58.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 67 0.08% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 249 0.29% 58.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 52 0.06% 58.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 529 0.61% 59.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 292 0.34% 59.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 23 0.03% 59.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 99 0.11% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 19 0.02% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 187 0.22% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 47 0.05% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 18 0.02% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 308 0.35% 60.60% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::35008-35015 1 0.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 126 0.15% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 8 0.01% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35520-35527 1 0.00% 84.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 185 0.21% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 384 0.44% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 55 0.06% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 67 0.08% 85.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 130 0.15% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 321 0.37% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 5 0.01% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 165 0.19% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 258 0.30% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 194 0.22% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 60 0.07% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 64 0.07% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38784-38791 1 0.00% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 449 0.52% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 5 0.01% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 3 0.00% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 128 0.15% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39744-39751 1 0.00% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 257 0.30% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 4 0.00% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 186 0.21% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 65 0.07% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 498 0.57% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 65 0.07% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 183 0.21% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41600-41607 1 0.00% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41671 1 0.00% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 4 0.00% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 258 0.30% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 128 0.15% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 2 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 4 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 450 0.52% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 65 0.07% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43456-43463 1 0.00% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 59 0.07% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 195 0.22% 90.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 257 0.30% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 2 0.00% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 1 0.00% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 2 0.00% 90.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 168 0.19% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 1 0.00% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 6 0.01% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 2 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-44999 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 327 0.38% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 131 0.15% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 67 0.08% 91.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 55 0.06% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 386 0.44% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 185 0.21% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 6 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 126 0.15% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 260 0.30% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 129 0.15% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 130 0.15% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 122 0.14% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 386 0.44% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 1 0.00% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 129 0.15% 93.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 65 0.07% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 2 0.00% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5210 6.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49671 2 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::50688-50695 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51072-51079 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51207 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86636 # Bytes accessed per row activation -system.physmem.totQLat 369559391250 # Total ticks spent queuing -system.physmem.totMemAccLat 463610140000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76423455000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17627293750 # Total ticks spent accessing banks -system.physmem.avgQLat 24178.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1153.26 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::50816-50823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51136-51143 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51207 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86806 # Bytes accessed per row activation +system.physmem.totQLat 369546937250 # Total ticks spent queuing +system.physmem.totMemAccLat 463545387250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76424795000 # Total ticks spent in databus transfers +system.physmem.totBankLat 17573655000 # Total ticks spent accessing banks +system.physmem.avgQLat 24177.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1149.74 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30331.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30326.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.02 # Data bus utilization in percentage @@ -575,13 +594,13 @@ system.physmem.busUtilRead 3.00 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.05 # Average write queue length when enqueuing -system.physmem.readRowHits 15212838 # Number of row buffer hits during reads -system.physmem.writeRowHits 93174 # Number of row buffer hits during writes +system.physmem.readRowHits 15213019 # Number of row buffer hits during reads +system.physmem.writeRowHits 93108 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.29 # Row buffer hit rate for writes -system.physmem.avgGap 158279.45 # Average gap between requests +system.physmem.writeRowHitRate 86.23 # Row buffer hit rate for writes +system.physmem.avgGap 158347.97 # Average gap between requests system.physmem.pageHitRate 99.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.88 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.65 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -594,285 +613,305 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54995612 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346068 # Transaction distribution -system.membus.trans_dist::ReadResp 16346071 # Transaction distribution +system.membus.throughput 54973413 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346095 # Transaction distribution +system.membus.trans_dist::ReadResp 16346098 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59135 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4685 # Transaction distribution -system.membus.trans_dist::ReadExReq 131422 # Transaction distribution -system.membus.trans_dist::ReadExResp 131422 # Transaction distribution +system.membus.trans_dist::Writeback 59165 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4689 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4690 # Transaction distribution +system.membus.trans_dist::ReadExReq 131440 # Transaction distribution +system.membus.trans_dist::ReadExResp 131440 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885807 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272561 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272691 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550193 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390337 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550323 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16694284 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19092269 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16699028 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19097009 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140202797 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140202797 # Total data (bytes) +system.membus.tot_pkt_size::total 140207537 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140207537 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487346000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487746500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3636500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17566569000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17566438500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4736419263 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4736460824 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34185683234 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64357 # number of replacements -system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use -system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129744 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.686020 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2512210729500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36987.198092 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.713113 # Average occupied blocks per requestor +system.l2c.tags.replacements 64398 # number of replacements +system.l2c.tags.tagsinuse 51440.737713 # Cycle average of tags in use +system.l2c.tags.total_refs 1904463 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129791 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.673306 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513095359500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36974.659237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.382027 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4872.243485 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3313.752357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.584037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3345.363294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2901.396724 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4864.361052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3325.264959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.733963 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.979227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3333.561172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2910.795705 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564189 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074345 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050564 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.051046 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785114 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65363 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3051 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6862 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55068 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997360 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18937227 # Number of tag accesses -system.l2c.tags.data_accesses 18937227 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32950 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 506567 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 181823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 205967 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436338 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608494 # number of Writeback hits -system.l2c.Writeback_hits::total 608494 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.074224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050740 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784923 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65370 # Occupied blocks per task id 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+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.715168 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62155.866596 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61603.993250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61909.751342 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63741.379310 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70741.379310 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60207.985930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61934.760585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83968.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61706.554068 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63840.729873 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62697.577805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59796.587250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62176.018321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86464.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61240.361577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61866.153720 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61907.619247 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1055,49 +1114,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58478558 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677542 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677544 # Transaction distribution +system.toL2Bus.throughput 58420424 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676760 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676762 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608494 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2952 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607936 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2958 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246169 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246169 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246118 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246118 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798582 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38031 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149645 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7954666 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62951744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85614957 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148876637 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148876637 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 205392 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4965399712 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1968062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796874 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149966 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952482 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62939648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85542385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254948 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148791853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148791853 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 207152 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962468234 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434611165 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4433875230 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4486677044 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4484319469 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24152407 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23911393 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86557036 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86679578 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48444152 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322136 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322136 # Transaction distribution +system.iobus.throughput 48422959 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1119,12 +1178,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1146,14 +1205,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390337 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500865 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500865 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500861 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1199,698 +1258,740 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41494630022 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41495326766 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7183590 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5694303 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377290 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4721847 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3824688 # Number of BTB hits +system.cpu0.branchPred.lookups 7528776 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6012881 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377531 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4829761 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3930404 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.999829 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 708757 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39349 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.378851 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 724348 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39225 # Number of incorrect RAS predictions. +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25676392 # DTB read hits -system.cpu0.dtb.read_misses 38073 # DTB read misses -system.cpu0.dtb.write_hits 5871403 # DTB write hits -system.cpu0.dtb.write_misses 9193 # DTB write misses -system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25731693 # DTB read hits +system.cpu0.dtb.read_misses 40178 # DTB read misses +system.cpu0.dtb.write_hits 6168711 # DTB write hits +system.cpu0.dtb.write_misses 10337 # DTB write misses +system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5420 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5677 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1369 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 585 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25714465 # DTB read accesses -system.cpu0.dtb.write_accesses 5880596 # DTB write accesses +system.cpu0.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25771871 # DTB read accesses +system.cpu0.dtb.write_accesses 6179048 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31547795 # DTB hits -system.cpu0.dtb.misses 47266 # DTB misses -system.cpu0.dtb.accesses 31595061 # DTB accesses -system.cpu0.itb.inst_hits 5793609 # ITB inst hits -system.cpu0.itb.inst_misses 6965 # ITB inst misses +system.cpu0.dtb.hits 31900404 # DTB hits +system.cpu0.dtb.misses 50515 # DTB misses +system.cpu0.dtb.accesses 31950919 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 5899860 # ITB inst hits +system.cpu0.itb.inst_misses 7207 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 629 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 776 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2542 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2688 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1475 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1562 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5800574 # ITB inst accesses -system.cpu0.itb.hits 5793609 # DTB hits -system.cpu0.itb.misses 6965 # DTB misses -system.cpu0.itb.accesses 5800574 # DTB accesses -system.cpu0.numCycles 241355643 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5907067 # ITB inst accesses +system.cpu0.itb.hits 5899860 # DTB hits +system.cpu0.itb.misses 7207 # DTB misses +system.cpu0.itb.accesses 5907067 # DTB accesses +system.cpu0.numCycles 242297109 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15408312 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 44581736 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7183590 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4533445 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10042154 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2412494 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81949 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 48815807 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1726 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1993 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 42608 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1411972 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5791670 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 368874 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3149 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77468964 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.722040 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.069743 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15555542 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45617593 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7528776 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4654752 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10311247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2439507 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 83051 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50330649 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1691 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2002 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 48587 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1491133 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 722 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5897866 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 368478 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3041 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79507031 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.722707 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.070799 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67434698 87.05% 87.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 662922 0.86% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 849826 1.10% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1158615 1.50% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1071303 1.38% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 540404 0.70% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1264103 1.63% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 371341 0.48% 94.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4115752 5.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69202528 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 678265 0.85% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 875305 1.10% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1177307 1.48% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1118218 1.41% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557082 0.70% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1282023 1.61% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 381348 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4234955 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77468964 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029764 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.184714 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16332862 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49931887 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9147459 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 483482 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1571127 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 985970 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 93586 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53203424 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 313882 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1571127 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17204608 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20551297 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 26349401 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8685161 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3105311 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 50667470 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7242 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 502803 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2087731 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 194 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 52194379 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 231353972 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 213903823 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5361 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38031727 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14162651 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 415813 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 366209 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6409920 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9794680 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6688167 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1031152 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1299354 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47050561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 979447 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 60972564 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88288 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9787230 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24359943 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256705 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77468964 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.787058 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.508592 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79507031 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031072 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188271 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16656471 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51363244 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9231902 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 659908 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1593273 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1005882 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91811 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54700033 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 305616 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1593273 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17552192 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20324540 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27741870 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8932000 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3360998 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52127379 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 375 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 510306 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2174045 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 221 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53799249 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241745694 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220537236 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5112 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39397526 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14401722 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 594296 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 542687 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6992906 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10039494 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6994522 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1049493 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1384753 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48432856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1029992 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62172633 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89012 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9963233 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24631985 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 276940 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79507031 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.781977 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.500620 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55694568 71.89% 71.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6744950 8.71% 80.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3431902 4.43% 85.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2928703 3.78% 88.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6175861 7.97% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1433177 1.85% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 773017 1.00% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224018 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 62768 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56951176 71.63% 71.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7375765 9.28% 80.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3517120 4.42% 85.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2922983 3.68% 89.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6158188 7.75% 96.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1492282 1.88% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 793715 1.00% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 229189 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66613 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77468964 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79507031 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30016 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221900 94.67% 95.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207684 4.66% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 30271 0.68% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4195541 94.33% 95.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 221720 4.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 165809 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28246973 46.33% 46.60% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46806 0.08% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1267 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26338371 43.20% 89.88% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6173305 10.12% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15963 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29223949 47.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47621 0.08% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1246 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26409062 42.48% 89.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6474770 10.41% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 60972564 # Type of FU issued -system.cpu0.iq.rate 0.252625 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4459601 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073141 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 203996977 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57825737 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 42036875 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12074 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6420 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 65259915 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6441 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 303470 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62172633 # Type of FU issued +system.cpu0.iq.rate 0.256597 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4447534 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071535 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208427694 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59435167 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43384407 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11467 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6219 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5237 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66598153 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6051 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 313701 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2107176 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3913 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15490 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 838182 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2134408 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15882 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 849708 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17232343 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348683 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17067409 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348218 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1571127 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15861030 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 237452 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 48130825 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105592 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9794680 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6688167 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 690516 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54721 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15490 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 181987 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144371 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 326358 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59914186 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26012956 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1058378 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1593273 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15683016 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239861 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49569735 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107283 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10039494 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6994522 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 730989 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 55378 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15882 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184147 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145491 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329638 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61106002 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26080146 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1066631 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 100817 # number of nop insts executed -system.cpu0.iew.exec_refs 32128938 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5674429 # Number of branches executed -system.cpu0.iew.exec_stores 6115982 # Number of stores executed -system.cpu0.iew.exec_rate 0.248240 # Inst execution rate -system.cpu0.iew.wb_sent 59424173 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 42042235 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22754717 # num instructions producing a value -system.cpu0.iew.wb_consumers 41618983 # num instructions consuming a value +system.cpu0.iew.exec_nop 106887 # number of nop insts executed +system.cpu0.iew.exec_refs 32497006 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5987699 # Number of branches executed +system.cpu0.iew.exec_stores 6416860 # Number of stores executed +system.cpu0.iew.exec_rate 0.252195 # Inst execution rate +system.cpu0.iew.wb_sent 60612995 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43389644 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23417175 # num instructions producing a value +system.cpu0.iew.wb_consumers 43060015 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.174192 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546739 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.179076 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543826 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9657152 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 722742 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285161 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75897837 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.500741 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.473402 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9791777 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 753052 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287149 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77913758 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504003 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.469415 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62326931 82.12% 82.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6623929 8.73% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1927651 2.54% 93.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1062809 1.40% 94.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 977806 1.29% 96.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 537572 0.71% 96.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 721191 0.95% 97.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 348340 0.46% 98.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1371608 1.81% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63454715 81.44% 81.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7423327 9.53% 90.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1988141 2.55% 93.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1098394 1.41% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 861624 1.11% 96.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 581195 0.75% 96.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 738806 0.95% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 351756 0.45% 98.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1415800 1.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75897837 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29270698 # Number of instructions committed -system.cpu0.commit.committedOps 38005132 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77913758 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30063645 # Number of instructions committed +system.cpu0.commit.committedOps 39268790 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13537489 # Number of memory references committed -system.cpu0.commit.loads 7687504 # Number of loads committed -system.cpu0.commit.membars 203418 # Number of memory barriers committed -system.cpu0.commit.branches 4891612 # Number of branches committed -system.cpu0.commit.fp_insts 5306 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33685063 # Number of committed integer instructions. -system.cpu0.commit.function_calls 497791 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1371608 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14049900 # Number of memory references committed +system.cpu0.commit.loads 7905086 # Number of loads committed +system.cpu0.commit.membars 209983 # Number of memory barriers committed +system.cpu0.commit.branches 5182251 # Number of branches committed +system.cpu0.commit.fp_insts 5199 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34974968 # Number of committed integer instructions. +system.cpu0.commit.function_calls 508855 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1415800 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 121269057 # The number of ROB reads -system.cpu0.rob.rob_writes 96938789 # The number of ROB writes -system.cpu0.timesIdled 907351 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 163886679 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2251360755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29203197 # Number of Instructions Simulated -system.cpu0.committedOps 37937631 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29203197 # Number of Instructions Simulated -system.cpu0.cpi 8.264699 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.264699 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.120997 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.120997 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 271224247 # number of integer regfile reads -system.cpu0.int_regfile_writes 42758050 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22657 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19930 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15040337 # number of misc regfile reads -system.cpu0.misc_regfile_writes 403311 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984140 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.573239 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10515740 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984652 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.679651 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7012159250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 319.827324 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy 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# average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43390.015123 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36582 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25832 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3477 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 293 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.521139 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 88.163823 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14562.625000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45380.745817 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40970.362469 # average overall miss latency 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of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90803265751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182330669251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13693631022 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13075286221 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26768917243 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106094158515 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103008489165 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209102647680 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025341 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027810 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026594 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024927 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055248 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047467 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105221034522 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103878551972 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209099586494 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025543 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027639 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026576 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025195 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023406 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054282 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040929 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047428 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000033 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000024 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025168 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13992.929912 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13244.737489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13595.823194 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46213.552352 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47507.207423 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46845.248826 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12583.867511 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11609.743295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12145.907145 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025657 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025396 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025934 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025657 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13954.086330 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13285.710326 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13611.653829 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47027.142187 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45575.250598 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46368.672796 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12619.397523 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11614.686445 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12174.353840 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14124.750000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27290.768643 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25997.680782 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26625.968153 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12562.375000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27831.405146 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25022.844020 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26457.252239 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1905,324 +2006,366 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7296861 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5846678 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347662 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4742078 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3857406 # Number of BTB hits +system.cpu1.branchPred.lookups 7298811 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5882879 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344498 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4442454 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3749763 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 81.344212 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 691724 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35172 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.407469 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 676814 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34330 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25545961 # DTB read hits -system.cpu1.dtb.read_misses 37652 # DTB read misses -system.cpu1.dtb.write_hits 5843070 # DTB write hits -system.cpu1.dtb.write_misses 9833 # DTB write misses -system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25485052 # DTB read hits +system.cpu1.dtb.read_misses 36401 # DTB read misses +system.cpu1.dtb.write_hits 5542090 # DTB write hits +system.cpu1.dtb.write_misses 8345 # DTB write misses +system.cpu1.dtb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5607 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2149 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5452 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1278 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25583613 # DTB read accesses -system.cpu1.dtb.write_accesses 5852903 # DTB write accesses +system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25521453 # DTB read accesses +system.cpu1.dtb.write_accesses 5550435 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31389031 # DTB hits -system.cpu1.dtb.misses 47485 # DTB misses -system.cpu1.dtb.accesses 31436516 # DTB accesses -system.cpu1.itb.inst_hits 5792513 # ITB inst hits -system.cpu1.itb.inst_misses 7242 # ITB inst misses +system.cpu1.dtb.hits 31027142 # DTB hits +system.cpu1.dtb.misses 44746 # DTB misses +system.cpu1.dtb.accesses 31071888 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 5673835 # ITB inst hits +system.cpu1.itb.inst_misses 6882 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 512 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 810 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 663 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2667 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2658 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1547 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1447 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5799755 # ITB inst accesses -system.cpu1.itb.hits 5792513 # DTB hits -system.cpu1.itb.misses 7242 # DTB misses -system.cpu1.itb.accesses 5799755 # DTB accesses -system.cpu1.numCycles 235437063 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5680717 # ITB inst accesses +system.cpu1.itb.hits 5673835 # DTB hits +system.cpu1.itb.misses 6882 # DTB misses +system.cpu1.itb.accesses 5680717 # DTB accesses +system.cpu1.numCycles 236975623 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14594322 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46143705 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7296861 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4549130 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10187153 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2325105 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84075 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48390355 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1773 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 50802 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1299927 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5790405 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352119 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3045 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76215873 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.749895 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.108619 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14429172 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45037398 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7298811 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4426577 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9907364 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2282600 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82705 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49394158 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1073 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44118 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1230431 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5671812 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 352198 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3013 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76664255 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724522 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076690 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66035998 86.64% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 646269 0.85% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 866115 1.14% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1144603 1.50% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1038380 1.36% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570616 0.75% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1298592 1.70% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 378941 0.50% 94.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4236359 5.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66765211 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 630389 0.82% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 841220 1.10% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1125492 1.47% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 998152 1.30% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 547084 0.71% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1279264 1.67% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 367549 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4109894 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76215873 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030993 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.195992 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15595502 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49311936 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9258524 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 522439 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1525385 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 986467 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 83299 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54522655 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 277301 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1525385 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16476975 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19655955 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 26515105 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8823591 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3216801 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52024243 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13429 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 607553 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2083322 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 488 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54254654 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237368382 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 219812592 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5012 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 40368418 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13886236 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 416636 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 371803 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6618695 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10010762 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6654363 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 928897 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1221940 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48420965 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1005597 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62096685 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94311 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9477685 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23931706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245448 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76215873 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814747 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.522121 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76664255 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030800 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190051 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15533095 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50132740 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8857878 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 647971 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1490380 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 961231 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85259 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 52933701 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 285543 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1490380 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16375879 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19322833 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27622785 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8617835 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3232383 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50467558 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 173 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 596710 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2000524 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 626 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52901652 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233465152 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213426027 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5240 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39335356 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13566296 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 577962 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 535418 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6495060 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9746539 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6334911 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 894923 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1137674 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 46958643 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 959615 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60863950 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 85447 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9232783 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23424311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 229955 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76664255 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793903 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504568 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53862159 70.67% 70.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6987914 9.17% 79.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3609115 4.74% 84.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3073312 4.03% 88.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6185840 8.12% 96.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1415029 1.86% 98.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 789705 1.04% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 228522 0.30% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64277 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54480181 71.06% 71.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7304682 9.53% 80.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3460273 4.51% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2866704 3.74% 88.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6125054 7.99% 96.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1372858 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 769548 1.00% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222824 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62131 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76215873 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76664255 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 30122 0.69% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4155854 94.74% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200598 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29010 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4179738 94.96% 95.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 192807 4.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 197857 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29468242 47.46% 47.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46687 0.08% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 846 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26218549 42.22% 90.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6164475 9.93% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 12555 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28808011 47.33% 47.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45980 0.08% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 867 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26140692 42.95% 90.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5855817 9.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62096685 # Type of FU issued -system.cpu1.iq.rate 0.263751 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4386578 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070641 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 204926211 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58913069 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43552448 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11222 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6050 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4957 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66279422 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5984 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 320383 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60863950 # Type of FU issued +system.cpu1.iq.rate 0.256836 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4401559 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072318 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 202912608 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57159577 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42178137 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11121 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6181 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5062 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65247126 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5828 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 310626 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2041284 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2958 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15466 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 770955 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1995012 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2960 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15279 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 746422 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16877302 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331906 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17045290 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332871 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1525385 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14957873 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 224833 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49549209 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 95185 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10010762 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6654363 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 720304 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50705 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4281 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15466 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 171203 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135670 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 306873 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61058870 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25897367 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1037815 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1490380 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14881654 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 224199 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48035025 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 95776 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9746539 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6334911 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 685011 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49572 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 5137 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15279 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166909 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 134382 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301291 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59839107 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25823960 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1024843 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 122647 # number of nop insts executed -system.cpu1.iew.exec_refs 32008147 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5821795 # Number of branches executed -system.cpu1.iew.exec_stores 6110780 # Number of stores executed -system.cpu1.iew.exec_rate 0.259343 # Inst execution rate -system.cpu1.iew.wb_sent 60589807 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43557405 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24211075 # num instructions producing a value -system.cpu1.iew.wb_consumers 44594441 # num instructions consuming a value +system.cpu1.iew.exec_nop 116767 # number of nop insts executed +system.cpu1.iew.exec_refs 31629946 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5849908 # Number of branches executed +system.cpu1.iew.exec_stores 5805986 # Number of stores executed +system.cpu1.iew.exec_rate 0.252512 # Inst execution rate +system.cpu1.iew.wb_sent 59372558 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42183199 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23508004 # num instructions producing a value +system.cpu1.iew.wb_consumers 42759548 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.185007 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.542917 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178006 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549772 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9363446 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 760149 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 265641 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74690488 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.532256 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.520816 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9155270 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 729660 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260542 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75173875 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511996 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483358 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60561931 81.08% 81.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6932594 9.28% 90.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1961063 2.63% 92.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1092193 1.46% 94.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1024970 1.37% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 536622 0.72% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 713910 0.96% 97.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 380912 0.51% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1486293 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60919870 81.04% 81.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7446257 9.91% 90.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1922213 2.56% 93.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1068282 1.42% 94.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 820469 1.09% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 498258 0.66% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 699309 0.93% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369578 0.49% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1429639 1.90% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74690488 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31194382 # Number of instructions committed -system.cpu1.commit.committedOps 39754477 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75173875 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30400176 # Number of instructions committed +system.cpu1.commit.committedOps 38488707 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13852886 # Number of memory references committed -system.cpu1.commit.loads 7969478 # Number of loads committed -system.cpu1.commit.membars 200339 # Number of memory barriers committed -system.cpu1.commit.branches 5070949 # Number of branches committed -system.cpu1.commit.fp_insts 4906 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35178713 # Number of committed integer instructions. -system.cpu1.commit.function_calls 493679 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1486293 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13340016 # Number of memory references committed +system.cpu1.commit.loads 7751527 # Number of loads committed +system.cpu1.commit.membars 193715 # Number of memory barriers committed +system.cpu1.commit.branches 5124652 # Number of branches committed +system.cpu1.commit.fp_insts 5013 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34222153 # Number of committed integer instructions. +system.cpu1.commit.function_calls 482564 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1429639 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 121392021 # The number of ROB reads -system.cpu1.rob.rob_writes 99804752 # The number of ROB writes -system.cpu1.timesIdled 864703 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159221190 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2318646914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31111502 # Number of Instructions Simulated -system.cpu1.committedOps 39671597 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 31111502 # Number of Instructions Simulated -system.cpu1.cpi 7.567525 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.567525 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132144 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132144 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 276724007 # number of integer regfile reads -system.cpu1.int_regfile_writes 44911737 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22398 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19708 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15283998 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429459 # number of misc regfile writes +system.cpu1.rob.rob_reads 120517356 # The number of ROB reads +system.cpu1.rob.rob_writes 96821590 # The number of ROB writes +system.cpu1.timesIdled 866519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160311368 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2319089759 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30321678 # Number of Instructions Simulated +system.cpu1.committedOps 38410209 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30321678 # Number of Instructions Simulated +system.cpu1.cpi 7.815386 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.815386 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127953 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127953 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271574951 # number of integer regfile reads +system.cpu1.int_regfile_writes 43566618 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45165 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42266 # number of floating regfile writes +system.cpu1.misc_regfile_reads 132802747 # number of misc regfile reads +system.cpu1.misc_regfile_writes 590318 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2239,17 +2382,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1518454987022 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518454987022 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1518454987022 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1518508564766 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518508564766 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1518508564766 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83065 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 6f15742b0..1d8001986 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -243,19 +318,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -270,10 +347,34 @@ system=system tracer=system.cpu1.tracer workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -281,6 +382,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -288,24 +390,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -313,6 +450,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -951,7 +1089,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index 4dfb66c84..fdcb49ed7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -11,8 +11,42 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 25848b995..16dc9f3ee 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:31:08 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 19:11:44 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x6f57400 0x6f57400 + 0: system.cpu1.isa: ISA system set to: 0x6f57400 0x6f57400 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e79723ba6..b41d3a6bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629717 # Number of seconds simulated -sim_ticks 2629717216500 # Number of ticks simulated -final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629734 # Number of seconds simulated +sim_ticks 2629733911500 # Number of ticks simulated +final_tick 2629733911500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 592417 # Simulator instruction rate (inst/s) -host_op_rate 753843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25873243563 # Simulator tick rate (ticks/s) -host_mem_usage 401372 # Number of bytes of host memory used -host_seconds 101.64 # Real time elapsed on the host -sim_insts 60212334 # Number of instructions simulated -sim_ops 76619433 # Number of ops (including micro ops) simulated +host_inst_rate 461706 # Simulator instruction rate (inst/s) +host_op_rate 587514 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20164609948 # Simulator tick rate (ticks/s) +host_mem_usage 422284 # Number of bytes of host memory used +host_seconds 130.41 # Real time elapsed on the host +sim_insts 60212552 # Number of instructions simulated +sim_ops 76619667 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4661584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 300040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4644312 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4399060 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 298016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689984 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1527272 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1489008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706264 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 404420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4416276 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 300040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704460 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3689920 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1526984 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1489296 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 72871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 72603 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6366 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68770 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690901 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57656 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381818 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372252 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811726 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47250805 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 69039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690912 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57655 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381746 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372324 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811725 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47250505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 113326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1772656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 114095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1766077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 154543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1672826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50964230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 113326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 154543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 580774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 566224 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550184 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47250805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 153787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1679362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50963900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 114095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 153787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1403153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 580661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566330 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1403153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47250505 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 113326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2353430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 114095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2346738 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 154543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2239050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690901 # Number of read requests accepted -system.physmem.writeReqs 811726 # Number of write requests accepted -system.physmem.readBursts 15690901 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811726 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004215808 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 153787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2245692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53514044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690912 # Number of read requests accepted +system.physmem.writeReqs 811725 # Number of write requests accepted +system.physmem.readBursts 15690912 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811725 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004216512 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6837952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706264 # Total written bytes from the system interface side +system.physmem.bytesWritten 6837440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706200 # Total written bytes from the system interface side system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704883 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4518 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 704890 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980392 # Per bank write bursts system.physmem.perBankRdBursts::1 980205 # Per bank write bursts system.physmem.perBankRdBursts::2 980222 # Per bank write bursts @@ -88,60 +88,60 @@ system.physmem.perBankRdBursts::8 980615 # Pe system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980154 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts system.physmem.perBankRdBursts::13 980093 # Per bank write bursts -system.physmem.perBankRdBursts::14 980155 # Per bank write bursts +system.physmem.perBankRdBursts::14 980167 # Per bank write bursts system.physmem.perBankRdBursts::15 980109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6731 # Per bank write bursts -system.physmem.perBankWrBursts::1 6599 # Per bank write bursts -system.physmem.perBankWrBursts::2 6610 # Per bank write bursts -system.physmem.perBankWrBursts::3 6672 # Per bank write bursts -system.physmem.perBankWrBursts::4 6746 # Per bank write bursts +system.physmem.perBankWrBursts::0 6735 # Per bank write bursts +system.physmem.perBankWrBursts::1 6596 # Per bank write bursts +system.physmem.perBankWrBursts::2 6612 # Per bank write bursts +system.physmem.perBankWrBursts::3 6671 # Per bank write bursts +system.physmem.perBankWrBursts::4 6747 # Per bank write bursts system.physmem.perBankWrBursts::5 7052 # Per bank write bursts -system.physmem.perBankWrBursts::6 7033 # Per bank write bursts -system.physmem.perBankWrBursts::7 6881 # Per bank write bursts -system.physmem.perBankWrBursts::8 7002 # Per bank write bursts -system.physmem.perBankWrBursts::9 6827 # Per bank write bursts -system.physmem.perBankWrBursts::10 6323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6122 # Per bank write bursts -system.physmem.perBankWrBursts::12 6612 # Per bank write bursts -system.physmem.perBankWrBursts::13 6399 # Per bank write bursts +system.physmem.perBankWrBursts::6 7031 # Per bank write bursts +system.physmem.perBankWrBursts::7 6880 # Per bank write bursts +system.physmem.perBankWrBursts::8 6999 # Per bank write bursts +system.physmem.perBankWrBursts::9 6828 # Per bank write bursts +system.physmem.perBankWrBursts::10 6320 # Per bank write bursts +system.physmem.perBankWrBursts::11 6125 # Per bank write bursts +system.physmem.perBankWrBursts::12 6609 # Per bank write bursts +system.physmem.perBankWrBursts::13 6397 # Per bank write bursts system.physmem.perBankWrBursts::14 6618 # Per bank write bursts -system.physmem.perBankWrBursts::15 6616 # Per bank write bursts +system.physmem.perBankWrBursts::15 6615 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629712785000 # Total gap between requests +system.physmem.totGap 2629729480000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6706 # Read request sizes (log2) +system.physmem.readPktSize::2 6718 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152163 # Read request sizes (log2) +system.physmem.readPktSize::6 152162 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754070 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57656 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1290849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1134741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1135188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3791353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2690884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2690157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2706986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 51561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 56279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1274921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1118631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1118848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3789956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2706257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2705513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2723130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 52826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,28 +157,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4975 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4687 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -189,299 +189,317 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11177.544033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1030.436917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16744.733089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23393 25.86% 25.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14737 16.29% 42.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2929 3.24% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2185 2.42% 47.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1403 1.55% 49.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1153 1.27% 50.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 940 1.04% 51.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1175 1.30% 52.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 610 0.67% 53.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 557 0.62% 54.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 555 0.61% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 601 0.66% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 293 0.32% 55.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 323 0.36% 56.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 207 0.23% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 643 0.71% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 173 0.19% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 139 0.15% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 211 0.23% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 108 0.12% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2249 2.49% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 135 0.15% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 71 0.08% 60.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 48 0.05% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 33 0.04% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 98 0.11% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 34 0.04% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 23 0.03% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 231 0.26% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 27 0.03% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 30 0.03% 61.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 143 0.16% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 12 0.01% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 18 0.02% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 17 0.02% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 22 0.02% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 12 0.01% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 205 0.23% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 20 0.02% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 404 0.45% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 18 0.02% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 8 0.01% 62.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 21 0.02% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 11 0.01% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 14 0.02% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 16 0.02% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 82 0.09% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 9 0.01% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 15 0.02% 62.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 35 0.04% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 129 0.14% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 9 0.01% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 7 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 283 0.31% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 5 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 10 0.01% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 6 0.01% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 5 0.01% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 11 0.01% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 8 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 271 0.30% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 14 0.02% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 4 0.00% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 9 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 136 0.15% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.00% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 11 0.01% 63.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 341 0.38% 64.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 2 0.00% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 14 0.02% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 4 0.00% 64.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 205 0.23% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 168 0.19% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 3 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 126 0.14% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 267 0.30% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 256 0.28% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 5 0.01% 65.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 65 0.07% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 454 0.50% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 66.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 9 0.01% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 2 0.00% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 192 0.21% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 261 0.29% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 193 0.21% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 9 0.01% 66.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 455 0.50% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 1 0.00% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 64 0.07% 67.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 5 0.01% 67.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 257 0.28% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 67.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 265 0.29% 67.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 124 0.14% 68.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 4 0.00% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 195 0.22% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11207 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 336 0.37% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 123 0.14% 68.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 266 0.29% 69.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 267 0.30% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 121 0.13% 69.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 75 0.08% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 4 0.00% 69.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 387 0.43% 70.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 197 0.22% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 78 0.09% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13895 1 0.00% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 129 0.14% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 206 0.23% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 65 0.07% 70.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 65 0.07% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 71 0.08% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 1 0.00% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 455 0.50% 71.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 66 0.07% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 131 0.14% 71.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 128 0.14% 71.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 401 0.44% 72.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 130 0.14% 72.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 129 0.14% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 68 0.08% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 460 0.51% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 1 0.00% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 71 0.08% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 66 0.07% 73.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 64 0.07% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 208 0.23% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 128 0.14% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 77 0.09% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 196 0.22% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 1 0.00% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 386 0.43% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 3 0.00% 74.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 72 0.08% 74.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 120 0.13% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 270 0.30% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 265 0.29% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 123 0.14% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 334 0.37% 75.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 195 0.22% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21824-21831 1 0.00% 75.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 3 0.00% 76.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 127 0.14% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 264 0.29% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22720-22727 1 0.00% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 255 0.28% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 5 0.01% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 65 0.07% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 452 0.50% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 9 0.01% 77.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 192 0.21% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 3 0.00% 77.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 259 0.29% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 1 0.00% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 193 0.21% 78.01% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::37632-37639 123 0.14% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 333 0.37% 86.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 195 0.22% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 125 0.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 265 0.29% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 256 0.28% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 5 0.01% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 65 0.07% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 452 0.50% 88.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 7 0.01% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 192 0.21% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 259 0.29% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 3 0.00% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 192 0.21% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 9 0.01% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 452 0.50% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 64 0.07% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 5 0.01% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 255 0.28% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42816-42823 1 0.00% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 264 0.29% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 126 0.14% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 194 0.21% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 335 0.37% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 123 0.14% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 264 0.29% 91.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 264 0.29% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 120 0.13% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 72 0.08% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 4 0.00% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 385 0.43% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 194 0.21% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 76 0.08% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 128 0.14% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 209 0.23% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 65 0.07% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 67 0.07% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 1 0.00% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 73 0.08% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 459 0.51% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 3 0.00% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 69 0.08% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48448-48455 1 0.00% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 129 0.14% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 129 0.14% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5220 5.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90454 # Bytes accessed per row activation -system.physmem.totQLat 377144928750 # Total ticks spent queuing -system.physmem.totMemAccLat 474552728750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454360000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18953440000 # Total ticks spent accessing banks -system.physmem.avgQLat 24035.94 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1207.93 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 90412 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11182.734327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1029.544171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16746.961445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23519 26.01% 26.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14711 16.27% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2935 3.25% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2119 2.34% 47.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1367 1.51% 49.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1185 1.31% 50.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 943 1.04% 51.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1073 1.19% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 614 0.68% 53.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 515 0.57% 54.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 541 0.60% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 575 0.64% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 297 0.33% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 299 0.33% 56.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 230 0.25% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 594 0.66% 56.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 170 0.19% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 148 0.16% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 128 0.14% 57.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 277 0.31% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 134 0.15% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2231 2.47% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 229 0.25% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 52 0.06% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 35 0.04% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 49 0.05% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 107 0.12% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 29 0.03% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 27 0.03% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 27 0.03% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 349 0.39% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 23 0.03% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 21 0.02% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 26 0.03% 61.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 89 0.10% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 16 0.02% 61.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 22 0.02% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 22 0.02% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 90 0.10% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 13 0.01% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 10 0.01% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 21 0.02% 61.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 65 0.07% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 13 0.01% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 15 0.02% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 14 0.02% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 339 0.37% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 16 0.02% 62.42% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::3840-3847 139 0.15% 63.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 14 0.02% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 9 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 13 0.01% 63.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 357 0.39% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 6 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 7 0.01% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 77 0.09% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 8 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 79 0.09% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 8 0.01% 63.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 9 0.01% 63.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 6 0.01% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 18 0.02% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 6 0.01% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 10 0.01% 63.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 10 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 276 0.31% 64.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 64.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 9 0.01% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 76 0.08% 64.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 164 0.18% 64.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 59 0.07% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 1 0.00% 64.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 301 0.33% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 129 0.14% 64.88% # Bytes accessed per row activation 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129 0.14% 66.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 66 0.07% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 512 0.57% 66.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 67 0.07% 66.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 130 0.14% 66.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 68 0.08% 66.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 266 0.29% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 2 0.00% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 69 0.08% 67.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 72 0.08% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.45% # Bytes accessed per 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+system.physmem.bytesPerActivate::48384-48391 73 0.08% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 66 0.07% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 2 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5357 5.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90412 # Bytes accessed per row activation +system.physmem.totQLat 377428295750 # Total ticks spent queuing +system.physmem.totMemAccLat 474604408250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454415000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18721697500 # Total ticks spent accessing banks +system.physmem.avgQLat 24053.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1193.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30243.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30247.14 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s @@ -492,13 +510,13 @@ system.physmem.busUtilRead 2.98 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 1.22 # Average write queue length when enqueuing -system.physmem.readRowHits 15616330 # Number of row buffer hits during reads -system.physmem.writeRowHits 90931 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.readRowHits 15616374 # Number of row buffer hits during reads +system.physmem.writeRowHits 90932 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.11 # Row buffer hit rate for writes -system.physmem.avgGap 159351.16 # Average gap between requests +system.physmem.avgGap 159352.08 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 2.38 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -511,259 +529,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54426353 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743636 # Transaction distribution -system.membus.trans_dist::ReadResp 16743636 # Transaction distribution +system.membus.throughput 54425977 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743649 # Transaction distribution +system.membus.trans_dist::ReadResp 16743649 # Transaction distribution system.membus.trans_dist::WriteReq 763424 # Transaction distribution system.membus.trans_dist::WriteResp 763424 # Transaction distribution -system.membus.trans_dist::Writeback 57656 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4518 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4518 # Transaction distribution -system.membus.trans_dist::ReadExReq 131342 # Transaction distribution -system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.trans_dist::Writeback 57655 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131340 # Transaction distribution +system.membus.trans_dist::ReadExResp 131340 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892570 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279449 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343513 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471520 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869661 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18869581 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125917 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125917 # Total data (bytes) +system.membus.tot_pkt_size::total 143125837 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143125837 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225680000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225677000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3756000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3756500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171618500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171612500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4990533473 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4990561725 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35076949500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62046 # number of replacements -system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use -system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574782383500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38213.733489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2749.245070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3097.480060 # Average occupied blocks per requestor +system.l2c.tags.replacements 62045 # number of replacements +system.l2c.tags.tagsinuse 51605.891965 # Cycle average of tags in use +system.l2c.tags.total_refs 1699472 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127428 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.336723 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574797983500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38210.959857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2799.685375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3087.560110 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4271.539066 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3273.867246 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583095 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4221.092196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3286.593539 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583053 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.041950 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.047264 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.042720 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.047112 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.064409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050149 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6484 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277508 # Number of tag accesses -system.l2c.tags.data_accesses 17277508 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits +system.l2c.tags.tag_accesses 17277894 # Number of tag accesses +system.l2c.tags.data_accesses 17277894 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9810 # number of ReadReq hits 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uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -915,39 +933,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790683 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471881 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471881 # Transaction distribution +system.toL2Bus.throughput 52790764 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471959 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471959 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763424 # Transaction distribution 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-system.toL2Bus.respLayer0.occupancy 3865648250 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865656500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4421117527 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4421145525 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13024000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13055000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30647250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30669250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48159799 # Throughput (bytes/s) +system.iobus.throughput 48159493 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution @@ -1057,147 +1075,189 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42583673750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42582472500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 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+system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6418 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6408 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 151 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7428230 # DTB read accesses -system.cpu0.dtb.write_accesses 5629845 # DTB write accesses +system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7428717 # DTB read accesses +system.cpu0.dtb.write_accesses 5625860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13049406 # DTB hits -system.cpu0.dtb.misses 8669 # DTB misses -system.cpu0.dtb.accesses 13058075 # DTB accesses -system.cpu0.itb.inst_hits 30610107 # ITB inst hits -system.cpu0.itb.inst_misses 3562 # ITB inst misses +system.cpu0.dtb.hits 13045920 # DTB hits +system.cpu0.dtb.misses 8657 # DTB misses +system.cpu0.dtb.accesses 13054577 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 30611798 # ITB inst hits +system.cpu0.itb.inst_misses 3559 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 666 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2748 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2782 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30613669 # ITB inst accesses -system.cpu0.itb.hits 30610107 # DTB hits -system.cpu0.itb.misses 3562 # DTB misses -system.cpu0.itb.accesses 30613669 # DTB accesses -system.cpu0.numCycles 2628235952 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30615357 # ITB inst accesses +system.cpu0.itb.hits 30611798 # DTB hits +system.cpu0.itb.misses 3559 # DTB misses +system.cpu0.itb.accesses 30615357 # DTB accesses +system.cpu0.numCycles 2628262709 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29990580 # Number of instructions committed -system.cpu0.committedOps 38158663 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34282971 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4584 # Number of float alu accesses -system.cpu0.num_func_calls 1059870 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3968282 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34282971 # number of integer instructions -system.cpu0.num_fp_insts 4584 # number of float instructions -system.cpu0.num_int_register_reads 196555242 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36964020 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3346 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1240 # number of times the floating registers were written -system.cpu0.num_mem_refs 13622094 # number of memory refs -system.cpu0.num_load_insts 7743834 # Number of load instructions -system.cpu0.num_store_insts 5878260 # Number of store instructions -system.cpu0.num_idle_cycles 2282805163.828333 # Number of idle cycles -system.cpu0.num_busy_cycles 345430788.171666 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131431 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868569 # Percentage of idle cycles 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written +system.cpu0.num_mem_refs 13619078 # number of memory refs +system.cpu0.num_load_insts 7744657 # Number of load instructions +system.cpu0.num_store_insts 5874421 # Number of store instructions +system.cpu0.num_idle_cycles 2288628005.429596 # Number of idle cycles +system.cpu0.num_busy_cycles 339634703.570404 # Number of busy cycles +system.cpu0.not_idle_fraction 0.129224 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.870776 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 856230 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.853093 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60649685 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 510.852804 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60649877 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 856742 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.791072 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20173406250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 217.243034 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy +system.cpu0.icache.tags.avg_refs 70.791297 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20177865250 # Cycle when the warmup percentage was hit. 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439357 # number of ReadReq misses +system.cpu0.icache.tags.tag_accesses 62363363 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62363363 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30194610 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30455267 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60649877 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30194610 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30455267 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60649877 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30194610 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30455267 # number of overall hits +system.cpu0.icache.overall_hits::total 60649877 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 417188 # number of ReadReq misses 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0.013929 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013636 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014220 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013628 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014227 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013636 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014220 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013628 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014227 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13647.206662 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.046955 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.997052 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13781.997052 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13647.206662 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.046955 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13781.997052 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13660.715313 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.779652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13789.011699 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13789.011699 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13660.715313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.779652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13789.011699 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1206,48 +1266,48 @@ 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StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123208 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 124411 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 123361 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247772 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11823140 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11970437 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793577 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11823140 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11970437 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793577 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027230 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027178 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024775 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024203 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048296 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045152 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046732 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026167 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025910 # miss rate for demand accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11820442 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11973181 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23793623 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11820442 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11973181 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23793623 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027224 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027185 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027205 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024735 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024243 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024489 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048147 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045313 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046736 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026147 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025930 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026037 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026167 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025910 # miss rate for overall accesses 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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14269.863383 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13862.229035 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27371.161182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27780.625274 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26962.721579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27371.161182 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14924.019245 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14771.616300 # average ReadReq miss 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# average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27778.092379 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27010.562985 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 27393.462931 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1377,77 +1437,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596450 # number of writebacks -system.cpu0.dcache.writebacks::total 596450 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182495 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 186610 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369105 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126878 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123539 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6016 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5563 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11579 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 309373 # number of demand (read+write) MSHR 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-system.cpu0.dcache.overall_mshr_miss_latency::total 15664180482 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91489795250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90582792250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182072587500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13259276491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12977158000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236434491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104749071741 # number of overall MSHR uncacheable cycles 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uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13263386492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12973041499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26236427991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104688854242 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103620052749 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208308906991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027185 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027205 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024735 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024243 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024489 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.045313 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046736 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026037 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026167 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026147 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025930 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026037 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12929.815885 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12762.909276 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12845.432194 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44044.222537 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43181.702661 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43618.712915 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11484.125665 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12261.324825 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11857.522239 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25690.249689 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24879.367223 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25284.300609 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12916.725575 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12766.148261 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12840.591872 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44100.375887 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43254.890577 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43682.270741 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11490.567613 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12195.125224 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.677893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25688.032870 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24926.939632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25306.628752 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1458,70 +1518,112 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7578699 # DTB read hits -system.cpu1.dtb.read_misses 7251 # DTB read misses -system.cpu1.dtb.write_hits 5604812 # DTB write hits -system.cpu1.dtb.write_misses 1846 # DTB write misses -system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7578222 # DTB read hits +system.cpu1.dtb.read_misses 7256 # DTB read misses +system.cpu1.dtb.write_hits 5608824 # DTB write hits +system.cpu1.dtb.write_misses 1858 # DTB write misses +system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6708 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6698 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7585950 # DTB read accesses -system.cpu1.dtb.write_accesses 5606658 # DTB write accesses +system.cpu1.dtb.perms_faults 234 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7585478 # DTB read accesses +system.cpu1.dtb.write_accesses 5610682 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13183511 # DTB hits -system.cpu1.dtb.misses 9097 # DTB misses -system.cpu1.dtb.accesses 13192608 # DTB accesses -system.cpu1.itb.inst_hits 30896338 # ITB inst hits -system.cpu1.itb.inst_misses 3789 # ITB inst misses +system.cpu1.dtb.hits 13187046 # DTB hits +system.cpu1.dtb.misses 9114 # DTB misses +system.cpu1.dtb.accesses 13196160 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 30894839 # ITB inst hits +system.cpu1.itb.inst_misses 3806 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 766 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 773 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2857 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2929 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30900127 # ITB inst accesses -system.cpu1.itb.hits 30896338 # DTB hits -system.cpu1.itb.misses 3789 # DTB misses -system.cpu1.itb.accesses 30900127 # DTB accesses -system.cpu1.numCycles 2631198481 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30898645 # ITB inst accesses +system.cpu1.itb.hits 30894839 # DTB hits +system.cpu1.itb.misses 3806 # DTB misses +system.cpu1.itb.accesses 30898645 # DTB accesses +system.cpu1.numCycles 2631205114 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30221754 # Number of instructions committed -system.cpu1.committedOps 38460770 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34602143 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5685 # Number of float alu accesses -system.cpu1.num_func_calls 1080538 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3981203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34602143 # number of integer instructions -system.cpu1.num_fp_insts 5685 # number of float instructions -system.cpu1.num_int_register_reads 198301383 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37233535 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4147 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1540 # number of times the floating registers were written -system.cpu1.num_mem_refs 13778426 # number of memory refs -system.cpu1.num_load_insts 7920474 # Number of load instructions -system.cpu1.num_store_insts 5857952 # Number of store instructions -system.cpu1.num_idle_cycles 2292395060.642381 # Number of idle cycles -system.cpu1.num_busy_cycles 338803420.357619 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128764 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871236 # Percentage of idle cycles +system.cpu1.committedInsts 30222584 # Number of instructions committed +system.cpu1.committedOps 38466237 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34785148 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5462 # Number of float alu accesses +system.cpu1.num_func_calls 1080322 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3981720 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34785148 # number of integer instructions +system.cpu1.num_fp_insts 5462 # number of float instructions +system.cpu1.num_int_register_reads 201769035 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37410979 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3860 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1604 # number of times the floating registers were written +system.cpu1.num_mem_refs 13781482 # number of memory refs +system.cpu1.num_load_insts 7919681 # Number of load instructions +system.cpu1.num_store_insts 5861801 # Number of store instructions +system.cpu1.num_idle_cycles 2292298207.924829 # Number of idle cycles +system.cpu1.num_busy_cycles 338906906.075172 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128803 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871197 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1540,10 +1642,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1557221573750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557221573750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1557221573750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1557253805500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557253805500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1557253805500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 09e0d3e34..fd7ad70a0 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 88b266667..c4b7fa411 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:37:28 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:10:45 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x50d0380 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -23,4 +24,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26911413000 because target called exit() +Exiting @ tick 26911921000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index f2d38a430..8c91cbc4e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026911 # Number of seconds simulated -sim_ticks 26911413000 # Number of ticks simulated -final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026912 # Number of seconds simulated +sim_ticks 26911921000 # Number of ticks simulated +final_tick 26911921000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180996 # Simulator instruction rate (inst/s) -host_op_rate 182296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53768206 # Simulator tick rate (ticks/s) -host_mem_usage 381936 # Number of bytes of host memory used -host_seconds 500.51 # Real time elapsed on the host +host_inst_rate 176190 # Simulator instruction rate (inst/s) +host_op_rate 177456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52341651 # Simulator tick rate (ticks/s) +host_mem_usage 402844 # Number of bytes of host memory used +host_seconds 514.16 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory -system.physmem.bytes_read::total 993152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 710 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15518 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1688503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35215988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36904491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1688503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1688503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1688503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35215988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36904491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15518 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947776 # Number of bytes read from this memory +system.physmem.bytes_read::total 993280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14809 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1690849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35217701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36908551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1690849 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1690849 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1690849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35217701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36908551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15520 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15518 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15520 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 993152 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 993280 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 993152 # Total read bytes from the system interface side +system.physmem.bytesReadSys 993280 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 987 # Per bank write bursts +system.physmem.perBankRdBursts::0 989 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::3 1029 # Per bank write bursts +system.physmem.perBankRdBursts::4 1049 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts -system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1080 # Per bank write bursts +system.physmem.perBankRdBursts::6 1079 # Per bank write bursts +system.physmem.perBankRdBursts::7 1079 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 959 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26911220500 # Total gap between requests +system.physmem.totGap 26911727500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15518 # Read request sizes (log2) +system.physmem.readPktSize::6 15520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -154,126 +154,126 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1598.759289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 481.680955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2200.761860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 153 24.72% 24.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 75 12.12% 36.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 40 6.46% 43.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 20 3.23% 46.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 12 1.94% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.97% 49.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 27 4.36% 53.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 12 1.94% 55.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.81% 56.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.62% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.48% 58.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.65% 59.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.81% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.29% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.48% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.97% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.65% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.97% 66.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.07% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.97% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.97% 71.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.48% 71.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.97% 73.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.97% 74.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.81% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.65% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.65% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.65% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.65% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.81% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.65% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.97% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 12 1.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 619 # Bytes accessed per row activation -system.physmem.totQLat 103760250 # Total ticks spent queuing -system.physmem.totMemAccLat 357130250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77590000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175780000 # Total ticks spent accessing banks -system.physmem.avgQLat 6686.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11327.49 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 622 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1591.562701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 476.433802 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2197.906875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 160 25.72% 25.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 68 10.93% 36.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 41 6.59% 43.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 21 3.38% 46.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 13 2.09% 48.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 6 0.96% 49.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 27 4.34% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 12 1.93% 55.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.80% 56.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.61% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.48% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.64% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.80% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.29% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.48% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 0.96% 63.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.32% 64.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.64% 65.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6 0.96% 66.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 19 3.05% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.96% 70.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.96% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.48% 72.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 6 0.96% 73.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 6 0.96% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.16% 76.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 5 0.80% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.64% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.64% 79.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.32% 80.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.16% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.64% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.64% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.80% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.64% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 6 0.96% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 2 0.32% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 12 1.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 622 # Bytes accessed per row activation +system.physmem.totQLat 103005000 # Total ticks spent queuing +system.physmem.totMemAccLat 356453750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77600000 # Total ticks spent in databus transfers +system.physmem.totBankLat 175848750 # Total ticks spent accessing banks +system.physmem.avgQLat 6636.92 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11330.46 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23013.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 22967.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage @@ -281,40 +281,61 @@ system.physmem.busUtilRead 0.29 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14899 # Number of row buffer hits during reads +system.physmem.readRowHits 14898 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.01 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734193.87 # Average gap between requests -system.physmem.pageHitRate 96.01 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36904491 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 980 # Transaction distribution -system.membus.trans_dist::ReadResp 980 # Transaction distribution +system.physmem.avgGap 1734003.06 # Average gap between requests +system.physmem.pageHitRate 95.99 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.99 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36908551 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 982 # Transaction distribution +system.membus.trans_dist::ReadResp 982 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31038 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 993152 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 993152 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31042 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31042 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 993280 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 993280 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19253000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19254500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 145212249 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26686306 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11366672 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11283030 # Number of BTB hits +system.cpu.branchPred.lookups 26683530 # Number of BP lookups +system.cpu.branchPred.condPredicted 22001633 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 843091 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366562 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11283436 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.264147 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70474 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 170 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.268679 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69998 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 165 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -336,6 +357,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -358,99 +400,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53822827 # number of cpu cycles simulated +system.cpu.numCycles 53823843 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14174375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127897951 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26686306 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11353504 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24037647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4766390 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11312706 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 108 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 14173676 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127895760 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26683530 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11353434 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24037387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4765940 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11314746 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13845393 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329438 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53431463 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410222 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13845039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329540 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53432137 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29432152 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389873 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028658 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1553769 2.91% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668148 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2920061 5.47% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1509677 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090745 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9838380 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29433098 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389468 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2029496 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1553729 2.91% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1668795 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2919650 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1509735 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090422 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9837744 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53431463 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495818 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.376277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16937925 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9159010 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22405754 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1030805 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897969 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444268 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8691 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126081524 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42632 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897969 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18719458 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3589629 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186437 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21552986 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5484984 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123156725 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 425837 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4596994 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1284 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143603336 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536446832 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 500029218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 672 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53432137 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495757 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.376192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937041 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9161066 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22405812 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1030640 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3897578 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444113 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8703 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126077551 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42669 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3897578 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18718868 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3591285 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186478 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21552610 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5485318 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123153621 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 426233 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4596906 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1480 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143604331 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536493258 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499981919 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 760 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36189150 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4635 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4633 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12540789 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29477429 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5520545 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151265 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1294097 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118170448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8500 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105167442 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79307 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26742090 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65583646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53431463 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968268 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908949 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36190145 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4605 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4603 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12541075 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29476574 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520683 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2151148 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1293650 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118168195 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8471 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105168426 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79356 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26740210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65568590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53432137 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.908954 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15374280 28.77% 28.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11649569 21.80% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8250468 15.44% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6827782 12.78% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4953380 9.27% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2948609 5.52% 93.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2456731 4.60% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528512 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442132 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15374181 28.77% 28.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11650585 21.80% 50.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8250698 15.44% 66.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6826591 12.78% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4953996 9.27% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2948586 5.52% 93.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2456814 4.60% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528614 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442072 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53431463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53432137 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45750 6.92% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45737 6.91% 6.91% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available @@ -479,13 +521,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340320 51.44% 58.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275443 41.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340297 51.45% 58.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275411 41.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74429619 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10979 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74430007 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -507,90 +549,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 129 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 130 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 165 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25613153 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113394 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25613380 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5113753 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105167442 # Type of FU issued -system.cpu.iq.rate 1.953956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661540 # FU busy when requested +system.cpu.iq.FU_type_0::total 105168426 # Type of FU issued +system.cpu.iq.rate 1.953938 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661472 # FU busy when requested system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264506537 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144925816 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102691564 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 657 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 923 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105828655 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441760 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 264509133 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144921601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102693545 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 684 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 985 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 281 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105829562 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441614 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6903463 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6716 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6442 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 775701 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6902608 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6756 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6465 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775839 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31606 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31615 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897969 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 957023 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126637 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118191644 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310003 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29477429 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5520545 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4612 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6738 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6442 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447212 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446019 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 893231 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104191675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25292948 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975767 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3897578 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 958412 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 126923 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118189357 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310100 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29476574 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520683 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4583 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 65855 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6705 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6465 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447219 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445977 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893196 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104191790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292626 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 976636 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12696 # number of nop insts executed -system.cpu.iew.exec_refs 30349771 # number of memory reference insts executed -system.cpu.iew.exec_branches 21326762 # Number of branches executed -system.cpu.iew.exec_stores 5056823 # Number of stores executed -system.cpu.iew.exec_rate 1.935827 # Inst execution rate -system.cpu.iew.wb_sent 102970942 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102691851 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62249009 # num instructions producing a value -system.cpu.iew.wb_consumers 104309545 # num instructions consuming a value +system.cpu.iew.exec_nop 12691 # number of nop insts executed +system.cpu.iew.exec_refs 30349836 # number of memory reference insts executed +system.cpu.iew.exec_branches 21326689 # Number of branches executed +system.cpu.iew.exec_stores 5057210 # Number of stores executed +system.cpu.iew.exec_rate 1.935792 # Inst execution rate +system.cpu.iew.wb_sent 102971901 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102693826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62250392 # num instructions producing a value +system.cpu.iew.wb_consumers 104309215 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596772 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596787 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26941617 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26939334 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834570 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49533494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842248 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540561 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 834485 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49534559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842208 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540547 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20042935 40.46% 40.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146551 26.54% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167484 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431298 6.93% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1535317 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 726626 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954928 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253259 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275096 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20043988 40.46% 40.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13146531 26.54% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4167490 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431351 6.93% 82.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1535298 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 726633 1.47% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 954931 1.93% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253243 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275094 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49533494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49534559 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,105 +643,105 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275096 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275094 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162447241 # The number of ROB reads -system.cpu.rob.rob_writes 240306728 # The number of ROB writes -system.cpu.timesIdled 46009 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 391364 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162446025 # The number of ROB reads +system.cpu.rob.rob_writes 240301749 # The number of ROB writes +system.cpu.timesIdled 46102 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 391706 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594138 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683111 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683111 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495604527 # number of integer regfile reads -system.cpu.int_regfile_writes 120552200 # number of integer regfile writes -system.cpu.fp_regfile_reads 148 # number of floating regfile reads -system.cpu.fp_regfile_writes 360 # number of floating regfile writes -system.cpu.misc_regfile_reads 29090078 # number of misc regfile reads +system.cpu.cpi 0.594149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594149 # CPI: Total CPI of All Threads +system.cpu.ipc 1.683079 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.683079 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495606364 # number of integer regfile reads +system.cpu.int_regfile_writes 120553547 # number of integer regfile writes +system.cpu.fp_regfile_reads 143 # number of floating regfile reads +system.cpu.fp_regfile_writes 349 # number of floating regfile writes +system.cpu.misc_regfile_reads 29209842 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497665284 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942892 # Transaction distribution +system.cpu.toL2Bus.throughput 4497544713 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942884 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43700 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43700 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1472 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839564 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120991360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121038400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121038400 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 43696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43696 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1476 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838066 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120990272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121037440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121037440 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888506500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 1888491000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1222499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1225749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424110491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1424096491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 632.612747 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13844401 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 735 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18835.919728 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.652083 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844045 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 737 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18784.321574 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 732 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 632.652083 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 734 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.357422 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27691521 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27691521 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13844401 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13844401 # number of overall hits -system.cpu.icache.overall_hits::total 13844401 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 991 # number of overall misses -system.cpu.icache.overall_misses::total 991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67770748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67770748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67770748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67770748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67770748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67770748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13845392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13845392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13845392 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13845392 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13845392 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13845392 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_task_id_percent::1024 0.358398 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27690815 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27690815 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13844045 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844045 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844045 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844045 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844045 # number of overall hits +system.cpu.icache.overall_hits::total 13844045 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 993 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 993 # number of overall misses +system.cpu.icache.overall_misses::total 993 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66969998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66969998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66969998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66969998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66969998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66969998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845038 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845038 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845038 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845038 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845038 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845038 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68386.224016 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68386.224016 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68386.224016 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68386.224016 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68386.224016 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 651 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67442.092649 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67442.092649 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67442.092649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67442.092649 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 594 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -709,131 +751,131 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 254 system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51712250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51712250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51712250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51712250 # number of demand (read+write) MSHR miss cycles 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demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50789000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50789000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50789000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70165.875170 # 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41786750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797491750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 839278500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780533500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780533500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40836000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797802750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 838638750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40836000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797802750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 838638750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001086 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332677 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332677 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965986 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58854.577465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64585.185185 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60433.418367 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016366 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016366 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57434.599156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63724.169742 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59170.315682 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53656.194112 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53656.194112 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58854.577465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53855.466640 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54084.192551 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53689.193837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53689.193837 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53872.830711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54036.001933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.701049 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.741279 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896421 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896421 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 448 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3128 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3140 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59988680 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59988680 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532846 # number of WriteReq hits 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demand (read+write) hits -system.cpu.dcache.demand_hits::total 28136618 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28136618 # number of overall hits -system.cpu.dcache.overall_hits::total 28136618 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173981 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173981 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202135 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202135 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28136588 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136588 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136588 # number of overall hits +system.cpu.dcache.overall_hits::total 28136588 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173883 # number of ReadReq misses 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miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8458649331 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376014 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376014 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376014 # number of overall misses +system.cpu.dcache.overall_misses::total 1376014 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893935229 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13893935229 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8459874583 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8459874583 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22353097810 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22353097810 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22353097810 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22353097810 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24777753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24777753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22353809812 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22353809812 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22353809812 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22353809812 # number of overall miss cycles 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-system.cpu.dcache.demand_accesses::cpu.data 29512734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29512734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29512734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29512734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047380 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047380 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042690 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042690 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046628 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046628 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046628 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046628 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.326533 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.326533 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41846.534895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41846.534895 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047377 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047377 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042689 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042689 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.877365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.877365 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41853.424675 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41853.424675 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16243.614499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16243.614499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16243.614499 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154190 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16245.336030 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16245.336030 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154233 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.436115 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.439522 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942892 # number of writebacks -system.cpu.dcache.writebacks::total 942892 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270066 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 270066 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks +system.cpu.dcache.writebacks::total 942884 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269973 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269973 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428516 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428516 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428516 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428516 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903915 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903915 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43685 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43685 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947600 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947600 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947600 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947600 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994483010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994483010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1318924416 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1318924416 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313407426 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313407426 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313407426 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313407426 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 428423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903910 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903910 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43681 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43681 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947591 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947591 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947591 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947591 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994274260 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994274260 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319346668 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319346668 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313620928 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11313620928 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313620928 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11313620928 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009226 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009226 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.883678 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.883678 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30191.700034 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30191.700034 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.011636 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.011636 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.713899 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.713899 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30204.131499 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30204.131499 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 8155e41d5..000056a51 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 35b926dc8..c759bbe65 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:39:34 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:11:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x63b66c0 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index be3e03048..0430a3e3f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2327254 # Simulator instruction rate (inst/s) -host_op_rate 2343964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1393249116 # Simulator tick rate (ticks/s) -host_mem_usage 371180 # Number of bytes of host memory used -host_seconds 38.93 # Real time elapsed on the host +host_inst_rate 2151308 # Simulator instruction rate (inst/s) +host_op_rate 2166754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1287915883 # Simulator tick rate (ticks/s) +host_mem_usage 391064 # Number of bytes of host memory used +host_seconds 42.12 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9960199711 # Th system.membus.data_through_bus 540247816 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 112245 # nu system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read +system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index f9a7d69b3..5e43af11f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 92da3b737..ea901fcca 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:40:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:12:31 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5565040 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index f99edcca6..a1028c3a3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1334589 # Simulator instruction rate (inst/s) -host_op_rate 1344158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2167949307 # Simulator tick rate (ticks/s) -host_mem_usage 379884 # Number of bytes of host memory used -host_seconds 67.87 # Real time elapsed on the host +host_inst_rate 1098833 # Simulator instruction rate (inst/s) +host_op_rate 1106711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1784978875 # Simulator tick rate (ticks/s) +host_mem_usage 400800 # Number of bytes of host memory used +host_seconds 82.43 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 112245 # nu system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read +system.cpu.num_int_register_reads 464618159 # number of times the integer registers were read system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index d70753e9b..b9d303473 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 0f922bcc1..980a69a9d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:41:42 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:14:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4cfd380 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -67,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 202741893000 because target called exit() +Exiting @ tick 202696649500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 3185557ef..4ea8f08d5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202742 # Number of seconds simulated -sim_ticks 202741893000 # Number of ticks simulated -final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202697 # Number of seconds simulated +sim_ticks 202696649500 # Number of ticks simulated +final_tick 202696649500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148118 # Simulator instruction rate (inst/s) -host_op_rate 166994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59436990 # Simulator tick rate (ticks/s) -host_mem_usage 253144 # Number of bytes of host memory used -host_seconds 3411.04 # Real time elapsed on the host +host_inst_rate 142513 # Simulator instruction rate (inst/s) +host_op_rate 160675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57175030 # Simulator tick rate (ticks/s) +host_mem_usage 274024 # Number of bytes of host memory used +host_seconds 3545.20 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148209 # Number of read requests accepted -system.physmem.writeReqs 97655 # Number of write requests accepted -system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9269696 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6249792 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249792 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3374 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144839 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148213 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97653 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97653 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1065316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45731866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46797182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1065316 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1065316 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30833228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30833228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30833228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1065316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45731866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77630410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148213 # Number of read requests accepted +system.physmem.writeReqs 97653 # Number of write requests accepted +system.physmem.readBursts 148213 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97653 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9481152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue +system.physmem.bytesWritten 6249152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9485632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6249792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9585 # Per bank write bursts -system.physmem.perBankRdBursts::1 9243 # Per bank write bursts -system.physmem.perBankRdBursts::2 9257 # Per bank write bursts -system.physmem.perBankRdBursts::3 8972 # Per bank write bursts -system.physmem.perBankRdBursts::4 9761 # Per bank write bursts -system.physmem.perBankRdBursts::5 9639 # Per bank write bursts -system.physmem.perBankRdBursts::6 9125 # Per bank write bursts -system.physmem.perBankRdBursts::7 8321 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 7 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9594 # Per bank write bursts +system.physmem.perBankRdBursts::1 9237 # Per bank write bursts +system.physmem.perBankRdBursts::2 9258 # Per bank write bursts +system.physmem.perBankRdBursts::3 8983 # Per bank write bursts +system.physmem.perBankRdBursts::4 9776 # Per bank write bursts +system.physmem.perBankRdBursts::5 9641 # Per bank write bursts +system.physmem.perBankRdBursts::6 9120 # Per bank write bursts +system.physmem.perBankRdBursts::7 8318 # Per bank write bursts system.physmem.perBankRdBursts::8 8799 # Per bank write bursts -system.physmem.perBankRdBursts::9 8911 # Per bank write bursts -system.physmem.perBankRdBursts::10 8951 # Per bank write bursts -system.physmem.perBankRdBursts::11 9736 # Per bank write bursts -system.physmem.perBankRdBursts::12 9644 # Per bank write bursts -system.physmem.perBankRdBursts::13 9766 # Per bank write bursts -system.physmem.perBankRdBursts::14 8945 # Per bank write bursts -system.physmem.perBankRdBursts::15 9461 # Per bank write bursts -system.physmem.perBankWrBursts::0 6262 # Per bank write bursts -system.physmem.perBankWrBursts::1 6160 # Per bank write bursts -system.physmem.perBankWrBursts::2 6087 # Per bank write bursts -system.physmem.perBankWrBursts::3 5881 # Per bank write bursts -system.physmem.perBankWrBursts::4 6253 # Per bank write bursts -system.physmem.perBankWrBursts::5 6276 # Per bank write bursts -system.physmem.perBankWrBursts::6 6048 # Per bank write bursts -system.physmem.perBankWrBursts::7 5555 # Per bank write bursts -system.physmem.perBankWrBursts::8 5811 # Per bank write bursts -system.physmem.perBankWrBursts::9 5907 # Per bank write bursts -system.physmem.perBankWrBursts::10 5994 # Per bank write bursts -system.physmem.perBankWrBursts::11 6518 # Per bank write bursts -system.physmem.perBankWrBursts::12 6370 # Per bank write bursts -system.physmem.perBankWrBursts::13 6328 # Per bank write bursts -system.physmem.perBankWrBursts::14 6055 # Per bank write bursts -system.physmem.perBankWrBursts::15 6145 # Per bank write bursts +system.physmem.perBankRdBursts::9 8914 # Per bank write bursts +system.physmem.perBankRdBursts::10 8952 # Per bank write bursts +system.physmem.perBankRdBursts::11 9727 # Per bank write bursts +system.physmem.perBankRdBursts::12 9657 # Per bank write bursts +system.physmem.perBankRdBursts::13 9778 # Per bank write bursts +system.physmem.perBankRdBursts::14 8939 # Per bank write bursts +system.physmem.perBankRdBursts::15 9450 # Per bank write bursts +system.physmem.perBankWrBursts::0 6271 # Per bank write bursts +system.physmem.perBankWrBursts::1 6158 # Per bank write bursts +system.physmem.perBankWrBursts::2 6091 # Per bank write bursts +system.physmem.perBankWrBursts::3 5883 # Per bank write bursts +system.physmem.perBankWrBursts::4 6254 # Per bank write bursts +system.physmem.perBankWrBursts::5 6272 # Per bank write bursts +system.physmem.perBankWrBursts::6 6041 # Per bank write bursts +system.physmem.perBankWrBursts::7 5553 # Per bank write bursts +system.physmem.perBankWrBursts::8 5808 # Per bank write bursts +system.physmem.perBankWrBursts::9 5908 # Per bank write bursts +system.physmem.perBankWrBursts::10 5990 # Per bank write bursts +system.physmem.perBankWrBursts::11 6516 # Per bank write bursts +system.physmem.perBankWrBursts::12 6373 # Per bank write bursts +system.physmem.perBankWrBursts::13 6333 # Per bank write bursts +system.physmem.perBankWrBursts::14 6051 # Per bank write bursts +system.physmem.perBankWrBursts::15 6141 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202741873000 # Total gap between requests +system.physmem.totGap 202696525000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148209 # Read request sizes (log2) +system.physmem.readPktSize::6 148213 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97655 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97653 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -130,175 +130,197 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4501 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.469277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.950297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.311281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32073 46.38% 46.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12750 18.44% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5391 7.80% 72.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3340 4.83% 77.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2388 3.45% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2364 3.42% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3443 4.98% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1961 2.84% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 807 1.17% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 577 0.83% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 471 0.68% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 358 0.52% 95.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 272 0.39% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 260 0.38% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 188 0.27% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 160 0.23% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 170 0.25% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 142 0.21% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 124 0.18% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 152 0.22% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 134 0.19% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 815 1.18% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 105 0.15% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 136 0.20% 99.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 89 0.13% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 48 0.07% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 64 0.09% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 20 0.03% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 34 0.05% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 21 0.03% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 9 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 15 0.02% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 7 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 10 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 5 0.01% 99.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 7 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 7 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 8 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 2 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 4 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 1 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 4 0.01% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 4 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 1 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 8 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 4 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation -system.physmem.totQLat 1735354000 # Total ticks spent queuing -system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks -system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::5376 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69151 # Bytes accessed per row activation +system.physmem.totQLat 1733842500 # Total ticks spent queuing +system.physmem.totMemAccLat 4938805000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740715000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2464247500 # Total ticks spent accessing banks +system.physmem.avgQLat 11703.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16634.25 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33338.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 46.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing -system.physmem.readRowHits 118629 # Number of row buffer hits during reads -system.physmem.writeRowHits 57942 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes -system.physmem.avgGap 824609.84 # Average gap between requests -system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77612139 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46927 # Transaction distribution -system.membus.trans_dist::ReadResp 46926 # Transaction distribution -system.membus.trans_dist::Writeback 97655 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 101282 # Transaction distribution -system.membus.trans_dist::ReadExResp 101282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735232 # Total data (bytes) +system.physmem.avgWrQLen 8.92 # Average write queue length when enqueuing +system.physmem.readRowHits 118670 # Number of row buffer hits during reads +system.physmem.writeRowHits 57965 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes +system.physmem.avgGap 824418.69 # Average gap between requests +system.physmem.pageHitRate 71.86 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.58 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77630410 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46935 # Transaction distribution +system.membus.trans_dist::ReadResp 46935 # Transaction distribution +system.membus.trans_dist::Writeback 97653 # Transaction distribution +system.membus.trans_dist::UpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 101278 # Transaction distribution +system.membus.trans_dist::ReadExResp 101278 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394093 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394093 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15735424 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735424 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083458000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398218993 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 182821881 # Number of BP lookups -system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits +system.cpu.branchPred.lookups 182767812 # Number of BP lookups +system.cpu.branchPred.condPredicted 143090812 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7262422 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93142512 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87193307 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.612793 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12680291 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116092 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -320,6 +342,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -342,99 +385,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405483787 # number of cpu cycles simulated +system.cpu.numCycles 405393300 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119358761 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761461935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182767812 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99873598 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170116443 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35667741 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77537943 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 427 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114511433 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2436940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394614975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164245 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986660 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224511182 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14185619 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22882928 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22735959 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20902964 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599090 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13052635 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11995684 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52748914 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 394614975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450841 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878329 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129045860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73029235 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158776788 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6235766 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27527326 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26113836 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825433505 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27527326 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135634392 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10115343 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47882338 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158241210 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15214366 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800503248 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1357 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3055222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8963577 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 323 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954180101 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3518022066 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3236814887 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 287927810 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293035 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293033 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41823481 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170244853 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73468690 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28584671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15947575 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 754970143 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775446 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665247715 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1368678 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187299729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479807189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797814 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394614975 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685815 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734907 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139112608 35.25% 35.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69963718 17.73% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71480339 18.11% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53412881 13.54% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31169155 7.90% 92.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15993671 4.05% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8759011 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2903101 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820491 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394614975 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480625 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -463,15 +506,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6529255 68.28% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2553152 26.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447743251 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383309 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -497,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153363071 23.05% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63757987 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued -system.cpu.iq.rate 1.640858 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665247715 # Type of FU issued +system.cpu.iq.rate 1.640993 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9563032 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014375 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736041890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946851577 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 645982069 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 225 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674810634 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8546846 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44215298 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41270 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810207 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16608213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8279 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27527326 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5271033 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 384981 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760303523 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1119045 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170244853 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73468690 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286904 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219731 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11453 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810207 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335544 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4001823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8337367 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655831134 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150081839 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9416581 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558919 # number of nop insts executed -system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed -system.cpu.iew.exec_branches 138505177 # Number of branches executed -system.cpu.iew.exec_stores 62475461 # Number of stores executed -system.cpu.iew.exec_rate 1.617619 # Inst execution rate -system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374710129 # num instructions producing a value -system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value +system.cpu.iew.exec_nop 1557934 # number of nop insts executed +system.cpu.iew.exec_refs 212547196 # number of memory reference insts executed +system.cpu.iew.exec_branches 138487054 # Number of branches executed +system.cpu.iew.exec_stores 62465357 # Number of stores executed +system.cpu.iew.exec_rate 1.617765 # Inst execution rate +system.cpu.iew.wb_sent 650951989 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 645982085 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374676308 # num instructions producing a value +system.cpu.iew.wb_consumers 646230138 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593470 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579788 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189364408 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7188399 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367087649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230509 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159393543 43.42% 43.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98511772 26.84% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33830447 9.22% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18783252 5.12% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16176645 4.41% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7442765 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6952611 1.89% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3163238 0.86% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22833376 6.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367087649 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -585,239 +628,239 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22833376 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104828701 # The number of ROB reads -system.cpu.rob.rob_writes 1548619548 # The number of ROB writes -system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104579710 # The number of ROB reads +system.cpu.rob.rob_writes 1548313166 # The number of ROB writes +system.cpu.timesIdled 328667 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10778325 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads -system.cpu.int_regfile_writes 752019512 # number of integer regfile writes +system.cpu.cpi 0.802381 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802381 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058357965 # number of integer regfile reads +system.cpu.int_regfile_writes 751931601 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads +system.cpu.misc_regfile_reads 237823379 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 733902057 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110906 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 71 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 71 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348829 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33629 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3537891 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1073600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147680832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148754432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148754432 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273126497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25848480 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1823961981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15017 # number of replacements -system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 14927 # number of replacements +system.cpu.icache.tags.tagsinuse 1097.546967 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114490465 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16785 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6820.998808 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1849 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.902832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 229105594 # Number of tag accesses -system.cpu.icache.tags.data_accesses 229105594 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114523215 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114523215 # number of overall hits -system.cpu.icache.overall_hits::total 114523215 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21116 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21116 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21116 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21116 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21116 # number of overall misses -system.cpu.icache.overall_misses::total 21116 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 569003980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 569003980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 569003980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 569003980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 569003980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 569003980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114544331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114544331 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114544331 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114544331 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114544331 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114544331 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26946.579845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26946.579845 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26946.579845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26946.579845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26946.579845 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1001 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1097.546967 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.535912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.535912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 229039718 # Number of tag accesses +system.cpu.icache.tags.data_accesses 229039718 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 114490465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114490465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114490465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114490465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114490465 # number of overall hits +system.cpu.icache.overall_hits::total 114490465 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20967 # number of overall misses +system.cpu.icache.overall_misses::total 20967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 566965977 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 566965977 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 566965977 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 566965977 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 566965977 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 566965977 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114511432 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114511432 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114511432 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114511432 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114511432 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114511432 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000183 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000183 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000183 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000183 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000183 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000183 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27040.872657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27040.872657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27040.872657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27040.872657 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 91 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4183 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4183 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4183 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4183 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4183 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4183 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16933 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16933 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16933 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16933 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16933 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16933 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 412315016 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 412315016 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 412315016 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 412315016 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 412315016 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 412315016 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24349.791295 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24349.791295 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24349.791295 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24349.791295 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4113 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16854 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16854 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16854 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16854 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16854 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16854 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 413760769 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 413760769 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 413760769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 413760769 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 413760769 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 413760769 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24549.707429 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24549.707429 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24549.707429 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24549.707429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24549.707429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24549.707429 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115463 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27089.747444 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1781862 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146718 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.144808 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 115464 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27088.798678 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1780777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146712 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.137910 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 102535173000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23009.564484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.930795 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3719.252164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31255 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 23012.092696 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 360.882153 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3715.823828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.702273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011013 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113398 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.826685 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31248 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 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MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9429511502 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051383 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.070423 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.070423 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290343 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290343 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122150 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121043 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65125.074096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67596.106609 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67418.472355 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61835.189528 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61835.189528 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64655.023781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63603.183733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63627.057898 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860.441370 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860.441370 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65125.074096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63585.445433 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63620.493891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65125.074096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63585.445433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63620.493891 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192730 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.514955 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190201285 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196826 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.921418 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1192511 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.506365 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190177939 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196607 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.930993 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.506365 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990602 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990602 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391502938 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391502938 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988251 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488825 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488825 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 391455847 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 391455847 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 136212044 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136212044 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988351 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488804 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488804 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits -system.cpu.dcache.overall_hits::total 187223724 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses 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WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187200395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187200395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187200395 # number of overall hits +system.cpu.dcache.overall_hits::total 187200395 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3250955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3250955 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4951844 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4951844 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4951844 # number of overall misses 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102205282441 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137912933 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137912933 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488840 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488840 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192152239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192152239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192152239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192152239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012333 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012333 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059937 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059937 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025770 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025770 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025770 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025770 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17456.499343 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17456.499343 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22305.357881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22305.357881 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16541.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16541.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20639.842944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20639.842944 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17574 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52604 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1663 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.567649 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.582451 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks -system.cpu.dcache.writebacks::total 1110997 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1110906 # number of writebacks +system.cpu.dcache.writebacks::total 1110906 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852565 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852565 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902601 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902601 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3755166 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3755166 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3755166 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3755166 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848324 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848324 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348354 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348354 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196678 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196678 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196678 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196678 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12420423026 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12420423026 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10423297989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10423297989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22843721015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22843721015 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22843721015 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22843721015 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14641.131249 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14641.131249 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29921.568258 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29921.568258 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 3b7a89fcb..b14a667a9 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index edefc9939..af6242a6d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:44:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:19:30 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5d016c0 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index d2cbe9ffb..a575cce26 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498967000 # Number of ticks simulated final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2346027 # Simulator instruction rate (inst/s) -host_op_rate 2644207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345327991 # Simulator tick rate (ticks/s) -host_mem_usage 241300 # Number of bytes of host memory used -host_seconds 215.93 # Real time elapsed on the host +host_inst_rate 2103217 # Simulator instruction rate (inst/s) +host_op_rate 2370536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1206088561 # Simulator tick rate (ticks/s) +host_mem_usage 262216 # Number of bytes of host memory used +host_seconds 240.86 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 570968167 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9312824252 # Th system.membus.data_through_bus 2705365825 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 19311615 # nu system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read +system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index cc298b9ef..ac28a9b86 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 13fa82ee3..36fd0e9c5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:45:59 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:21:27 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x6322040 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index feaf610e8..8fb3b6819 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu sim_ticks 717366012000 # Number of ticks simulated final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1243497 # Simulator instruction rate (inst/s) -host_op_rate 1401211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1766466230 # Simulator tick rate (ticks/s) -host_mem_usage 251064 # Number of bytes of host memory used -host_seconds 406.10 # Real time elapsed on the host +host_inst_rate 1131056 # Simulator instruction rate (inst/s) +host_op_rate 1274509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1606737202 # Simulator tick rate (ticks/s) +host_mem_usage 271980 # Number of bytes of host memory used +host_seconds 446.47 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.1 # La system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 19311615 # nu system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read +system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 9e26a822b..2cd58faa0 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 704a64531..d9e911681 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:48:11 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:23:42 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4718040 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -13,4 +14,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68509635500 because target called exit() +Exiting @ tick 68503867000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d1e8937b6..634fe5f9a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068510 # Number of seconds simulated -sim_ticks 68509635500 # Number of ticks simulated -final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068504 # Number of seconds simulated +sim_ticks 68503867000 # Number of ticks simulated +final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157844 # Simulator instruction rate (inst/s) -host_op_rate 201796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39605771 # Simulator tick rate (ticks/s) -host_mem_usage 257252 # Number of bytes of host memory used -host_seconds 1729.79 # Real time elapsed on the host +host_inst_rate 147835 # Simulator instruction rate (inst/s) +host_op_rate 189000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37091215 # Simulator tick rate (ticks/s) +host_mem_usage 278164 # Number of bytes of host memory used +host_seconds 1846.90 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory -system.physmem.bytes_read::total 466944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 194560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 194560 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4256 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7296 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3975849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6815742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3975849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6815742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7296 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory +system.physmem.bytes_read::total 466240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7286 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7296 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466944 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466944 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 607 # Per bank write bursts -system.physmem.perBankRdBursts::1 801 # Per bank write bursts +system.physmem.perBankRdBursts::0 606 # Per bank write bursts +system.physmem.perBankRdBursts::1 800 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 356 # Per bank write bursts -system.physmem.perBankRdBursts::6 162 # Per bank write bursts -system.physmem.perBankRdBursts::7 220 # Per bank write bursts +system.physmem.perBankRdBursts::4 443 # Per bank write bursts +system.physmem.perBankRdBursts::5 354 # Per bank write bursts +system.physmem.perBankRdBursts::6 164 # Per bank write bursts +system.physmem.perBankRdBursts::7 219 # Per bank write bursts system.physmem.perBankRdBursts::8 207 # Per bank write bursts -system.physmem.perBankRdBursts::9 294 # Per bank write bursts -system.physmem.perBankRdBursts::10 324 # Per bank write bursts -system.physmem.perBankRdBursts::11 416 # Per bank write bursts +system.physmem.perBankRdBursts::9 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 322 # Per bank write bursts +system.physmem.perBankRdBursts::11 415 # Per bank write bursts system.physmem.perBankRdBursts::12 529 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts system.physmem.perBankRdBursts::14 611 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68509447000 # Total gap between requests +system.physmem.totGap 68503846500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7296 # Read request sizes (log2) +system.physmem.readPktSize::6 7286 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,80 +154,83 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 364.419405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.521659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 755.556461 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 528 41.31% 41.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 217 16.98% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 132 10.33% 68.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 73 5.71% 74.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 38 2.97% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 36 2.82% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.35% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 40 3.13% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 1.17% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 24 1.88% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 7 0.55% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.02% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 4 0.31% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.78% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.39% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.47% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 7 0.55% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.55% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.23% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 4 0.31% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.23% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 6 0.47% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 5 0.39% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.39% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.16% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 5 0.39% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 4 0.31% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.16% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.23% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.16% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.16% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.16% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.08% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1278 # Bytes accessed per row activation -system.physmem.totQLat 61296000 # Total ticks spent queuing -system.physmem.totMemAccLat 197202250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36480000 # Total ticks spent in databus transfers -system.physmem.totBankLat 99426250 # Total ticks spent accessing banks -system.physmem.avgQLat 8401.32 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13627.50 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation +system.physmem.totQLat 62980000 # Total ticks spent queuing +system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers +system.physmem.totBankLat 98670000 # Total ticks spent accessing banks +system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27028.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.82 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -235,40 +238,61 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6018 # Number of row buffer hits during reads +system.physmem.readRowHits 6000 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9390000.96 # Average gap between requests -system.physmem.pageHitRate 82.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6815742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4471 # Transaction distribution -system.membus.trans_dist::ReadResp 4471 # Transaction distribution +system.physmem.avgGap 9402120.02 # Average gap between requests +system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6806039 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4462 # Transaction distribution +system.membus.trans_dist::ReadResp 4461 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 2825 # Transaction distribution -system.membus.trans_dist::ReadExResp 2825 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14596 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466944 # Total data (bytes) +system.membus.trans_dist::ReadExReq 2824 # Transaction distribution +system.membus.trans_dist::ReadExResp 2824 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466240 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8937500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35425567 # Number of BP lookups -system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19605313 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16823422 # Number of BTB hits +system.cpu.branchPred.lookups 35407535 # Number of BP lookups +system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.810525 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6781780 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8434 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -290,6 +314,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -312,100 +357,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137019272 # number of cpu cycles simulated +system.cpu.numCycles 137007735 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39008530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 318058207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35425567 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23605202 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70950828 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6887573 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21494775 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1573 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37609299 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 515132 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136671204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454359 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66353464 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6794042 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5704725 4.17% 57.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6102503 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4920388 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4084365 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3186134 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4139625 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35385958 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136671204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258544 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.321266 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45524127 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16648036 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66820925 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2531461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5146655 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7342433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401839978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 214083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5146655 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51074305 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1910036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63741314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14466395 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394244633 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 55 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1658642 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10186296 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1132 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432779208 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2333721873 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575557795 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200430073 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48213015 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11816 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11815 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36510705 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103606610 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91402094 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4304684 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5331956 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384603029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22794 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374241110 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1211414 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34812310 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 87759919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 674 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136671204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738259 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024772 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25129949 18.39% 18.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19927179 14.58% 32.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20562891 15.05% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18173263 13.30% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24036101 17.59% 78.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15736190 11.51% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814920 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3372202 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 918509 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136671204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8708 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4694 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -424,22 +469,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46360 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7648 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 433 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190801 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4328 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241338 1.36% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9265240 52.28% 55.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7952555 44.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126474576 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175710 0.58% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued @@ -450,7 +495,7 @@ system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued @@ -458,93 +503,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6781686 1.81% 36.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8476200 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430464 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1596092 0.43% 39.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20867035 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7174148 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130628 1.91% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101661693 27.16% 76.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88297588 23.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374241110 # Type of FU issued -system.cpu.iq.rate 2.731303 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17722107 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047355 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654665747 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 289075917 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250124446 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249421198 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130376340 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118073548 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263342959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128620258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11085750 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued +system.cpu.iq.rate 2.731341 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8957862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109225 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9026511 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 173986 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1905 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5146655 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 274797 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35672 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384627381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 873173 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103606610 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91402094 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11760 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1300817 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 370830 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1671647 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370280641 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100372061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3960469 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558 # number of nop insts executed -system.cpu.iew.exec_refs 187586293 # number of memory reference insts executed -system.cpu.iew.exec_branches 32011507 # Number of branches executed -system.cpu.iew.exec_stores 87214232 # Number of stores executed -system.cpu.iew.exec_rate 2.702398 # Inst execution rate -system.cpu.iew.wb_sent 368867964 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368197994 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183086265 # num instructions producing a value -system.cpu.iew.wb_consumers 363871713 # num instructions consuming a value +system.cpu.iew.exec_nop 1661 # number of nop insts executed +system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed +system.cpu.iew.exec_branches 32009347 # Number of branches executed +system.cpu.iew.exec_stores 87218543 # Number of stores executed +system.cpu.iew.exec_rate 2.702456 # Inst execution rate +system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183055174 # num instructions producing a value +system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687199 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503162 # average fanout of values written-back +system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35562440 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1591916 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131524549 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.653992 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34720675 26.40% 26.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28457654 21.64% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13339371 10.14% 58.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11431101 8.69% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13773309 10.47% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7413510 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3874860 2.95% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3887136 2.96% 88.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14626933 11.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131524549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,238 +600,238 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14626933 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501522594 # The number of ROB reads -system.cpu.rob.rob_writes 774405807 # The number of ROB writes -system.cpu.timesIdled 6645 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 348068 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501462134 # The number of ROB reads +system.cpu.rob.rob_writes 774278104 # The number of ROB writes +system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501835 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501835 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992688 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992688 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769988396 # number of integer regfile reads -system.cpu.int_regfile_writes 233047297 # number of integer regfile writes -system.cpu.fp_regfile_reads 188164665 # number of floating regfile reads -system.cpu.fp_regfile_writes 132532739 # number of floating regfile writes -system.cpu.misc_regfile_reads 566941334 # number of misc regfile reads +system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads +system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads +system.cpu.int_regfile_writes 233026497 # number of integer regfile writes +system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads +system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes +system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20093174 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1036 # Transaction distribution +system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2842 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1376320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1376320 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11791500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24322738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7408962 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13968 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.251388 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37591948 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15858 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2370.535250 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13947 # number of replacements +system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75234453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75234453 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37591948 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37591948 # number of overall hits -system.cpu.icache.overall_hits::total 37591948 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17349 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17349 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17349 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17349 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17349 # number of overall misses -system.cpu.icache.overall_misses::total 17349 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 451171984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 451171984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 451171984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 451171984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 451171984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 451171984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37609297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37609297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37609297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37609297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37609297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37609297 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses +system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits +system.cpu.icache.overall_hits::total 37578823 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses +system.cpu.icache.overall_misses::total 17320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26005.647818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26005.647818 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26005.647818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26005.647818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26005.647818 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2002 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 87.043478 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1490 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1490 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1490 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1490 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1490 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15859 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15859 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15859 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15859 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15859 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359132259 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359132259 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359132259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359132259 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359132259 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359132259 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000422 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22645.328142 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22645.328142 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22645.328142 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22645.328142 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1482 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1482 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1482 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1482 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1482 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1482 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15838 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15838 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15838 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15838 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15838 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15838 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359653509 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359653509 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359653509 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359653509 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359653509 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359653509 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22708.265501 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22708.265501 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3941.799565 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13198 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5394 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.446793 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3937.367139 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13183 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5383 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.449006 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 379.005926 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2786.464306 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 776.329333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1235 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 378.211483 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2780.743240 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 778.412416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.023755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.120159 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5383 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1236 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4014 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180292 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180292 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1036 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1036 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4007 # Occupied blocks per task id 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(read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 318 # number of overall hits -system.cpu.l2cache.overall_hits::total 13121 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3052 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1471 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4523 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 12790 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13106 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12790 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits +system.cpu.l2cache.overall_hits::total 13106 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3044 # number of ReadReq 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ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58489.734513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58489.734513 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58016.447368 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59708.529135 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.495066 # average overall mshr miss latency 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count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 684 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342019754 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342019754 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031381 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170960424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170960424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170960424 # number of overall hits -system.cpu.dcache.overall_hits::total 170960424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3956 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3956 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21284 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21284 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits +system.cpu.dcache.overall_hits::total 170951801 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25240 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25240 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25240 # number of overall misses -system.cpu.dcache.overall_misses::total 25240 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 235586955 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 235586955 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1260992389 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1260992389 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses +system.cpu.dcache.overall_misses::total 25020 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1496579344 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1496579344 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1496579344 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1496579344 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88932999 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88932999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170985664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170985664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170985664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170985664 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000259 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59551.808645 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59551.808645 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59246.024666 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59246.024666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59293.951823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59293.951823 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59293.951823 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28312 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 411 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.885645 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks -system.cpu.dcache.writebacks::total 1036 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18442 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18442 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks +system.cpu.dcache.writebacks::total 1035 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20624 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20624 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20624 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20624 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2842 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 114384040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 114384040 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203208498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 203208498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317592538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 317592538 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317592538 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317592538 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -983,14 +1028,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64478.038331 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64478.038331 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71501.934553 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71501.934553 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68802.542894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68802.542894 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 098c10a60..d33135638 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index b3ebb4d02..563fc0af8 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:52:31 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:27:26 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x56d96c0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 02fd51087..b6b6bed83 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344043000 # Number of ticks simulated final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1679583 # Simulator instruction rate (inst/s) -host_op_rate 2147266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1306228104 # Simulator tick rate (ticks/s) -host_mem_usage 246496 # Number of bytes of host memory used -host_seconds 162.56 # Real time elapsed on the host +host_inst_rate 1312619 # Simulator instruction rate (inst/s) +host_op_rate 1678120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1020836459 # Simulator tick rate (ticks/s) +host_mem_usage 266392 # Number of bytes of host memory used +host_seconds 208.01 # Real time elapsed on the host sim_insts 273037663 # Number of instructions simulated sim_ops 349065399 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 10715621794 # Th system.membus.data_through_bus 2275398455 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 12448615 # nu system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls system.cpu.num_int_insts 279584918 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read +system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index aa5380744..3089e084a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 32b55c30c..9d7fb2434 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:52:55 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:29:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4c37d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 5bfa9270c..7d607329f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu sim_ticks 525834342000 # Number of ticks simulated final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870200 # Simulator instruction rate (inst/s) -host_op_rate 1112519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1677723175 # Simulator tick rate (ticks/s) -host_mem_usage 255236 # Number of bytes of host memory used -host_seconds 313.42 # Real time elapsed on the host +host_inst_rate 719381 # Simulator instruction rate (inst/s) +host_op_rate 919702 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1386947293 # Simulator tick rate (ticks/s) +host_mem_usage 276148 # Number of bytes of host memory used +host_seconds 379.13 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 12448615 # nu system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read +system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 116b954da..1aaeea9d1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index f17e243b1..542867b6f 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:55:24 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:31:04 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x4c3a340 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index f4aa63ff2..b6f8c26dc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.629535 # Nu sim_ticks 629535413500 # Number of ticks simulated final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111054 # Simulator instruction rate (inst/s) -host_op_rate 151240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50501117 # Simulator tick rate (ticks/s) -host_mem_usage 257896 # Number of bytes of host memory used -host_seconds 12465.77 # Real time elapsed on the host +host_inst_rate 106173 # Simulator instruction rate (inst/s) +host_op_rate 144593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48281629 # Simulator tick rate (ticks/s) +host_mem_usage 278772 # Number of bytes of host memory used +host_seconds 13038.82 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -264,14 +264,14 @@ system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # By system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation -system.physmem.totQLat 3804882250 # Total ticks spent queuing -system.physmem.totMemAccLat 15248096000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3804806750 # Total ticks spent queuing +system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks -system.physmem.avgQLat 8012.81 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32111.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s @@ -303,20 +303,41 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 34627840 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215450500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 438247561 # Number of BP lookups -system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted +system.cpu.branchPred.lookups 438247722 # Number of BP lookups +system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 248480001 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229339299 # Number of BTB hits +system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.296884 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -338,6 +359,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -363,94 +405,94 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1259070828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 354141008 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2279760487 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438247561 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282254970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601258072 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157188088 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 134732646 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658370 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216659156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 615445856 50.58% 50.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44699242 3.67% 76.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216659156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.810669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405371714 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106745319 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 560686974 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17351070 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126504079 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44827999 # Number of times decode resolved a branch +system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3022923361 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126504079 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441422889 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38085775 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 457741 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539750608 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70438064 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2941756877 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54385480 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2930214829 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14001897517 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12151175707 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 937074739 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179295872 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792666421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2435152062 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894813451 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2308126927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380682430 31.29% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183043156 15.04% 46.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204120943 16.78% 63.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169552819 13.94% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132904789 10.92% 87.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92975981 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12393834 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216659156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available @@ -486,7 +528,7 @@ system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104246319 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued @@ -519,17 +561,17 @@ system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Ty system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2435152062 # Type of FU issued -system.cpu.iq.rate 1.934087 # Inst issue rate +system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued +system.cpu.iq.rate 1.934086 # Inst issue rate system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6065395375 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3604907621 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2250139997 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2459503230 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -540,13 +582,13 @@ system.cpu.iew.lsq.thread0.squashedStores 208692629 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 259 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126504079 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792706843 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1386728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions @@ -556,43 +598,43 @@ system.cpu.iew.memOrderViolationEvents 1430281 # Nu system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2359934614 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794158657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75217448 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12446 # number of nop insts executed -system.cpu.iew.exec_refs 1217435243 # number of memory reference insts executed +system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed system.cpu.iew.exec_branches 319532182 # Number of branches executed system.cpu.iew.exec_stores 423276586 # Number of stores executed system.cpu.iew.exec_rate 1.874346 # Inst execution rate -system.cpu.iew.wb_sent 2332318779 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2306573100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1349155886 # num instructions producing a value -system.cpu.iew.wb_consumers 2527422056 # num instructions consuming a value +system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349155649 # num instructions producing a value +system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831965 # insts written-back per cycle +system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907370613 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449868803 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288583121 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106429 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70222159 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473802 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848603 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10986529 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090155077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -605,10 +647,10 @@ system.cpu.commit.int_insts 1653698867 # Nu system.cpu.commit.function_calls 41577833 # Number of function calls committed. system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791959297 # The number of ROB reads -system.cpu.rob.rob_writes 5711929091 # The number of ROB writes +system.cpu.rob.rob_reads 3791959363 # The number of ROB reads +system.cpu.rob.rob_writes 5711929117 # The number of ROB writes system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42411672 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated @@ -616,11 +658,11 @@ system.cpu.cpi 0.909490 # CP system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11767673862 # number of integer regfile reads -system.cpu.int_regfile_writes 2220512687 # number of integer regfile writes +system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads +system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364568347 # number of misc regfile reads +system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution @@ -743,7 +785,7 @@ system.cpu.l2cache.tags.total_refs 1110777 # To system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy @@ -788,16 +830,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2426 # system.cpu.l2cache.overall_misses::cpu.data 472563 # number of overall misses system.cpu.l2cache.overall_misses::total 474989 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176218750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746587000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30922805750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30746506500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30922725250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4757394750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4757394750 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 176218750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35503981750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35680200500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35503901250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35680120000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 176218750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35503981750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35680200500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35503901250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35680120000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 25018 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1464549 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1489567 # number of ReadReq accesses(hits+misses) @@ -827,16 +869,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096970 system.cpu.l2cache.overall_miss_rate::cpu.data 0.307445 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.304074 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.965460 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75622.152810 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.684692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75117.951153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,18 +912,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 system.cpu.l2cache.overall_mshr_misses::cpu.data 472539 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 474963 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686513500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832151250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25686438000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25832075750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 42624262 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 42624262 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924978750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924978750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145637750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611492250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29757130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29611416750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29757054500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145637750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611492250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29757130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29611416750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29757054500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.096890 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277534 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274500 # mshr miss rate for ReadReq accesses @@ -896,24 +938,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096890 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307429 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.304057 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.362666 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.903220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.652547 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.469693 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1532970 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 971409274 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 631.989306 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy @@ -925,20 +967,20 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 971375738 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 971375738 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 971375738 # number of overall hits -system.cpu.dcache.overall_hits::total 971375738 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits +system.cpu.dcache.overall_hits::total 971375795 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses @@ -949,28 +991,28 @@ system.cpu.dcache.demand_misses::cpu.data 2796744 # n system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses system.cpu.dcache.overall_misses::total 2796744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415300557 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80415300557 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619884416 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58619884416 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 139035184973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 139035184973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 139035184973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 139035184973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697236804 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697236804 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974172482 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974172482 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974172482 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974172482 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses @@ -981,16 +1023,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.774874 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.774874 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.845892 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.845892 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49713.232592 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.232592 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49713.232592 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked @@ -1019,14 +1061,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792232024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792232024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785726512 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47785726512 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785726512 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47785726512 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -1035,14 +1077,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.669766 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.669766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.877065 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.877065 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 879581bbb..1d7b4f375 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 6d065fef8..c4e0dd481 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 22:58:19 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:35:34 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x49db380 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 982d92f29..059b5a3b1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613126000 # Number of ticks simulated final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1817390 # Simulator instruction rate (inst/s) -host_op_rate 2475033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241382789 # Simulator tick rate (ticks/s) -host_mem_usage 247108 # Number of bytes of host memory used -host_seconds 761.74 # Real time elapsed on the host +host_inst_rate 1603190 # Simulator instruction rate (inst/s) +host_op_rate 2183323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1095071931 # Simulator tick rate (ticks/s) +host_mem_usage 266996 # Number of bytes of host memory used +host_seconds 863.52 # Real time elapsed on the host sim_insts 1384381606 # Number of instructions simulated sim_ops 1885336358 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9675679644 # Th system.membus.data_through_bus 9149449674 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 80372855 # nu system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read +system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 0bdfc6610..11c9b066a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 973b4e1bf..f8adf17ee 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:11:12 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:50:08 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x56b7d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index ecd5fda89..f64dc7529 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu sim_ticks 2326118592000 # Number of ticks simulated final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 968971 # Simulator instruction rate (inst/s) -host_op_rate 1314478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1631393565 # Simulator tick rate (ticks/s) -host_mem_usage 255816 # Number of bytes of host memory used -host_seconds 1425.85 # Real time elapsed on the host +host_inst_rate 908275 # Simulator instruction rate (inst/s) +host_op_rate 1232140 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1529204664 # Simulator tick rate (ticks/s) +host_mem_usage 276728 # Number of bytes of host memory used +host_seconds 1521.13 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 80372855 # nu system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read +system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 3a6f7de14..20429e4aa 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index 1a4f96712..78695e4f1 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1 +1,2 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 51d96dffd..0fe32cbd7 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:17:11 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:54:40 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5a6c340 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26810051000 because target called exit() +Exiting @ tick 26790388000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 044953ad0..9978094b9 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026810 # Number of seconds simulated -sim_ticks 26810051000 # Number of ticks simulated -final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026790 # Number of seconds simulated +sim_ticks 26790388000 # Number of ticks simulated +final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140336 # Simulator instruction rate (inst/s) -host_op_rate 199155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53060871 # Simulator tick rate (ticks/s) -host_mem_usage 257660 # Number of bytes of host memory used -host_seconds 505.27 # Real time elapsed on the host +host_inst_rate 134448 # Simulator instruction rate (inst/s) +host_op_rate 190799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50797444 # Simulator tick rate (ticks/s) +host_mem_usage 278572 # Number of bytes of host memory used +host_seconds 527.40 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 299136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 299136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128787 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11157607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296278138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307435745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11157607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11157607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200395292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200395292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200395292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11157607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296278138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 507831037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128788 # Number of read requests accepted -system.physmem.writeReqs 83947 # Number of write requests accepted -system.physmem.readBursts 128788 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83947 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8242304 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory +system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128754 # Number of read requests accepted +system.physmem.writeReqs 83937 # Number of write requests accepted +system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8242432 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372608 # Total written bytes from the system interface side +system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8141 # Per bank write bursts -system.physmem.perBankRdBursts::1 8391 # Per bank write bursts -system.physmem.perBankRdBursts::2 8249 # Per bank write bursts -system.physmem.perBankRdBursts::3 8162 # Per bank write bursts -system.physmem.perBankRdBursts::4 8307 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts +system.physmem.perBankRdBursts::0 8131 # Per bank write bursts +system.physmem.perBankRdBursts::1 8390 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::3 8163 # Per bank write bursts +system.physmem.perBankRdBursts::4 8302 # Per bank write bursts +system.physmem.perBankRdBursts::5 8446 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7966 # Per bank write bursts +system.physmem.perBankRdBursts::7 7962 # Per bank write bursts system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7616 # Per bank write bursts -system.physmem.perBankRdBursts::10 7784 # Per bank write bursts -system.physmem.perBankRdBursts::11 7815 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7887 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8012 # Per bank write bursts -system.physmem.perBankWrBursts::0 5178 # Per bank write bursts +system.physmem.perBankRdBursts::9 7613 # Per bank write bursts +system.physmem.perBankRdBursts::10 7786 # Per bank write bursts +system.physmem.perBankRdBursts::11 7812 # Per bank write bursts +system.physmem.perBankRdBursts::12 7879 # Per bank write bursts +system.physmem.perBankRdBursts::13 7885 # Per bank write bursts +system.physmem.perBankRdBursts::14 7978 # Per bank write bursts +system.physmem.perBankRdBursts::15 8010 # Per bank write bursts +system.physmem.perBankWrBursts::0 5179 # Per bank write bursts system.physmem.perBankWrBursts::1 5375 # Per bank write bursts -system.physmem.perBankWrBursts::2 5292 # Per bank write bursts +system.physmem.perBankWrBursts::2 5289 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5267 # Per bank write bursts +system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5206 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5028 # Per bank write bursts -system.physmem.perBankWrBursts::9 5090 # Per bank write bursts -system.physmem.perBankWrBursts::10 5248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5142 # Per bank write bursts +system.physmem.perBankWrBursts::6 5207 # Per bank write bursts +system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::9 5089 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::11 5144 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5222 # Per bank write bursts +system.physmem.perBankWrBursts::15 5226 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26810034000 # Total gap between requests +system.physmem.totGap 26790282500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128788 # Read request sizes (log2) +system.physmem.readPktSize::6 128754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83947 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 72914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83937 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,31 +129,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -161,190 +161,208 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37958 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 358.604352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.758574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 692.410978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15190 40.02% 40.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5700 15.02% 55.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3416 9.00% 64.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2313 6.09% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1704 4.49% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1539 4.05% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1108 2.92% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 903 2.38% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 681 1.79% 85.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 548 1.44% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 355 0.94% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 578 1.52% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 299 0.79% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 386 1.02% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 183 0.48% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 223 0.59% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 117 0.31% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 252 0.66% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 118 0.31% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 257 0.68% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 108 0.28% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 421 1.11% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 88 0.23% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 246 0.65% 96.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 122 0.32% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 43 0.11% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 88 0.23% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 65 0.17% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 27 0.07% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 45 0.12% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 16 0.04% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 15 0.04% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 29 0.08% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 15 0.04% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 34 0.09% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 13 0.03% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 17 0.04% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 7 0.02% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 19 0.05% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 17 0.04% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.03% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 27 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 7 0.02% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 14 0.04% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.03% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 15 0.04% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.02% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 11 0.03% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 10 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 13 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 8 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 13 0.03% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 9 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 8 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 7 0.02% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 6 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 9 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 7 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 7 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 4 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 3 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 5 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 35 0.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37958 # Bytes accessed per row activation -system.physmem.totQLat 3020745250 # Total ticks spent queuing -system.physmem.totMemAccLat 4967419000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643930000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1302743750 # Total ticks spent accessing banks -system.physmem.avgQLat 23455.54 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10115.57 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation +system.physmem.totQLat 3022726750 # Total ticks spent queuing +system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks +system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38571.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.73 # Average write queue length when enqueuing -system.physmem.readRowHits 117878 # Number of row buffer hits during reads -system.physmem.writeRowHits 56878 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.75 # Row buffer hit rate for writes -system.physmem.avgGap 126025.50 # Average gap between requests -system.physmem.pageHitRate 82.15 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 507831037 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26531 # Transaction distribution -system.membus.trans_dist::ReadResp 26530 # Transaction distribution -system.membus.trans_dist::Writeback 83947 # Transaction distribution +system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing +system.physmem.readRowHits 117872 # Number of row buffer hits during reads +system.physmem.writeRowHits 56933 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes +system.physmem.avgGap 125958.70 # Average gap between requests +system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 508101040 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26500 # Transaction distribution +system.membus.trans_dist::ReadResp 26500 # Transaction distribution +system.membus.trans_dist::Writeback 83937 # Transaction distribution system.membus.trans_dist::UpgradeReq 308 # Transaction distribution system.membus.trans_dist::UpgradeResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 102257 # Transaction distribution -system.membus.trans_dist::ReadExResp 102257 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342138 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13614976 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13614976 # Total data (bytes) +system.membus.trans_dist::ReadExReq 102254 # Transaction distribution +system.membus.trans_dist::ReadExResp 102254 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13612224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934752500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16646392 # Number of BP lookups -system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10818826 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7781096 # Number of BTB hits +system.cpu.branchPred.lookups 16615535 # Number of BP lookups +system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.921815 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825486 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113411 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -366,6 +384,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -388,239 +427,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53620103 # number of cpu cycles simulated +system.cpu.numCycles 53580777 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12555863 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85327612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16646392 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9606582 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21220606 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2386309 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10655499 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 479 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11697004 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 183631 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46184612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.586702 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24984951 54.10% 54.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138585 4.63% 58.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1966197 4.26% 62.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046003 4.43% 67.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1469884 3.18% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1382868 2.99% 73.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958032 2.07% 75.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1189943 2.58% 78.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10048149 21.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46184612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310451 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.591336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14642918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9005955 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19517473 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1369283 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1648983 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3334820 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105179 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116999070 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363013 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1648983 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16350179 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2575616 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1030832 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19130431 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5448571 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115098604 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17023 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4589680 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115425064 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 530260724 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476967295 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2691 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16292392 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12970121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29626660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22464166 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3855353 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4357218 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111639066 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36000 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107318490 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 273494 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10897204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26020912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46184612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.323685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.992080 # Number of insts issued each cycle +system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10954733 23.72% 23.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8081116 17.50% 41.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7387326 16.00% 57.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7126917 15.43% 72.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408207 11.71% 84.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3931545 8.51% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1847862 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 871002 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 575904 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46184612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112087 4.51% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 3 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1355242 54.58% 59.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1015813 40.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56685703 52.82% 52.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91410 0.09% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 203 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28899327 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21641840 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107318490 # Type of FU issued -system.cpu.iq.rate 2.001460 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2483145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263577666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122600736 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105627540 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 565 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 906 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109801353 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2178214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued +system.cpu.iq.rate 2.001511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2319552 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6675 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1908428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 694 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1648983 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1092293 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45577 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111684840 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295051 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29626660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22464166 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20080 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6356 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5380 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 395595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 182079 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 577674 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106281813 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28597262 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1036677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9774 # number of nop insts executed -system.cpu.iew.exec_refs 49953963 # number of memory reference insts executed -system.cpu.iew.exec_branches 14606559 # Number of branches executed -system.cpu.iew.exec_stores 21356701 # Number of stores executed -system.cpu.iew.exec_rate 1.982126 # Inst execution rate -system.cpu.iew.wb_sent 105847179 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105627710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53336530 # num instructions producing a value -system.cpu.iew.wb_consumers 104015656 # num instructions consuming a value +system.cpu.iew.exec_nop 9806 # number of nop insts executed +system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599283 # Number of branches executed +system.cpu.iew.exec_stores 21341796 # Number of stores executed +system.cpu.iew.exec_rate 1.982275 # Inst execution rate +system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53316718 # num instructions producing a value +system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.969927 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512774 # average fanout of values written-back +system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11053294 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 504169 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44535629 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.259594 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.766011 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15484235 34.77% 34.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11649742 26.16% 60.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3457573 7.76% 68.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2865921 6.44% 75.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1843682 4.14% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1946516 4.37% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 688008 1.54% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565195 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6034757 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44535629 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -631,243 +670,243 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6034757 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150161295 # The number of ROB reads -system.cpu.rob.rob_writes 225029668 # The number of ROB writes -system.cpu.timesIdled 76463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7435491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150021199 # The number of ROB reads +system.cpu.rob.rob_writes 224747411 # The number of ROB writes +system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.756197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.756197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322408 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322408 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511842322 # number of integer regfile reads -system.cpu.int_regfile_writes 103400028 # number of integer regfile writes -system.cpu.fp_regfile_reads 836 # number of floating regfile reads -system.cpu.fp_regfile_writes 732 # number of floating regfile writes -system.cpu.misc_regfile_reads 49193821 # number of misc regfile reads +system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads +system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511545132 # number of integer regfile reads +system.cpu.int_regfile_writes 103340839 # number of integer regfile writes +system.cpu.fp_regfile_reads 806 # number of floating regfile reads +system.cpu.fp_regfile_writes 694 # number of floating regfile writes +system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 770392865 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 86565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 86563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107049 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61854 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 516494 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18659456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20623232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20623232 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 31040 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290637496 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47495730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260347495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 28815 # number of replacements -system.cpu.icache.tags.tagsinuse 1808.840382 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11662045 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 30854 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 377.975141 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29638 # number of replacements +system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2039 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1260 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 677 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23425177 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23425177 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11662047 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11662047 # number of overall hits -system.cpu.icache.overall_hits::total 11662047 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34957 # number of overall misses -system.cpu.icache.overall_misses::total 34957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 813284976 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 813284976 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 813284976 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 813284976 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 813284976 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 813284976 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11697004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11697004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11697004 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11697004 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11697004 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11697004 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23265.296679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23265.296679 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23265.296679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23265.296679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23265.296679 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2987 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits +system.cpu.icache.overall_hits::total 11640118 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses +system.cpu.icache.overall_misses::total 35738 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 129.869565 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3787 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3787 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3787 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3787 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3787 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3787 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31170 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31170 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31170 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31170 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31170 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31170 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 659799769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 659799769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 659799769 # number of demand (read+write) MSHR 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+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83482.568519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83482.568519 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -876,202 +915,202 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks -system.cpu.l2cache.writebacks::total 83947 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 83937 # number of writebacks +system.cpu.l2cache.writebacks::total 83937 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4674 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26531 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4646 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21854 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26500 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4674 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124114 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128788 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4674 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124114 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128788 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 308414000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1593918750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1902332750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3088307 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3088307 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7239546250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7239546250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 308414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8833465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9141879000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 308414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8833465000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9141879000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394566 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308213 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.959502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.959502 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955235 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955235 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.666850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152322 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764042 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.666850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65985.023534 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72924.863888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71702.263390 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.970779 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.970779 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70797.561536 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70797.561536 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65985.023534 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71172.188472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70983.934839 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102254 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102254 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124108 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4646 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124108 # number of overall MSHR misses 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9143383750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311360750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8832023000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9143383750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses 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miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency 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Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993369 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1767 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2268 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92301717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92301717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266759 # number of WriteReq hits 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of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44330005 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44330005 # number of overall hits -system.cpu.dcache.overall_hits::total 44330005 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124539 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124539 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583142 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707681 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707681 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707681 # number of overall misses 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-system.cpu.dcache.overall_miss_latency::total 132215195206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26187785 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26187785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315381 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315381 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315381 # number of overall hits +system.cpu.dcache.overall_hits::total 44315381 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708462 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708462 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708462 # number of overall misses +system.cpu.dcache.overall_misses::total 1708462 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205484954 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5205484954 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127036653749 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 856750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 856750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16032 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16032 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46037686 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46037686 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46037686 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46037686 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004756 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004756 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079756 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079756 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002682 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002682 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037093 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037093 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037093 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037093 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41885.262568 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41885.262568 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80219.491676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80219.491676 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 24104.651163 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 24104.651163 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77423.825179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77423.825179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77423.825179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3791 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1217 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 149 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.442953 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 93.615385 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129111 # number of writebacks -system.cpu.dcache.writebacks::total 129111 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475806 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475806 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55429 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55429 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107336 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107336 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162765 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162765 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162765 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162765 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263965562 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263965562 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8681187684 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8681187684 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945153246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945153246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945153246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945153246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks +system.cpu.dcache.writebacks::total 129182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40844.423713 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40844.423713 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80878.621190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80878.621190 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.127921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.127921 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index b4899830a..ba6e5f41a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index fd88c13a1..b32e4875d 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:25:48 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:03:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x49b6380 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 53932157000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 130b6bb56..d5e255546 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1940189 # Simulator instruction rate (inst/s) -host_op_rate 2753308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1475586020 # Simulator tick rate (ticks/s) -host_mem_usage 245844 # Number of bytes of host memory used -host_seconds 36.55 # Real time elapsed on the host +host_inst_rate 1720542 # Simulator instruction rate (inst/s) +host_op_rate 2441608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1308536096 # Simulator tick rate (ticks/s) +host_mem_usage 265732 # Number of bytes of host memory used +host_seconds 41.22 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9230371187 # Th system.membus.data_through_bus 497813828 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 3311620 # nu system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read +system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 8802837e9..de369d8f4 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 89bb0e0aa..4bb28ef2b 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:26:35 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:04:30 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5604d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Exiting @ tick 132689045000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 7d6b41b45..6c81ce1de 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019812 # Simulator instruction rate (inst/s) -host_op_rate 1446120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1922848599 # Simulator tick rate (ticks/s) -host_mem_usage 254584 # Number of bytes of host memory used -host_seconds 69.01 # Real time elapsed on the host +host_inst_rate 945773 # Simulator instruction rate (inst/s) +host_op_rate 1341131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783248877 # Simulator tick rate (ticks/s) +host_mem_usage 275500 # Number of bytes of host memory used +host_seconds 74.41 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.7 # La system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 3311620 # nu system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read +system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index c32ff375e..56ff7911f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index aa09d1777..c3788cdfe 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:27:54 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:05:55 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5017340 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -24,4 +25,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 533797009000 because target called exit() +Exiting @ tick 533761922000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5e5db11e7..8c6f8359f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533797 # Number of seconds simulated -sim_ticks 533797009000 # Number of ticks simulated -final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.533762 # Number of seconds simulated +sim_ticks 533761922000 # Number of ticks simulated +final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163502 # Simulator instruction rate (inst/s) -host_op_rate 182399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56505895 # Simulator tick rate (ticks/s) -host_mem_usage 249880 # Number of bytes of host memory used -host_seconds 9446.75 # Real time elapsed on the host +host_inst_rate 155948 # Simulator instruction rate (inst/s) +host_op_rate 173972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53891847 # Simulator tick rate (ticks/s) +host_mem_usage 269768 # Number of bytes of host memory used +host_seconds 9904.32 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory -system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory -system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246734 # Number of read requests accepted -system.physmem.writeReqs 1100498 # Number of write requests accepted -system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue -system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory +system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory +system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246694 # Number of read requests accepted +system.physmem.writeReqs 1100579 # Number of write requests accepted +system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue +system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139750 # Per bank write bursts -system.physmem.perBankRdBursts::1 136273 # Per bank write bursts -system.physmem.perBankRdBursts::2 133708 # Per bank write bursts -system.physmem.perBankRdBursts::3 136246 # Per bank write bursts -system.physmem.perBankRdBursts::4 134906 # Per bank write bursts -system.physmem.perBankRdBursts::5 135253 # Per bank write bursts -system.physmem.perBankRdBursts::6 136175 # Per bank write bursts -system.physmem.perBankRdBursts::7 136295 # Per bank write bursts -system.physmem.perBankRdBursts::8 143732 # Per bank write bursts -system.physmem.perBankRdBursts::9 146555 # Per bank write bursts -system.physmem.perBankRdBursts::10 144302 # Per bank write bursts -system.physmem.perBankRdBursts::11 146237 # Per bank write bursts -system.physmem.perBankRdBursts::12 145788 # Per bank write bursts -system.physmem.perBankRdBursts::13 146277 # Per bank write bursts -system.physmem.perBankRdBursts::14 142119 # Per bank write bursts -system.physmem.perBankRdBursts::15 142542 # Per bank write bursts -system.physmem.perBankWrBursts::0 69128 # Per bank write bursts -system.physmem.perBankWrBursts::1 67452 # Per bank write bursts -system.physmem.perBankWrBursts::2 65650 # Per bank write bursts -system.physmem.perBankWrBursts::3 66298 # Per bank write bursts -system.physmem.perBankWrBursts::4 66182 # Per bank write bursts -system.physmem.perBankWrBursts::5 66379 # Per bank write bursts -system.physmem.perBankWrBursts::6 67939 # Per bank write bursts -system.physmem.perBankWrBursts::7 68869 # Per bank write bursts -system.physmem.perBankWrBursts::8 70353 # Per bank write bursts -system.physmem.perBankWrBursts::9 70986 # Per bank write bursts -system.physmem.perBankWrBursts::10 70505 # Per bank write bursts -system.physmem.perBankWrBursts::11 70955 # Per bank write bursts -system.physmem.perBankWrBursts::12 70250 # Per bank write bursts -system.physmem.perBankWrBursts::13 70819 # Per bank write bursts -system.physmem.perBankWrBursts::14 69624 # Per bank write bursts -system.physmem.perBankWrBursts::15 69092 # Per bank write bursts +system.physmem.perBankRdBursts::0 139629 # Per bank write bursts +system.physmem.perBankRdBursts::1 136292 # Per bank write bursts +system.physmem.perBankRdBursts::2 133828 # Per bank write bursts +system.physmem.perBankRdBursts::3 136435 # Per bank write bursts +system.physmem.perBankRdBursts::4 134766 # Per bank write bursts +system.physmem.perBankRdBursts::5 135151 # Per bank write bursts +system.physmem.perBankRdBursts::6 136244 # Per bank write bursts +system.physmem.perBankRdBursts::7 136309 # Per bank write bursts +system.physmem.perBankRdBursts::8 143829 # Per bank write bursts +system.physmem.perBankRdBursts::9 146501 # Per bank write bursts +system.physmem.perBankRdBursts::10 144298 # Per bank write bursts +system.physmem.perBankRdBursts::11 146295 # Per bank write bursts +system.physmem.perBankRdBursts::12 145712 # Per bank write bursts +system.physmem.perBankRdBursts::13 146106 # Per bank write bursts +system.physmem.perBankRdBursts::14 142241 # Per bank write bursts +system.physmem.perBankRdBursts::15 142471 # Per bank write bursts +system.physmem.perBankWrBursts::0 69077 # Per bank write bursts +system.physmem.perBankWrBursts::1 67426 # Per bank write bursts +system.physmem.perBankWrBursts::2 65726 # Per bank write bursts +system.physmem.perBankWrBursts::3 66343 # Per bank write bursts +system.physmem.perBankWrBursts::4 66130 # Per bank write bursts +system.physmem.perBankWrBursts::5 66357 # Per bank write bursts +system.physmem.perBankWrBursts::6 67984 # Per bank write bursts +system.physmem.perBankWrBursts::7 68878 # Per bank write bursts +system.physmem.perBankWrBursts::8 70373 # Per bank write bursts +system.physmem.perBankWrBursts::9 70997 # Per bank write bursts +system.physmem.perBankWrBursts::10 70493 # Per bank write bursts +system.physmem.perBankWrBursts::11 70981 # Per bank write bursts +system.physmem.perBankWrBursts::12 70269 # Per bank write bursts +system.physmem.perBankWrBursts::13 70812 # Per bank write bursts +system.physmem.perBankWrBursts::14 69646 # Per bank write bursts +system.physmem.perBankWrBursts::15 69069 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 533796944500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 533761847000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246734 # Read request sizes (log2) +system.physmem.readPktSize::6 2246694 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100498 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100579 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,216 +129,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see 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0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation -system.physmem.totQLat 32821468000 # Total ticks spent queuing -system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers -system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks -system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation +system.physmem.totQLat 32815970750 # Total ticks spent queuing +system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers +system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks +system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing -system.physmem.readRowHits 932509 # Number of row buffer hits during reads -system.physmem.writeRowHits 336457 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes -system.physmem.avgGap 159474.14 # Average gap between requests -system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401318817 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420235 # Transaction distribution -system.membus.trans_dist::ReadResp 1420234 # Transaction distribution -system.membus.trans_dist::Writeback 1100498 # Transaction distribution -system.membus.trans_dist::ReadExReq 826499 # Transaction distribution -system.membus.trans_dist::ReadExResp 826499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214222784 # Total data (bytes) +system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing +system.physmem.readRowHits 932061 # Number of row buffer hits during reads +system.physmem.writeRowHits 336288 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes +system.physmem.avgGap 159461.70 # Average gap between requests +system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 401350114 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420099 # Transaction distribution +system.membus.trans_dist::ReadResp 1420098 # Transaction distribution +system.membus.trans_dist::Writeback 1100579 # Transaction distribution +system.membus.trans_dist::ReadExReq 826595 # Transaction distribution +system.membus.trans_dist::ReadExResp 826595 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214225408 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 303451211 # Number of BP lookups -system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits +system.cpu.branchPred.lookups 303426723 # Number of BP lookups +system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,6 +381,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -382,132 +424,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067594019 # number of cpu cycles simulated +system.cpu.numCycles 1067523845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 843 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 542 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -529,90 +571,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued -system.cpu.iq.rate 1.890996 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued +system.cpu.iq.rate 1.891055 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 92 # number of nop insts executed -system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed -system.cpu.iew.exec_branches 238324356 # Number of branches executed -system.cpu.iew.exec_stores 190177930 # Number of stores executed -system.cpu.iew.exec_rate 1.862201 # Inst execution rate -system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295422958 # num instructions producing a value -system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value +system.cpu.iew.exec_nop 143 # number of nop insts executed +system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed +system.cpu.iew.exec_branches 238318975 # Number of branches executed +system.cpu.iew.exec_stores 190166415 # Number of stores executed +system.cpu.iew.exec_rate 1.862270 # Inst execution rate +system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295394361 # num instructions producing a value +system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back +system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -623,97 +665,98 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995444799 # The number of ROB reads -system.cpu.rob.rob_writes 4475102834 # The number of ROB writes -system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2995284619 # The number of ROB reads +system.cpu.rob.rob_writes 4474886700 # The number of ROB writes +system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads -system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads -system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes -system.cpu.fp_regfile_reads 112 # number of floating regfile reads -system.cpu.fp_regfile_writes 111 # number of floating regfile writes -system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads +system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads +system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads +system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes +system.cpu.fp_regfile_reads 98 # number of floating regfile reads +system.cpu.fp_regfile_writes 94 # number of floating regfile writes +system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) +system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 20 # number of replacements -system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 19 # number of replacements +system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 754 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 726 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.368164 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579143830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579143830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits -system.cpu.icache.overall_hits::total 289570320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses -system.cpu.icache.overall_misses::total 1208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits +system.cpu.icache.overall_hits::total 289577640 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses +system.cpu.icache.overall_misses::total 1205 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -722,129 +765,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles 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(read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 173878798500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46285250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173832513250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 173878798500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184230 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436505 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436505 # mshr miss rate for ReadExReq accesses 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ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 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-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2397 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1056 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1355914350 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1355914350 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits -system.cpu.dcache.overall_hits::total 656019351 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits +system.cpu.dcache.overall_hits::total 656012474 # number of overall hits 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cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses) 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(read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks -system.cpu.dcache.writebacks::total 3780837 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks +system.cpu.dcache.writebacks::total 3782070 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 1a911e7c2..ad0230a84 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 922328096..e972d8df4 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:35:09 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:13:20 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x571a380 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index de1eec5b4..a0198a23d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2414882 # Simulator instruction rate (inst/s) -host_op_rate 2693979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346991470 # Simulator tick rate (ticks/s) -host_mem_usage 238968 # Number of bytes of host memory used -host_seconds 639.60 # Real time elapsed on the host +host_inst_rate 2200753 # Simulator instruction rate (inst/s) +host_op_rate 2455102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1227552560 # Simulator tick rate (ticks/s) +host_mem_usage 258852 # Number of bytes of host memory used +host_seconds 701.83 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9731209155 # Th system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 27330256 # nu system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read +system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 05924440e..a5a5a4799 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 684ae1ce5..4d71ca666 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:38:44 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:15:41 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5333d00 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 3ce47f2c9..b8a9db006 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1202285 # Simulator instruction rate (inst/s) -host_op_rate 1341761 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1868329144 # Simulator tick rate (ticks/s) -host_mem_usage 247832 # Number of bytes of host memory used -host_seconds 1279.86 # Real time elapsed on the host +host_inst_rate 1176543 # Simulator instruction rate (inst/s) +host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1828326739 # Simulator tick rate (ticks/s) +host_mem_usage 268744 # Number of bytes of host memory used +host_seconds 1307.87 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -53,6 +53,27 @@ system.membus.reqLayer0.utilization 0.5 # La system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -74,6 +95,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -107,7 +149,7 @@ system.cpu.num_func_calls 27330256 # nu system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read +system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_writes 16 # number of times the floating registers were written diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 69c7d8edb..03d137b4d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 6ec033969..ce396dba2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 23:45:59 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:25:13 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5949040 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -23,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 74219948500 because target called exit() +122 123 124 Exiting @ tick 74219931000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 3723ab1c1..a1592fc7b 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.074220 # Number of seconds simulated -sim_ticks 74219948500 # Number of ticks simulated -final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 74219931000 # Number of ticks simulated +final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133200 # Simulator instruction rate (inst/s) -host_op_rate 145842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57376166 # Simulator tick rate (ticks/s) -host_mem_usage 253176 # Number of bytes of host memory used -host_seconds 1293.57 # Real time elapsed on the host +host_inst_rate 128899 # Simulator instruction rate (inst/s) +host_op_rate 141133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55523526 # Simulator tick rate (ticks/s) +host_mem_usage 273064 # Number of bytes of host memory used +host_seconds 1336.73 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 131072 # Nu system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3794 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74219930000 # Total gap between requests +system.physmem.totGap 74219912500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -199,14 +199,14 @@ system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25203500 # Total ticks spent queuing -system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 25208000 # Total ticks spent queuing +system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s @@ -221,10 +221,10 @@ system.physmem.readRowHits 3077 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19562448.60 # Average gap between requests +system.physmem.avgGap 19562443.99 # Average gap between requests system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3270711 # Throughput (bytes/s) +system.membus.throughput 3270712 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2723 # Transaction distribution system.membus.trans_dist::ReadResp 2722 # Transaction distribution system.membus.trans_dist::ReadExReq 1071 # Transaction distribution @@ -235,20 +235,41 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94784274 # Number of BP lookups -system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits +system.cpu.branchPred.lookups 94784239 # Number of BP lookups +system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -270,6 +291,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -292,100 +334,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148439898 # number of cpu cycles simulated +system.cpu.numCycles 148439863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups +system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available @@ -405,21 +447,21 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued @@ -448,84 +490,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued -system.cpu.iq.rate 1.680523 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested +system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued +system.cpu.iq.rate 1.680522 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17196 # number of nop insts executed -system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed -system.cpu.iew.exec_branches 53426072 # Number of branches executed -system.cpu.iew.exec_stores 13648456 # Number of stores executed -system.cpu.iew.exec_rate 1.636760 # Inst execution rate -system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148474078 # num instructions producing a value -system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value +system.cpu.iew.exec_nop 17197 # number of nop insts executed +system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426054 # Number of branches executed +system.cpu.iew.exec_stores 13648437 # Number of stores executed +system.cpu.iew.exec_rate 1.636759 # Inst execution rate +system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148473973 # num instructions producing a value +system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle +system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,99 +578,99 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448787434 # The number of ROB reads -system.cpu.rob.rob_writes 679451113 # The number of ROB writes -system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448786959 # The number of ROB reads +system.cpu.rob.rob_writes 679450685 # The number of ROB writes +system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads -system.cpu.int_regfile_writes 384871783 # number of integer regfile writes +system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads +system.cpu.int_regfile_writes 384871537 # number of integer regfile writes system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes -system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads +system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution +system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2394 # number of replacements -system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2395 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73705913 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73705913 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits -system.cpu.icache.overall_hits::total 36845557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses -system.cpu.icache.overall_misses::total 5337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits +system.cpu.icache.overall_hits::total 36845513 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses +system.cpu.icache.overall_misses::total 5338 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles 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rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -643,40 +685,40 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 1211 system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4126 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4126 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4126 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1967.449595 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2163 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. 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0.016384 # Average percentage of cache occupancy @@ -688,21 +730,21 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51779 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51779 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 51787 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51787 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2074 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits 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-system.cpu.l2cache.overall_hits::total 2169 # number of overall hits +system.cpu.l2cache.overall_hits::total 2170 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2053 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 2738 # number of ReadReq misses @@ -714,52 +756,52 @@ system.cpu.l2cache.demand_misses::total 3809 # nu system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3809 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51387250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194615500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 143228250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123679500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266907750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143228250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123679500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266907750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4127 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 4900 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1079 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1079 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4127 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5978 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4126 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5979 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4127 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1852 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5978 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497576 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 5979 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.497456 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.558890 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.558776 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992586 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992586 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497576 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.497456 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.948164 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.637170 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.637063 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497456 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::total 0.637063 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70072.919401 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.343400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70432.517084 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70072.919401 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -788,47 +830,47 @@ system.cpu.l2cache.demand_mshr_misses::total 3794 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117257250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42300250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159557500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117257250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101142000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218399250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117257250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101142000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218399250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555714 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id @@ -838,52 +880,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93593418 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93593418 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits -system.cpu.dcache.overall_hits::total 46741275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits +system.cpu.dcache.overall_hits::total 46741245 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses -system.cpu.dcache.overall_misses::total 9625 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses +system.cpu.dcache.overall_misses::total 9623 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses @@ -894,16 +936,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -914,16 +956,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses @@ -932,14 +974,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1852 system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -948,14 +990,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 0b27d47af..8a9c45524 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 3a7a72087..cd4551b05 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:00:14 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:37:39 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5fbc6c0 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index c33d29231..0803f6f8f 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2018881 # Simulator instruction rate (inst/s) -host_op_rate 2210479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1208004529 # Simulator tick rate (ticks/s) -host_mem_usage 241364 # Number of bytes of host memory used -host_seconds 85.35 # Real time elapsed on the host +host_inst_rate 1878588 # Simulator instruction rate (inst/s) +host_op_rate 2056872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1124059947 # Simulator tick rate (ticks/s) +host_mem_usage 262308 # Number of bytes of host memory used +host_seconds 91.73 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 8876496088 # Th system.membus.data_through_bus 915226805 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 3545028 # nu system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read +system.cpu.num_int_register_reads 815315678 # number of times the integer registers were read system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index a68b7deda..c1d62d90a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 50f61b81e..aba76e9d8 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 23 2014 00:01:50 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 18:39:21 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5d0ed00 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index daccb0e4d..c455c2ee7 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1248624 # Simulator instruction rate (inst/s) -host_op_rate 1367377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1686259354 # Simulator tick rate (ticks/s) -host_mem_usage 250108 # Number of bytes of host memory used -host_seconds 137.63 # Real time elapsed on the host +host_inst_rate 1152638 # Simulator instruction rate (inst/s) +host_op_rate 1262262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1556630640 # Simulator tick rate (ticks/s) +host_mem_usage 271024 # Number of bytes of host memory used +host_seconds 149.09 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 0.0 # La system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 3545028 # nu system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read +system.cpu.num_int_register_reads 904571312 # number of times the integer registers were read system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 894acecbc..b5633ad46 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,13 +325,14 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fastmem=false @@ -264,6 +340,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -309,7 +386,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -321,10 +398,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -332,9 +434,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.icache] type=BaseCache @@ -359,7 +462,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -379,24 +482,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -404,9 +543,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1019,7 +1159,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 1e2520995..bf118f1e9 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:53 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:07:33 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6a97800 0x6a97800 + 0: system.cpu1.isa: ISA system set to: 0x6a97800 0x6a97800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 912096763500 because m5_exit instruction encountered +Exiting @ tick 912096767500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index eb8cedaf3..f0bd97b20 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,30 +1,30 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.912097 # Number of seconds simulated -sim_ticks 912096763500 # Number of ticks simulated -final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 912096767500 # Number of ticks simulated +final_tick 912096767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1859152 # Simulator instruction rate (inst/s) -host_op_rate 2393654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27516397451 # Simulator tick rate (ticks/s) -host_mem_usage 399324 # Number of bytes of host memory used -host_seconds 33.15 # Real time elapsed on the host -sim_insts 61625970 # Number of instructions simulated -sim_ops 79343340 # Number of ops (including micro ops) simulated +host_inst_rate 1391627 # Simulator instruction rate (inst/s) +host_op_rate 1791703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20594093924 # Simulator tick rate (ticks/s) +host_mem_usage 421260 # Number of bytes of host memory used +host_seconds 44.29 # Real time elapsed on the host +sim_insts 61634065 # Number of instructions simulated +sim_ops 79353129 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6235196 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364536 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638596 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory @@ -32,12 +32,12 @@ system.physmem.bytes_written::total 7222864 # Nu system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97499 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 52599 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082824 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory @@ -45,29 +45,29 @@ system.physmem.num_writes::total 822331 # Nu system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 550621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6836112 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 235278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3688793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 550621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 235278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 785899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4600143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::writebacks 4600143 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 550621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854751 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 235278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6988978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341477 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -86,24 +86,24 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64986577 # Throughput (bytes/s) -system.membus.data_through_bus 59274047 # Total data (bytes) +system.membus.throughput 64986682 # Throughput (bytes/s) +system.membus.data_through_bus 59274143 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 70658 # number of replacements -system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.tagsinuse 51560.149479 # Cycle average of tags in use system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 39278.694836 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.444990 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451280 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922652 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -124,8 +124,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 12549 # system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16906854 # Number of tag accesses -system.l2c.tags.data_accesses 16906854 # Number of data accesses +system.l2c.tags.tag_accesses 16908094 # Number of tag accesses +system.l2c.tags.data_accesses 16908094 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -172,9 +172,9 @@ system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses @@ -208,9 +208,9 @@ system.l2c.ReadReq_accesses::cpu1.data 174787 # nu system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) @@ -243,9 +243,9 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses @@ -285,33 +285,75 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154009014 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140471123 # Total data (bytes) +system.toL2Bus.throughput 154019994 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140481139 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 45730949 # Throughput (bytes/s) system.iobus.data_through_bus 41711051 # Total data (bytes) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7975768 # DTB read hits +system.cpu0.dtb.read_hits 7977216 # DTB read hits system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5966574 # DTB write hits +system.cpu0.dtb.write_hits 5966960 # DTB write hits system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7979379 # DTB read accesses -system.cpu0.dtb.write_accesses 5967246 # DTB write accesses +system.cpu0.dtb.read_accesses 7980827 # DTB read accesses +system.cpu0.dtb.write_accesses 5967632 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13942342 # DTB hits +system.cpu0.dtb.hits 13944176 # DTB hits system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13946625 # DTB accesses -system.cpu0.itb.inst_hits 30238804 # ITB inst hits +system.cpu0.dtb.accesses 13948459 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 30245736 # ITB inst hits system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -321,80 +363,80 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses -system.cpu0.itb.hits 30238804 # DTB hits +system.cpu0.itb.inst_accesses 30247911 # ITB inst accesses +system.cpu0.itb.hits 30245736 # DTB hits system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30240979 # DTB accesses -system.cpu0.numCycles 1823671407 # number of cpu cycles simulated +system.cpu0.itb.accesses 30247911 # DTB accesses +system.cpu0.numCycles 1823671415 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29750005 # Number of instructions committed -system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses +system.cpu0.committedInsts 29756754 # Number of instructions committed +system.cpu0.committedOps 39137733 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34752271 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1241903 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34471201 # number of integer instructions +system.cpu0.num_func_calls 1242676 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4045310 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34752271 # number of integer instructions system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written +system.cpu0.num_int_register_reads 179899233 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36833612 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14626951 # number of memory refs -system.cpu0.num_load_insts 8357226 # Number of load instructions -system.cpu0.num_store_insts 6269725 # Number of store instructions -system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles -system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles +system.cpu0.num_mem_refs 14629077 # number of memory refs +system.cpu0.num_load_insts 8358676 # Number of load instructions +system.cpu0.num_store_insts 6270401 # Number of store instructions +system.cpu0.num_idle_cycles 1783997907.577739 # Number of idle cycles +system.cpu0.num_busy_cycles 39673507.422261 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021755 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978245 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.015213 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29818047 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.tags.avg_refs 69.496541 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537144000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015213 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30669233 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30669233 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits -system.cpu0.icache.overall_hits::total 29811115 # number of overall hits +system.cpu0.icache.tags.tag_accesses 30676165 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 30676165 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29818047 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29818047 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29818047 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29818047 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29818047 # number of overall hits +system.cpu0.icache.overall_hits::total 29818047 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30247106 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30247106 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30247106 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30247106 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30247106 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30247106 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014185 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014185 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014185 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014185 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014185 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014185 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,67 +447,67 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 323609 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 494.763093 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12469292 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.tags.avg_refs 38.487726 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763093 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51675155 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51675155 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 51682637 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51682637 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6513463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6513463 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5631258 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5631258 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits -system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 12144721 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12144721 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12144721 # number of overall hits +system.cpu0.dcache.overall_hits::total 12144721 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167351 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167351 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses -system.cpu0.dcache.overall_misses::total 364509 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 364518 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364518 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364518 # number of overall misses +system.cpu0.dcache.overall_misses::total 364518 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6710630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6710630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798609 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12509239 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12509239 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12509239 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12509239 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029381 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029381 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029140 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029140 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029140 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029140 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,28 +519,70 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks system.cpu0.dcache.writebacks::total 300958 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7364781 # DTB read hits +system.cpu1.dtb.read_hits 7365100 # DTB read hits system.cpu1.dtb.read_misses 3705 # DTB read misses -system.cpu1.dtb.write_hits 5489656 # DTB write hits +system.cpu1.dtb.write_hits 5489754 # DTB write hits system.cpu1.dtb.write_misses 1595 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7368486 # DTB read accesses -system.cpu1.dtb.write_accesses 5491251 # DTB write accesses +system.cpu1.dtb.read_accesses 7368805 # DTB read accesses +system.cpu1.dtb.write_accesses 5491349 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12854437 # DTB hits +system.cpu1.dtb.hits 12854854 # DTB hits system.cpu1.dtb.misses 5300 # DTB misses -system.cpu1.dtb.accesses 12859737 # DTB accesses -system.cpu1.itb.inst_hits 32412306 # ITB inst hits +system.cpu1.dtb.accesses 12860154 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 32413691 # ITB inst hits system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -508,48 +592,48 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses -system.cpu1.itb.hits 32412306 # DTB hits +system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses +system.cpu1.itb.hits 32413691 # DTB hits system.cpu1.itb.misses 2200 # DTB misses -system.cpu1.itb.accesses 32414506 # DTB accesses -system.cpu1.numCycles 1824193528 # number of cpu cycles simulated +system.cpu1.itb.accesses 32415891 # DTB accesses +system.cpu1.numCycles 1824193536 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31875965 # Number of instructions committed -system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses +system.cpu1.committedInsts 31877311 # Number of instructions committed +system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses -system.cpu1.num_func_calls 955227 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35797832 # number of integer instructions +system.cpu1.num_func_calls 955425 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35862250 # number of integer instructions system.cpu1.num_fp_insts 4436 # number of float instructions -system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written +system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written -system.cpu1.num_mem_refs 13370713 # number of memory refs -system.cpu1.num_load_insts 7642673 # Number of load instructions -system.cpu1.num_store_insts 5728040 # Number of store instructions -system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles -system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles +system.cpu1.num_mem_refs 13371151 # number of memory refs +system.cpu1.num_load_insts 7642991 # Number of load instructions +system.cpu1.num_store_insts 5728160 # Number of store instructions +system.cpu1.num_idle_cycles 1783399616.755682 # Number of idle cycles +system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 433942 # number of replacements -system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 475.447911 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967761000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447911 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -558,26 +642,26 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32848033 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32848033 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits -system.cpu1.icache.overall_hits::total 31979125 # number of overall hits +system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits +system.cpu1.icache.overall_hits::total 31980510 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses system.cpu1.icache.overall_misses::total 434454 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses @@ -595,10 +679,10 @@ system.cpu1.icache.cache_copies 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 294289 # number of replacements system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.total_refs 11708150 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.avg_refs 39.715435 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293491000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy @@ -608,56 +692,56 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48417680 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48417680 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 48419345 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 48419345 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002503 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002503 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520265 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520265 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 11522768 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522768 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522768 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522768 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126066 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126066 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses -system.cpu1.dcache.overall_misses::total 324195 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 324341 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324341 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324341 # number of overall misses +system.cpu1.dcache.overall_misses::total 324341 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027132 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index ab338ac30..54d6bfa01 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -288,7 +363,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 41742298b..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 8105d53fc..c1d447bb6 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:43 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:34 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x55f5800 0x55f5800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2332810264000 because m5_exit instruction encountered +Exiting @ tick 2332810269000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 0b833a71d..75a8f8d3e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810264000 # Number of ticks simulated -final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2332810269000 # Number of ticks simulated +final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1656319 # Simulator instruction rate (inst/s) -host_op_rate 2129924 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63962280307 # Simulator tick rate (ticks/s) -host_mem_usage 398176 # Number of bytes of host memory used -host_seconds 36.47 # Real time elapsed on the host -sim_insts 60408639 # Number of instructions simulated -sim_ops 77681819 # Number of ops (including micro ops) simulated +host_inst_rate 1274625 # Simulator instruction rate (inst/s) +host_op_rate 1639090 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49222371545 # Simulator tick rate (ticks/s) +host_mem_usage 420236 # Number of bytes of host memory used +host_seconds 47.39 # Real time elapsed on the host +sim_insts 60408649 # Number of instructions simulated +sim_ops 77681829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) @@ -48,9 +48,9 @@ system.physmem.bw_total::writebacks 1587455 # To system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -63,8 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969585 # Throughput (bytes/s) -system.membus.data_through_bus 130566422 # Total data (bytes) +system.membus.throughput 55969605 # Throughput (bytes/s) +system.membus.data_through_bus 130566470 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -75,9 +75,30 @@ system.cf0.dma_write_txs 0 # Nu system.iobus.throughput 48895252 # Throughput (bytes/s) system.iobus.data_through_bus 114063346 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971214 # DTB read hits +system.cpu.dtb.read_hits 14971217 # DTB read hits system.cpu.dtb.read_misses 7294 # DTB read misses system.cpu.dtb.write_hits 11217004 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses @@ -85,17 +106,38 @@ system.cpu.dtb.flush_tlb 2 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978508 # DTB read accesses +system.cpu.dtb.read_accesses 14978511 # DTB read accesses system.cpu.dtb.write_accesses 11219185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188218 # DTB hits +system.cpu.dtb.hits 26188221 # DTB hits system.cpu.dtb.misses 9475 # DTB misses -system.cpu.dtb.accesses 26197693 # DTB accesses +system.cpu.dtb.accesses 26197696 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 61431840 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -106,7 +148,7 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -117,37 +159,37 @@ system.cpu.itb.inst_accesses 61436311 # IT system.cpu.itb.hits 61431840 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61436311 # DTB accesses -system.cpu.numCycles 4665620529 # number of cpu cycles simulated +system.cpu.numCycles 4665620539 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60408639 # Number of instructions committed -system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses +system.cpu.committedInsts 60408649 # Number of instructions committed +system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 2136008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls -system.cpu.num_int_insts 68795605 # number of integer instructions +system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls +system.cpu.num_int_insts 69130761 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read -system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written +system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read +system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27361637 # number of memory refs -system.cpu.num_load_insts 15639527 # Number of load instructions +system.cpu.num_mem_refs 27361639 # number of memory refs +system.cpu.num_load_insts 15639529 # Number of load instructions system.cpu.num_store_insts 11722110 # Number of store instructions -system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles -system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles +system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles +system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor +system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -192,16 +234,16 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62243 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy @@ -312,12 +354,12 @@ system.cpu.l2cache.writebacks::writebacks 57863 # n system.cpu.l2cache.writebacks::total 57863 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 623337 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -382,8 +424,8 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) +system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index da0c44ae8..9fa392075 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -243,19 +318,21 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -295,7 +372,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[5] +mem_side=system.toL2Bus.slave[7] [system.cpu1.dcache.tags] type=LRU @@ -307,10 +384,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -318,9 +420,10 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[7] +port=system.toL2Bus.slave[9] [system.cpu1.icache] type=BaseCache @@ -345,7 +448,7 @@ tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[4] +mem_side=system.toL2Bus.slave[6] [system.cpu1.icache.tags] type=LRU @@ -365,24 +468,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -390,9 +529,10 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[6] +port=system.toL2Bus.slave[8] [system.cpu1.tracer] type=ExeTracer @@ -1029,7 +1169,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index 5a43c8b18..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -10,7 +10,4 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 012824f20..2b6d5c5d8 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:31:37 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:08:43 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x6319800 0x6319800 + 0: system.cpu1.isa: ISA system set to: 0x6319800 0x6319800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1196134388000 because m5_exit instruction encountered +Exiting @ tick 1196139241000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index da78d67e8..6ed9b7b45 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196134 # Number of seconds simulated -sim_ticks 1196134388000 # Number of ticks simulated -final_tick 1196134388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196139 # Number of seconds simulated +sim_ticks 1196139241000 # Number of ticks simulated +final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 708523 # Simulator instruction rate (inst/s) -host_op_rate 902798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13791811883 # Simulator tick rate (ticks/s) -host_mem_usage 403420 # Number of bytes of host memory used -host_seconds 86.73 # Real time elapsed on the host -sim_insts 61448705 # Number of instructions simulated -sim_ops 78297711 # Number of ops (including micro ops) simulated +host_inst_rate 553961 # Simulator instruction rate (inst/s) +host_op_rate 705843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10781179789 # Simulator tick rate (ticks/s) +host_mem_usage 425360 # Number of bytes of host memory used +host_seconds 110.95 # Real time elapsed on the host +sim_insts 61460236 # Number of instructions simulated +sim_ops 78311148 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4798512 # Number of bytes read from this memory -system.physmem.bytes_read::total 62145764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4112768 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory +system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7140112 # Number of bytes written to this memory +system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654482 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64262 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821098 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393546 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3950101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 270869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4011683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51955503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328876 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 270869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3438383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516727 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5969323 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3438383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3964314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 270869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6528410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57924826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654482 # Number of read requests accepted -system.physmem.writeReqs 821098 # Number of write requests accepted -system.physmem.readBursts 6654482 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425858048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 28800 # Total number of bytes read from write queue -system.physmem.bytesWritten 7268928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62145764 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7140112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 450 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707519 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11807 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415388 # Per bank write bursts -system.physmem.perBankRdBursts::1 415219 # Per bank write bursts -system.physmem.perBankRdBursts::2 415339 # Per bank write bursts -system.physmem.perBankRdBursts::3 415675 # Per bank write bursts -system.physmem.perBankRdBursts::4 422391 # Per bank write bursts -system.physmem.perBankRdBursts::5 415542 # Per bank write bursts -system.physmem.perBankRdBursts::6 415783 # Per bank write bursts -system.physmem.perBankRdBursts::7 415483 # Per bank write bursts -system.physmem.perBankRdBursts::8 416074 # Per bank write bursts -system.physmem.perBankRdBursts::9 415577 # Per bank write bursts -system.physmem.perBankRdBursts::10 415272 # Per bank write bursts -system.physmem.perBankRdBursts::11 414856 # Per bank write bursts -system.physmem.perBankRdBursts::12 415143 # Per bank write bursts -system.physmem.perBankRdBursts::13 415555 # Per bank write bursts -system.physmem.perBankRdBursts::14 415537 # Per bank write bursts -system.physmem.perBankRdBursts::15 415198 # Per bank write bursts -system.physmem.perBankWrBursts::0 6998 # Per bank write bursts -system.physmem.perBankWrBursts::1 6842 # Per bank write bursts -system.physmem.perBankWrBursts::2 7022 # Per bank write bursts -system.physmem.perBankWrBursts::3 7170 # Per bank write bursts -system.physmem.perBankWrBursts::4 7417 # Per bank write bursts -system.physmem.perBankWrBursts::5 7181 # Per bank write bursts -system.physmem.perBankWrBursts::6 7437 # Per bank write bursts -system.physmem.perBankWrBursts::7 7180 # Per bank write bursts -system.physmem.perBankWrBursts::8 7616 # Per bank write bursts -system.physmem.perBankWrBursts::9 7218 # Per bank write bursts -system.physmem.perBankWrBursts::10 7106 # Per bank write bursts -system.physmem.perBankWrBursts::11 6658 # Per bank write bursts -system.physmem.perBankWrBursts::12 6803 # Per bank write bursts -system.physmem.perBankWrBursts::13 7016 # Per bank write bursts -system.physmem.perBankWrBursts::14 7092 # Per bank write bursts -system.physmem.perBankWrBursts::15 6821 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654445 # Number of read requests accepted +system.physmem.writeReqs 821063 # Number of write requests accepted +system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue +system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415328 # Per bank write bursts +system.physmem.perBankRdBursts::1 415204 # Per bank write bursts +system.physmem.perBankRdBursts::2 415403 # Per bank write bursts +system.physmem.perBankRdBursts::3 415627 # Per bank write bursts +system.physmem.perBankRdBursts::4 422407 # Per bank write bursts +system.physmem.perBankRdBursts::5 415617 # Per bank write bursts +system.physmem.perBankRdBursts::6 415785 # Per bank write bursts +system.physmem.perBankRdBursts::7 415500 # Per bank write bursts +system.physmem.perBankRdBursts::8 416027 # Per bank write bursts +system.physmem.perBankRdBursts::9 415632 # Per bank write bursts +system.physmem.perBankRdBursts::10 415316 # Per bank write bursts +system.physmem.perBankRdBursts::11 414840 # Per bank write bursts +system.physmem.perBankRdBursts::12 415044 # Per bank write bursts +system.physmem.perBankRdBursts::13 415557 # Per bank write bursts +system.physmem.perBankRdBursts::14 415554 # Per bank write bursts +system.physmem.perBankRdBursts::15 415143 # Per bank write bursts +system.physmem.perBankWrBursts::0 6946 # Per bank write bursts +system.physmem.perBankWrBursts::1 6844 # Per bank write bursts +system.physmem.perBankWrBursts::2 7080 # Per bank write bursts +system.physmem.perBankWrBursts::3 7140 # Per bank write bursts +system.physmem.perBankWrBursts::4 7438 # Per bank write bursts +system.physmem.perBankWrBursts::5 7223 # Per bank write bursts +system.physmem.perBankWrBursts::6 7431 # Per bank write bursts +system.physmem.perBankWrBursts::7 7190 # Per bank write bursts +system.physmem.perBankWrBursts::8 7575 # Per bank write bursts +system.physmem.perBankWrBursts::9 7264 # Per bank write bursts +system.physmem.perBankWrBursts::10 7139 # Per bank write bursts +system.physmem.perBankWrBursts::11 6649 # Per bank write bursts +system.physmem.perBankWrBursts::12 6729 # Per bank write bursts +system.physmem.perBankWrBursts::13 7011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7090 # Per bank write bursts +system.physmem.perBankWrBursts::15 6760 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196129800000 # Total gap between requests +system.physmem.totGap 1196134740000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6825 # Read request sizes (log2) +system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159593 # Read request sizes (log2) +system.physmem.readPktSize::6 159532 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64262 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 634838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 481612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 482409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1579414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1125551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1120257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1116869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -165,28 +165,28 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see @@ -197,401 +197,419 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5819.401301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 396.636644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13081.491079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25728 34.57% 34.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15292 20.55% 55.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3262 4.38% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2304 3.10% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1614 2.17% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1322 1.78% 66.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1040 1.40% 67.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1190 1.60% 69.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 729 0.98% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 570 0.77% 71.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 569 0.76% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 665 0.89% 72.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 312 0.42% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 285 0.38% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 210 0.28% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 384 0.52% 74.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 194 0.26% 74.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 136 0.18% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 150 0.20% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 155 0.21% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2260 3.04% 78.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 133 0.18% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 107 0.14% 78.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 57 0.08% 78.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 59 0.08% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 48 0.06% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 56 0.08% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 51 0.07% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 23 0.03% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 16 0.02% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 212 0.28% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 23 0.03% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 26 0.03% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 105 0.14% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 15 0.02% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 24 0.03% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 92 0.12% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 21 0.03% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 18 0.02% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 21 0.03% 80.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 12 0.02% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 19 0.03% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 7 0.01% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 116 0.16% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 25 0.03% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 8 0.01% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 13 0.02% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 99 0.13% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 8 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 17 0.02% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 23 0.03% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 8 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 15 0.02% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 32 0.04% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 26 0.03% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 126 0.17% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 7 0.01% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 15 0.02% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 15 0.02% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 38 0.05% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 14 0.02% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 85 0.11% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 8 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 9 0.01% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 16 0.02% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 156 0.21% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 81.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 15 0.02% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 169 0.23% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 1 0.00% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 88 0.12% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 23 0.03% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 97 0.13% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 26 0.03% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 83 0.11% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 1 0.00% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 16 0.02% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 82.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 74 0.10% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 17 0.02% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 18 0.02% 82.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 158 0.21% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 1 0.00% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 22 0.03% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8583 1 0.00% 82.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 18 0.02% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 80 0.11% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 161 0.22% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 14 0.02% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9607 1 0.00% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 83 0.11% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 26 0.03% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 95 0.13% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 23 0.03% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 85 0.11% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 14 0.02% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 2 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 160 0.21% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 71 0.10% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 35 0.05% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 73 0.10% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 102 0.14% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 14 0.02% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 14 0.02% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 79 0.11% 84.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 6 0.01% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 79 0.11% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 82 0.11% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 173 0.23% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 28 0.04% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 20 0.03% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 17 0.02% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15303 1 0.00% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 165 0.22% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 18 0.02% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15687 1 0.00% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 85 0.11% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16007 2 0.00% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 16 0.02% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 274 0.37% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 28 0.04% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 83 0.11% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17095 1 0.00% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 19 0.03% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17223 1 0.00% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 163 0.22% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17607 1 0.00% 86.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 16 0.02% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 18 0.02% 86.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 1 0.00% 86.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 25 0.03% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 2 0.00% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 168 0.23% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 83 0.11% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 80 0.11% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 10 0.01% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 84 0.11% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 79 0.11% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 12 0.02% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 18 0.02% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 106 0.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 76 0.10% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20928-20935 1 0.00% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 32 0.04% 87.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 72 0.10% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 1 0.00% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 147 0.20% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 16 0.02% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 88 0.12% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22144-22151 1 0.00% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 18 0.02% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 92 0.12% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22599 1 0.00% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 29 0.04% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 83 0.11% 88.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 10 0.01% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 156 0.21% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 72 0.10% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 14 0.02% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 162 0.22% 88.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 2 0.00% 88.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 25 0.03% 88.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 16 0.02% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25223 1 0.00% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 2 0.00% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 74 0.10% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 153 0.21% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 12 0.02% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 84 0.11% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 23 0.03% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 2 0.00% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 91 0.12% 89.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 22 0.03% 89.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 88 0.12% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 18 0.02% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 143 0.19% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 72 0.10% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 33 0.04% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28224-28231 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 78 0.10% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 106 0.14% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 16 0.02% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 11 0.01% 90.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 79 0.11% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 86 0.12% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 2 0.00% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 79 0.11% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 88 0.12% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 164 0.22% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 2 0.00% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 26 0.03% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 20 0.03% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 12 0.02% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 163 0.22% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 12 0.02% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32064-32071 1 0.00% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 82 0.11% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 278 0.37% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 2 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 21 0.03% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 92 0.12% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 3 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33479 1 0.00% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 12 0.02% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 159 0.21% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 20 0.03% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 27 0.04% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 160 0.21% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation 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Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::48128-48135 184 0.25% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 2 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 42 0.06% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48448-48455 1 0.00% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 81 0.11% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 14 0.02% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 7 0.01% 97.15% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation +system.physmem.totQLat 159552537250 # Total ticks spent queuing +system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks +system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30426.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.52 # Average write queue length when enqueuing -system.physmem.readRowHits 6598367 # Number of row buffer hits during reads -system.physmem.writeRowHits 94814 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing +system.physmem.readRowHits 6598277 # Number of row buffer hits during reads +system.physmem.writeRowHits 94784 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes -system.physmem.avgGap 160004.95 # Average gap between requests +system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes +system.physmem.avgGap 160007.15 # Average gap between requests system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.95 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -610,314 +628,314 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59941628 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703327 # Transaction distribution -system.membus.trans_dist::ReadResp 7703327 # Transaction distribution -system.membus.trans_dist::WriteReq 767563 # Transaction distribution -system.membus.trans_dist::WriteResp 767563 # Transaction distribution -system.membus.trans_dist::Writeback 64262 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31362 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17250 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11807 # Transaction distribution -system.membus.trans_dist::ReadExReq 137774 # Transaction distribution -system.membus.trans_dist::ReadExResp 137331 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382556 # Packet count per connected master and slave (bytes) +system.membus.throughput 59936382 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703367 # Transaction distribution +system.membus.trans_dist::ReadResp 7703367 # Transaction distribution +system.membus.trans_dist::WriteReq 767572 # Transaction distribution +system.membus.trans_dist::WriteResp 767572 # Transaction distribution +system.membus.trans_dist::Writeback 64227 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution +system.membus.trans_dist::ReadExReq 137706 # Transaction distribution +system.membus.trans_dist::ReadExResp 137264 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4365438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17341566 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389866 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17381364 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19793730 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71698242 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71698242 # Total data (bytes) +system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71692258 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224728000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9233500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211169999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5081009046 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657682249 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69474 # number of replacements -system.l2c.tags.tagsinuse 52958.436277 # Cycle average of tags in use -system.l2c.tags.total_refs 1673866 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134633 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.432806 # Average number of references to valid blocks. +system.l2c.tags.replacements 69413 # number of replacements +system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use +system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40141.137275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3711.443492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4231.516476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2812.646868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2058.946054 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612505 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056632 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064752 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808922 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65181 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8037 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55165 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17208079 # Number of tag accesses -system.l2c.tags.data_accesses 17208079 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1845 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464495 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143269 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246060 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570845 # number of Writeback hits -system.l2c.Writeback_hits::total 570845 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 560 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1719 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56634 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109230 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3830 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1845 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464495 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 195865 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355290 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3830 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1752 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits -system.l2c.overall_hits::cpu0.data 262480 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5350 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1845 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464495 # number of overall hits -system.l2c.overall_hits::cpu1.data 195865 # number of overall hits -system.l2c.overall_hits::total 1355290 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994583 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17211018 # Number of tag accesses +system.l2c.tags.data_accesses 17211018 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 3808 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464853 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143402 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1246251 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571037 # number of Writeback hits +system.l2c.Writeback_hits::total 571037 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1156 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 566 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1722 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 102 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56302 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52763 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109065 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3808 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262229 # number of demand (read+write) hits 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59025.268693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1111,62 +1129,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119504988 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535165 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535165 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767563 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767563 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570845 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30638 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17564 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48202 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260860 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260860 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864640 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226897 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6150 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600271 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7671923 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41401460 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30051724 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39586058 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138342918 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138342918 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4601108 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4758624958 # Layer occupancy (ticks) +system.toL2Bus.throughput 119505667 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138342022 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1926201968 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1755625353 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2116407722 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2924723840 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326499 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 9919749 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391537 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671396 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671396 # Transaction distribution -system.iobus.trans_dist::WriteReq 7946 # Transaction distribution -system.iobus.trans_dist::WriteResp 7946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8052 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 45391376 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution +system.iobus.trans_dist::WriteReq 7950 # Transaction distribution +system.iobus.trans_dist::WriteResp 7950 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1188,12 +1206,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382556 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358684 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1215,14 +1233,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389866 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294378 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294406 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4032000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1268,32 +1286,74 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374610000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778098751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7069308 # DTB read hits -system.cpu0.dtb.read_misses 3747 # DTB read misses -system.cpu0.dtb.write_hits 5655300 # DTB write hits -system.cpu0.dtb.write_misses 806 # DTB write misses +system.cpu0.dtb.read_hits 7064121 # DTB read hits +system.cpu0.dtb.read_misses 3756 # DTB read misses +system.cpu0.dtb.write_hits 5649416 # DTB write hits +system.cpu0.dtb.write_misses 801 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1799 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073055 # DTB read accesses -system.cpu0.dtb.write_accesses 5656106 # DTB write accesses +system.cpu0.dtb.read_accesses 7067877 # DTB read accesses +system.cpu0.dtb.write_accesses 5650217 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12724608 # DTB hits -system.cpu0.dtb.misses 4553 # DTB misses -system.cpu0.dtb.accesses 12729161 # DTB accesses -system.cpu0.itb.inst_hits 29565201 # ITB inst hits +system.cpu0.dtb.hits 12713537 # DTB hits +system.cpu0.dtb.misses 4557 # DTB misses +system.cpu0.dtb.accesses 12718094 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 29561361 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1303,94 +1363,94 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29567406 # ITB inst accesses -system.cpu0.itb.hits 29565201 # DTB hits +system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses +system.cpu0.itb.hits 29561361 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29567406 # DTB accesses -system.cpu0.numCycles 2392268776 # number of cpu cycles simulated +system.cpu0.itb.accesses 29563566 # DTB accesses +system.cpu0.numCycles 2392278482 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28867316 # Number of instructions committed -system.cpu0.committedOps 37205643 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33092917 # Number of integer alu accesses +system.cpu0.committedInsts 28863304 # Number of instructions committed +system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241596 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372519 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33092917 # number of integer instructions +system.cpu0.num_func_calls 1241816 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33114268 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190017972 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36219842 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13392372 # number of memory refs -system.cpu0.num_load_insts 7406786 # Number of load instructions -system.cpu0.num_store_insts 5985586 # Number of store instructions -system.cpu0.num_idle_cycles 2246456550.382122 # Number of idle cycles -system.cpu0.num_busy_cycles 145812225.617878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060951 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939049 # Percentage of idle cycles +system.cpu0.num_mem_refs 13380719 # number of memory refs +system.cpu0.num_load_insts 7401377 # Number of load instructions +system.cpu0.num_store_insts 5979342 # Number of store instructions +system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles +system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46712 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 425445 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.359322 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29139226 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425957 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.408844 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 424872 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359322 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29991142 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29991142 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29139226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29139226 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29139226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29139226 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29139226 # number of overall hits -system.cpu0.icache.overall_hits::total 29139226 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses -system.cpu0.icache.overall_misses::total 425958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5905644218 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5905644218 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5905644218 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5905644218 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5905644218 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5905644218 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29565184 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29565184 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29565184 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29565184 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29565184 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29565184 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014407 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014407 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014407 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014407 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014407 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014407 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13864.381507 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13864.381507 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13864.381507 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13864.381507 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13864.381507 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13864.381507 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 29986729 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 29986729 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29135959 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29135959 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29135959 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29135959 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29135959 # number of overall hits +system.cpu0.icache.overall_hits::total 29135959 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425385 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425385 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425385 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425385 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425385 # number of overall misses +system.cpu0.icache.overall_misses::total 425385 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5898245722 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5898245722 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5898245722 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5898245722 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5898245722 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5898245722 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29561344 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29561344 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29561344 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29561344 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29561344 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29561344 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014390 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014390 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014390 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014390 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014390 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014390 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13865.664567 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13865.664567 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13865.664567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13865.664567 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1399,128 +1459,128 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5051503782 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5051503782 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5051503782 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5051503782 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5051503782 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5051503782 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014407 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014407 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014407 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014407 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11859.159311 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11859.159311 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11859.159311 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11859.159311 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11859.159311 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11859.159311 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425385 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425385 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425385 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425385 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425385 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425385 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045266278 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045266278 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045266278 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5045266278 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045266278 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5045266278 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014390 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014390 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014390 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11860.470581 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 330301 # number of replacements -system.cpu0.dcache.tags.tagsinuse 454.615886 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12269300 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 330813 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.088325 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 454.615886 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.887922 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.887922 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 329699 # number of replacements +system.cpu0.dcache.tags.tagsinuse 455.775151 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12258801 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 330211 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.124145 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.775151 # Average occupied blocks per requestor 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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50897043 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50897043 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6599288 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6599288 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5350353 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5350353 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147935 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147935 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149626 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149626 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11949641 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11949641 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11949641 # number of overall hits -system.cpu0.dcache.overall_hits::total 11949641 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227704 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227704 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141542 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141542 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9305 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9305 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7516 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7516 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369246 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369246 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369246 # number of overall misses -system.cpu0.dcache.overall_misses::total 369246 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3302919746 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3302919746 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5684238795 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5684238795 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91447249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 91447249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44459563 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44459563 # number 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LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157142 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157142 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12318887 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12318887 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12318887 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12318887 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033353 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033353 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025773 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025773 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059177 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059177 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047829 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047829 # miss rate for StoreCondReq accesses +system.cpu0.dcache.tags.tag_accesses 50852132 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50852132 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6594161 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6594161 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5344638 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5344638 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148004 # number 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misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7481 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7481 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 368910 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 368910 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 368910 # number of overall misses +system.cpu0.dcache.overall_misses::total 368910 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3307426746 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3307426746 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5667209233 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5667209233 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93091750 # number of LoadLockedReq miss cycles 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overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14505.321584 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14505.321584 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40159.378806 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40159.378806 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9827.753788 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9827.753788 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5915.322379 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5915.322379 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24339.217056 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24339.217056 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24339.217056 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14535.775483 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14535.775483 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40086.927723 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40086.927723 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1529,66 +1589,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305829 # number of writebacks -system.cpu0.dcache.writebacks::total 305829 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227704 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227704 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141542 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141542 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9305 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9305 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7514 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7514 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369246 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369246 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369246 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369246 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2845576254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2845576254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5370172205 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5370172205 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72789751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72789751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29432437 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29432437 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8215748459 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8215748459 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8215748459 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8215748459 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13558596000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13558596000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167114500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167114500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14725710500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14725710500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033353 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033353 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059177 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059177 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047817 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047817 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 305670 # number of writebacks +system.cpu0.dcache.writebacks::total 305670 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227537 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227537 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141373 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141373 # number of WriteReq MSHR misses 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+system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12496.821549 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12496.821549 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37940.485545 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37940.485545 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7822.649221 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7822.649221 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3917.013175 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3917.013175 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22250.067595 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22250.067595 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1596,28 +1652,70 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311308 # DTB read hits -system.cpu1.dtb.read_misses 3642 # DTB read misses -system.cpu1.dtb.write_hits 5827742 # DTB write hits -system.cpu1.dtb.write_misses 1438 # DTB write misses +system.cpu1.dtb.read_hits 8319266 # DTB read hits +system.cpu1.dtb.read_misses 3647 # DTB read misses +system.cpu1.dtb.write_hits 5834802 # DTB write hits +system.cpu1.dtb.write_misses 1433 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8314950 # DTB read accesses -system.cpu1.dtb.write_accesses 5829180 # DTB write accesses +system.cpu1.dtb.read_accesses 8322913 # DTB read accesses +system.cpu1.dtb.write_accesses 5836235 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14139050 # DTB hits +system.cpu1.dtb.hits 14154068 # DTB hits system.cpu1.dtb.misses 5080 # DTB misses -system.cpu1.dtb.accesses 14144130 # DTB accesses -system.cpu1.itb.inst_hits 33191969 # ITB inst hits +system.cpu1.dtb.accesses 14159148 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 33207997 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1627,93 +1725,93 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33194140 # ITB inst accesses -system.cpu1.itb.hits 33191969 # DTB hits +system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses +system.cpu1.itb.hits 33207997 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33194140 # DTB accesses -system.cpu1.numCycles 2390799575 # number of cpu cycles simulated +system.cpu1.itb.accesses 33210168 # DTB accesses +system.cpu1.numCycles 2390803785 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32581389 # Number of instructions committed -system.cpu1.committedOps 41092068 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37316324 # Number of integer alu accesses +system.cpu1.committedInsts 32596932 # Number of instructions committed +system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962102 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732829 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37316324 # number of integer instructions +system.cpu1.num_func_calls 962790 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37644247 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213681333 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39457808 # number of times the integer registers were written +system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14676854 # number of memory refs -system.cpu1.num_load_insts 8633232 # Number of load instructions -system.cpu1.num_store_insts 6043622 # Number of store instructions -system.cpu1.num_idle_cycles 1874349488.166457 # Number of idle cycles -system.cpu1.num_busy_cycles 516450086.833543 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216016 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783984 # Percentage of idle cycles +system.cpu1.num_mem_refs 14692820 # number of memory refs +system.cpu1.num_load_insts 8641241 # Number of load instructions +system.cpu1.num_store_insts 6051579 # Number of store instructions +system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles +system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles +system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43916 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469558 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.567582 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32721895 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470070 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.610686 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93987592500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.567582 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934702 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934702 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 469929 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33662035 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33662035 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32721895 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32721895 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32721895 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32721895 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32721895 # number of overall hits -system.cpu1.icache.overall_hits::total 32721895 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470070 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470070 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470070 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470070 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470070 # number of overall misses -system.cpu1.icache.overall_misses::total 470070 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6444934971 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6444934971 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6444934971 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6444934971 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6444934971 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6444934971 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33191965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33191965 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33191965 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33191965 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33191965 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33191965 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014162 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014162 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014162 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014162 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014162 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014162 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13710.585596 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13710.585596 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13710.585596 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13710.585596 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13710.585596 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits +system.cpu1.icache.overall_hits::total 32737552 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses +system.cpu1.icache.overall_misses::total 470441 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1722,126 +1820,126 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11706.445906 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 470441 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 470441 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 470441 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5503297277 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5503297277 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5503297277 # number of demand (read+write) MSHR miss cycles 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11698.166778 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292078 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.633961 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11962120 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292453 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.902709 # Average number of references to valid blocks. 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Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 49497647 # 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+system.cpu1.dcache.demand_accesses::cpu1.data 12109261 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12109261 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12109261 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12109261 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023961 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023961 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120868 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120868 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026507 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026507 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026507 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026507 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12999.601654 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12999.601654 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43832.403883 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 43832.403883 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8651.942523 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8651.942523 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5173.112592 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5173.112592 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27432.974553 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27432.974553 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1850,66 +1948,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265016 # number of writebacks -system.cpu1.dcache.writebacks::total 265016 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170562 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170562 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149956 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149956 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11055 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11055 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10052 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10052 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320518 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320518 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320518 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320518 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877722752 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877722752 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6246095798 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6246095798 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70722250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70722250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32100518 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32100518 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8123818550 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8123818550 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8123818550 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8123818550 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168605274000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168605274000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182596842 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182596842 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193787870842 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193787870842 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023964 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023964 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030127 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.118999 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.118999 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108319 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026501 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026501 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026501 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11009.033384 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11009.033384 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41652.856825 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41652.856825 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6397.308910 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6397.308910 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3193.445881 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3193.445881 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25345.904286 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25345.904286 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks +system.cpu1.dcache.writebacks::total 265367 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108280 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108280 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10995.636190 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10995.636190 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41676.687389 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41676.687389 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1933,10 +2027,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651789578751 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651789578751 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651789578751 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651789578751 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index ea47afb6b..4a127f1c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,19 +96,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -150,10 +162,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -161,6 +198,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -208,24 +246,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -233,6 +307,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -281,7 +356,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 41742298b..9dee17aa2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -11,5 +11,3 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 866b5bc98..a3076394e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:31:30 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:08:28 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x6b2c800 0x6b2c800 info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2616536483000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 9c560044d..9cf325a75 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,43 +4,43 @@ sim_seconds 2.616536 # Nu sim_ticks 2616536483000 # Number of ticks simulated final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 577538 # Simulator instruction rate (inst/s) -host_op_rate 734941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25103147507 # Simulator tick rate (ticks/s) -host_mem_usage 400220 # Number of bytes of host memory used -host_seconds 104.23 # Real time elapsed on the host -sim_insts 60197580 # Number of instructions simulated -sim_ops 76603973 # Number of ops (including micro ops) simulated +host_inst_rate 506890 # Simulator instruction rate (inst/s) +host_op_rate 645039 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22032386663 # Simulator tick rate (ticks/s) +host_mem_usage 421264 # Number of bytes of host memory used +host_seconds 118.76 # Real time elapsed on the host +sim_insts 60197590 # Number of instructions simulated +sim_ops 76603983 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089752 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142063 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494705 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s) @@ -48,17 +48,17 @@ system.physmem.bw_total::writebacks 1416443 # To system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494693 # Number of read requests accepted +system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53200016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494705 # Number of read requests accepted system.physmem.writeReqs 811927 # Number of write requests accepted -system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15494705 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 991556032 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 132477536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one @@ -77,7 +77,7 @@ system.physmem.perBankRdBursts::10 967949 # Pe system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967766 # Per bank write bursts +system.physmem.perBankRdBursts::14 967778 # Per bank write bursts system.physmem.perBankRdBursts::15 967796 # Per bank write bursts system.physmem.perBankWrBursts::0 6610 # Per bank write bursts system.physmem.perBankWrBursts::1 6410 # Per bank write bursts @@ -100,7 +100,7 @@ system.physmem.numWrRetry 0 # Nu system.physmem.totGap 2616532122000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6652 # Read request sizes (log2) +system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) @@ -112,7 +112,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 57909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1246989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1247001 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see @@ -176,98 +176,98 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89677 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11133.273058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1028.792401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16712.114180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23203 25.87% 25.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14561 16.24% 42.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2861 3.19% 45.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2042 2.28% 47.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1356 1.51% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1217 1.36% 50.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 956 1.07% 51.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1130 1.26% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 649 0.72% 53.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 589 0.66% 54.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 514 0.57% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 694 0.77% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 336 0.37% 55.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 266 0.30% 56.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 214 0.24% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 152 0.17% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 137 0.15% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 157 0.18% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 104 0.12% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 181 0.20% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 57 0.06% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 89676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11133.405772 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.811660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16712.159564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23202 25.87% 25.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14564 16.24% 42.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2857 3.19% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2044 2.28% 47.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1359 1.52% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1218 1.36% 50.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 957 1.07% 51.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1129 1.26% 52.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 646 0.72% 53.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 589 0.66% 54.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 513 0.57% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 690 0.77% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 338 0.38% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 262 0.29% 56.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 213 0.24% 56.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 156 0.17% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 151 0.17% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 136 0.15% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 156 0.17% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 102 0.11% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2292 2.56% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 63 0.07% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 60 0.07% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 44 0.05% 61.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 31 0.03% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 32 0.04% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 11 0.01% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 93 0.10% 61.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 15 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 26 0.03% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 91 0.10% 61.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 14 0.02% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 12 0.01% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 12 0.01% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 372 0.41% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 19 0.02% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 153 0.17% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 30 0.03% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 25 0.03% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 303 0.34% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 18 0.02% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 33 0.04% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 13 0.01% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 97 0.11% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 22 0.02% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 14 0.02% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 28 0.03% 61.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 86 0.10% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 19 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 14 0.02% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 14 0.02% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 9 0.01% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 370 0.41% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 11 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 17 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 15 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 14 0.02% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 12 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 37 0.04% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 13 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 11 0.01% 63.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4103 225 0.25% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 11 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 9 0.01% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 10 0.01% 63.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::4352-4359 165 0.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 84 0.09% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 10 0.01% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 83 0.09% 63.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 89 0.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 10 0.01% 63.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 88 0.10% 63.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 11 0.01% 63.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 434 0.48% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 435 0.49% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 9 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 6 0.01% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 9 0.01% 64.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5383 26 0.03% 64.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 65 0.07% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 67 0.07% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 8 0.01% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 280 0.31% 64.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5895 72 0.08% 65.02% # Bytes accessed per row activation @@ -291,7 +291,7 @@ system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # system.physmem.bytesPerActivate::7936-7943 77 0.09% 66.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8199 401 0.45% 66.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::8448-8455 79 0.09% 66.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::8704-8711 24 0.03% 66.85% # Bytes accessed per row activation @@ -420,7 +420,7 @@ system.physmem.bytesPerActivate::25344-25351 86 0.10% 78.20% system.physmem.bytesPerActivate::25472-25479 3 0.00% 78.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::25920-25927 1 0.00% 78.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::26112-26119 89 0.10% 78.92% # Bytes accessed per row activation @@ -456,7 +456,7 @@ system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.76% system.physmem.bytesPerActivate::29440-29447 136 0.15% 80.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::29696-29703 347 0.39% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::29888-29895 1 0.00% 81.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::29952-29959 141 0.16% 81.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::30080-30087 2 0.00% 81.47% # Bytes accessed per row activation @@ -489,7 +489,7 @@ system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.93% system.physmem.bytesPerActivate::33536-33543 80 0.09% 84.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::33792-33799 484 0.54% 84.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::34048-34055 12 0.01% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 89 0.10% 84.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::34560-34567 94 0.10% 84.78% # Bytes accessed per row activation @@ -507,7 +507,7 @@ system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.42% system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::35840-35847 347 0.39% 85.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::36352-36359 87 0.10% 86.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::36416-36423 1 0.00% 86.05% # Bytes accessed per row activation @@ -613,15 +613,15 @@ system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89677 # Bytes accessed per row activation -system.physmem.totQLat 373683436750 # Total ticks spent queuing -system.physmem.totMemAccLat 469596379250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18447687500 # Total ticks spent accessing banks -system.physmem.avgQLat 24119.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1190.71 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::total 89676 # Bytes accessed per row activation +system.physmem.totQLat 373682624750 # Total ticks spent queuing +system.physmem.totMemAccLat 469595819750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465315000 # Total ticks spent in databus transfers +system.physmem.totBankLat 18447880000 # Total ticks spent accessing banks +system.physmem.avgQLat 24119.35 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1190.72 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30310.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30310.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s @@ -632,11 +632,11 @@ system.physmem.busUtilRead 2.96 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 15419160 # Number of row buffer hits during reads +system.physmem.readRowHits 15419173 # Number of row buffer hits during reads system.physmem.writeRowHits 91146 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes -system.physmem.avgGap 160458.28 # Average gap between requests +system.physmem.avgGap 160458.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory @@ -651,9 +651,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54116520 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546551 # Transaction distribution -system.membus.trans_dist::ReadResp 16546551 # Transaction distribution +system.membus.throughput 54116538 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546563 # Transaction distribution +system.membus.trans_dist::ReadResp 16546563 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution system.membus.trans_dist::Writeback 57909 # Transaction distribution @@ -665,21 +665,21 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 23 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893537 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280385 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951233 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516392 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914505 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141597849 # Total data (bytes) +system.membus.tot_pkt_size::total 141597897 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141597897 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -689,9 +689,9 @@ system.membus.reqLayer2.occupancy 3614000 # La system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910610000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910622000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950347835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950375335 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) @@ -814,9 +814,30 @@ system.iobus.respLayer0.utilization 0.1 # La system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995644 # DTB read hits +system.cpu.dtb.read_hits 14995647 # DTB read hits system.cpu.dtb.read_misses 7334 # DTB read misses system.cpu.dtb.write_hits 11230146 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses @@ -824,17 +845,38 @@ system.cpu.dtb.flush_tlb 2 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3498 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002978 # DTB read accesses +system.cpu.dtb.read_accesses 15002981 # DTB read accesses system.cpu.dtb.write_accesses 11232358 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26225790 # DTB hits +system.cpu.dtb.hits 26225793 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 26235336 # DTB accesses +system.cpu.dtb.accesses 26235339 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 61491413 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -845,7 +887,7 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -859,20 +901,20 @@ system.cpu.itb.accesses 61495884 # DT system.cpu.numCycles 5233072966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197580 # Number of instructions committed -system.cpu.committedOps 76603973 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68871033 # Number of integer alu accesses +system.cpu.committedInsts 60197590 # Number of instructions committed +system.cpu.committedOps 76603983 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69206189 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 2140403 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948247 # number of instructions that are conditional controls -system.cpu.num_int_insts 68871033 # number of integer instructions +system.cpu.num_conditional_control_insts 7948249 # number of instructions that are conditional controls +system.cpu.num_int_insts 69206189 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394768801 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180798 # number of times the integer registers were written +system.cpu.num_int_register_reads 401354573 # number of times the integer registers were read +system.cpu.num_int_register_writes 74515956 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393280 # number of memory refs -system.cpu.num_load_insts 15659727 # Number of load instructions +system.cpu.num_mem_refs 27393282 # number of memory refs +system.cpu.num_load_insts 15659729 # Number of load instructions system.cpu.num_store_insts 11733553 # Number of store instructions system.cpu.num_idle_cycles 4581527140.608249 # Number of idle cycles system.cpu.num_busy_cycles 651545825.391751 # Number of busy cycles @@ -881,12 +923,12 @@ system.cpu.idle_fraction 0.875495 # Pe system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed system.cpu.icache.tags.replacements 856260 # number of replacements -system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.868407 # Cycle average of tags in use system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.868407 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -909,12 +951,12 @@ system.cpu.icache.demand_misses::cpu.inst 856772 # n system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses system.cpu.icache.overall_misses::total 856772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773713250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11773713250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11773713250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11773713250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11773713250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11773713250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11774021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11774021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11774021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11774021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11774021000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses @@ -927,12 +969,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.944473 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13741.944473 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13741.944473 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13741.944473 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.303670 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13742.303670 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13742.303670 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.303670 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13742.303670 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,44 +989,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856772 system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056122750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056122750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056122750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056122750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056122750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056122750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 435321250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056430000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056430000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 435943750 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.221513 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.221513 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.580126 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.580126 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.580126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.580126 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62509 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.670351 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 50754.656257 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.407530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.394097 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400299 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977449 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977018 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -1045,23 +1087,23 @@ system.cpu.l2cache.overall_misses::cpu.data 143632 # system.cpu.l2cache.overall_misses::total 154224 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752204750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 737637250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1490297250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752512000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 736932000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1489899250 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9620282393 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9620282393 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9619897393 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9619897393 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 752204750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10357919643 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11110579643 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 752512000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10356829393 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11109796643 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 752204750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10357919643 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11110579643 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 752512000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10356829393 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11109796643 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses) @@ -1104,23 +1146,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 system.cpu.l2cache.overall_miss_rate::total 0.103227 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71063.273500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75200.045876 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73050.205872 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71092.300425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.147620 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73030.697025 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71888.108868 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71888.108868 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71885.231933 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71885.231933 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72041.832938 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72036.755907 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71063.273500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72114.289594 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72041.832938 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71092.300425 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72106.699016 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72036.755907 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1152,31 +1194,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143632 system.cpu.l2cache.overall_mshr_misses::total 154224 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619637750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614753750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1234759250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619946000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 614046500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1234360250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7945647607 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7945647607 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7945262107 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7945262107 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619637750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8560401357 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9180406857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619946000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8559308607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9179622357 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619637750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8560401357 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9180406857 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 343871250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166656947250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167000818500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619946000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8559308607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9179622357 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 344358750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657044750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167001403500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702635150 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702635150 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 343871250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582400 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703453650 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 344358750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359679900 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183704038650 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses @@ -1198,23 +1240,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58539.230043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62672.418187 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60524.447331 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58568.351441 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62600.316036 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60504.889466 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59374.304918 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59374.304918 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59371.424247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59371.424247 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58568.351441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59591.933601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59521.360858 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1225,12 +1267,12 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 626139 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 511.876590 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.876590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1262,16 +1304,16 @@ system.cpu.dcache.demand_misses::cpu.data 618199 # n system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses system.cpu.dcache.overall_misses::total 618199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416240000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5416240000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11622215515 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11622215515 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158376750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158376750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17038455515 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17038455515 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17038455515 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17038455515 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5415523000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5415523000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621830515 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11621830515 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158390000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158390000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17037353515 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17037353515 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17037353515 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17037353515 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) @@ -1294,16 +1336,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14715.884082 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14715.884082 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46461.914150 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46461.914150 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.779554 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.779554 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27561.441405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27561.441405 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.935999 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.935999 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46460.375042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46460.375042 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13910.943264 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13910.943264 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27559.658807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27559.658807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27559.658807 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1324,22 +1366,22 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 618199 system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069989485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069989485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135550250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135550250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747826485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15747826485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747826485 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15747826485 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069604485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069604485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135564000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135564000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15746722485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15746722485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15746722485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15746722485 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050737750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050737750 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284890100 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284890100 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses @@ -1350,16 +1392,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12709.648584 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12709.648584 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44254.290452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44254.290452 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.992974 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.992974 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12707.695066 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12707.695066 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44252.751344 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44252.751344 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11906.200597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11906.200597 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25471.931344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25471.931344 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1367,9 +1409,9 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965193 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454584 # Transaction distribution +system.cpu.toL2Bus.throughput 52965212 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454596 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution @@ -1377,23 +1419,23 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749349 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749353 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755188 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614885 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614893 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138419049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138419049 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138419097 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138419097 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008582500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3008588500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295439000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295451750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534381165 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534384415 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index 4f02f4af8..20c714ee4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -14,6 +14,7 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l atags_addr=256 boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename= @@ -22,9 +23,16 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false init_param=0 kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 +load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 @@ -33,7 +41,9 @@ multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true +phys_addr_range_64=40 readfile=tests/halt.sh +reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -86,13 +96,14 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 fastmem=false @@ -100,6 +111,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -157,10 +169,35 @@ hit_latency=2 sequential_access=false size=32768 +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + [system.cpu0.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.dtb.walker @@ -168,6 +205,7 @@ walker=system.cpu0.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -215,24 +253,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu0.itb.walker @@ -240,6 +314,7 @@ walker=system.cpu0.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -250,13 +325,14 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 fastmem=false @@ -264,6 +340,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -284,10 +361,34 @@ tracer=system.cpu1.tracer width=1 workload= +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu1.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.dtb.walker @@ -295,6 +396,7 @@ walker=system.cpu1.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -302,24 +404,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu1.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu1.itb.walker @@ -327,6 +464,7 @@ walker=system.cpu1.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -941,7 +1079,7 @@ system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr index 38a425305..08406cf3a 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr @@ -11,8 +11,12 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index 312a2d840..f0d337e74 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,8 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:32:17 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:10:38 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x56d2400 0x56d2400 + 0: system.cpu1.isa: ISA system set to: 0x56d2400 0x56d2400 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index af2c3099c..9511fe4d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,29 +1,29 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.332810 # Number of seconds simulated -sim_ticks 2332810264000 # Number of ticks simulated -final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2332810269000 # Number of ticks simulated +final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1583722 # Simulator instruction rate (inst/s) -host_op_rate 2036569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61158803315 # Simulator tick rate (ticks/s) -host_mem_usage 399324 # Number of bytes of host memory used -host_seconds 38.14 # Real time elapsed on the host -sim_insts 60408639 # Number of instructions simulated -sim_ops 77681819 # Number of ops (including micro ops) simulated +host_inst_rate 1221068 # Simulator instruction rate (inst/s) +host_op_rate 1570218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47154151043 # Simulator tick rate (ticks/s) +host_mem_usage 421264 # Number of bytes of host memory used +host_seconds 49.47 # Real time elapsed on the host +sim_insts 60408649 # Number of instructions simulated +sim_ops 77681829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 492704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6494800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 492744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6494808 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 212416 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 2577132 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450716 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 492704 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 121450764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 492744 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 212416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1405784 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 1610060 # Number of bytes written to this memory @@ -31,11 +31,11 @@ system.physmem.bytes_written::total 6718884 # Nu system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 101515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101517 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 3319 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 40278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118198 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 351446 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 402515 # Number of write requests responded to by this memory @@ -43,14 +43,14 @@ system.physmem.num_writes::total 811821 # Nu system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2784110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2784113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 91056 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1104733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211223 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 91056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1587373 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 602614 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 690180 # Write bandwidth from this memory (bytes/s) @@ -59,11 +59,11 @@ system.physmem.bw_total::writebacks 1587373 # To system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3386724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3386727 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942166 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -76,23 +76,23 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969561 # Throughput (bytes/s) -system.membus.data_through_bus 130566366 # Total data (bytes) +system.membus.throughput 55969581 # Throughput (bytes/s) +system.membus.data_through_bus 130566414 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62242 # number of replacements -system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.tagsinuse 50006.300115 # Cycle average of tags in use system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571374 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495752 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy @@ -115,38 +115,38 @@ system.l2c.tags.tag_accesses 17104735 # Nu system.l2c.tags.data_accesses 17104735 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 196972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 473132 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 196968 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 4875 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 365737 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169792 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 365739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 169796 # number of ReadReq hits system.l2c.ReadReq_hits::total 1224842 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 592682 # number of Writeback hits system.l2c.Writeback_hits::total 592682 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63335 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50403 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 63334 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 50404 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 9005 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 473134 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 260307 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 473132 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 260302 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 4875 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 365737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 220195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 365739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 220200 # number of demand (read+write) hits system.l2c.demand_hits::total 1338580 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 9005 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3277 # number of overall hits -system.l2c.overall_hits::cpu0.inst 473134 # number of overall hits -system.l2c.overall_hits::cpu0.data 260307 # number of overall hits +system.l2c.overall_hits::cpu0.inst 473132 # number of overall hits +system.l2c.overall_hits::cpu0.data 260302 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 4875 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2050 # number of overall hits -system.l2c.overall_hits::cpu1.inst 365737 # number of overall hits -system.l2c.overall_hits::cpu1.data 220195 # number of overall hits +system.l2c.overall_hits::cpu1.inst 365739 # number of overall hits +system.l2c.overall_hits::cpu1.data 220200 # number of overall hits system.l2c.overall_hits::total 1338580 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses @@ -177,65 +177,65 @@ system.l2c.overall_misses::cpu1.data 41049 # nu system.l2c.overall_misses::total 153953 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 9007 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3280 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 480419 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 202779 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 480417 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 202775 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 4875 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2050 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 369056 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173857 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 369058 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 173861 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1245323 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 592682 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 592682 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1532 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1413 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 159823 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 87387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 159822 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 87388 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247210 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 9007 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 480419 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 362602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 480417 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 362597 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 4875 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2050 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 369056 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 261244 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 369058 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 261249 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1492533 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 9007 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3280 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 480419 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 362602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 480417 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 362597 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 4875 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2050 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 369056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 261244 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 369058 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 261249 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1492533 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.015164 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028638 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.008993 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.023381 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992167 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990092 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.603718 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.423221 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.603722 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.423216 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.539913 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.015164 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.282114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282118 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.008993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157129 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.157126 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.103149 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.015164 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.282114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.282118 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.008993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157129 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.157126 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.103149 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -254,87 +254,129 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119250 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137913994 # Total data (bytes) +system.toL2Bus.throughput 59119271 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137914042 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 48895252 # Throughput (bytes/s) system.iobus.data_through_bus 114063346 # Total data (bytes) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7929205 # DTB read hits -system.cpu0.dtb.read_misses 6441 # DTB read misses -system.cpu0.dtb.write_hits 6437098 # DTB write hits -system.cpu0.dtb.write_misses 1932 # DTB write misses -system.cpu0.dtb.flush_tlb 1168 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7929199 # DTB read hits +system.cpu0.dtb.read_misses 6444 # DTB read misses +system.cpu0.dtb.write_hits 6437089 # DTB write hits +system.cpu0.dtb.write_misses 1929 # DTB write misses +system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5576 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5568 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7935646 # DTB read accesses -system.cpu0.dtb.write_accesses 6439030 # DTB write accesses +system.cpu0.dtb.read_accesses 7935643 # DTB read accesses +system.cpu0.dtb.write_accesses 6439018 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14366303 # DTB hits +system.cpu0.dtb.hits 14366288 # DTB hits system.cpu0.dtb.misses 8373 # DTB misses -system.cpu0.dtb.accesses 14374676 # DTB accesses -system.cpu0.itb.inst_hits 32543253 # ITB inst hits +system.cpu0.dtb.accesses 14374661 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 32543256 # ITB inst hits system.cpu0.itb.inst_misses 3703 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1168 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2636 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32546956 # ITB inst accesses -system.cpu0.itb.hits 32543253 # DTB hits +system.cpu0.itb.inst_accesses 32546959 # ITB inst accesses +system.cpu0.itb.hits 32543256 # DTB hits system.cpu0.itb.misses 3703 # DTB misses -system.cpu0.itb.accesses 32546956 # DTB accesses -system.cpu0.numCycles 4633633401 # number of cpu cycles simulated +system.cpu0.itb.accesses 32546959 # DTB accesses +system.cpu0.numCycles 4633654699 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31998091 # Number of instructions committed -system.cpu0.committedOps 41901593 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37065495 # Number of integer alu accesses +system.cpu0.committedInsts 31998107 # Number of instructions committed +system.cpu0.committedOps 41901559 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37244533 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses -system.cpu0.num_func_calls 1207173 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4285544 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37065495 # number of integer instructions +system.cpu0.num_func_calls 1207172 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4285554 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37244533 # number of integer instructions system.cpu0.num_fp_insts 5364 # number of float instructions -system.cpu0.num_int_register_reads 188704279 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39536975 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192529528 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39716026 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu0.num_mem_refs 15013057 # number of memory refs +system.cpu0.num_mem_refs 15013044 # number of memory refs system.cpu0.num_load_insts 8304661 # Number of load instructions -system.cpu0.num_store_insts 6708396 # Number of store instructions -system.cpu0.num_idle_cycles 4555668120.247687 # Number of idle cycles -system.cpu0.num_busy_cycles 77965280.752313 # Number of busy cycles -system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles +system.cpu0.num_store_insts 6708383 # Number of store instructions +system.cpu0.num_idle_cycles 4553702806.473283 # Number of idle cycles +system.cpu0.num_busy_cycles 79951892.526717 # Number of busy cycles +system.cpu0.not_idle_fraction 0.017255 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.982745 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy +system.cpu0.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.509134 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.169458 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868182 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131190 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id @@ -344,32 +386,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 62285702 # Number of tag accesses system.cpu0.icache.tags.data_accesses 62285702 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 32064740 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28518758 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32064735 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28518763 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 32064740 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28518758 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60583498 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32064735 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28518763 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 32064740 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28518758 # number of overall hits system.cpu0.icache.overall_hits::total 60583498 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 481297 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 369805 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 481295 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 369807 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 481297 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 369805 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 481295 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 369807 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 851102 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 481297 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 369805 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 481295 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 369807 # number of overall misses system.cpu0.icache.overall_misses::total 851102 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32546032 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 28888568 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32546035 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 28888565 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32546032 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 28888568 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 32546035 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 28888565 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32546032 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 28888568 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32546035 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 28888565 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014788 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012801 # miss rate for ReadReq accesses @@ -390,13 +432,13 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 623334 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628286 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.avg_refs 37.875190 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298836 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698194 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -405,73 +447,73 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97632366 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97632366 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5776861 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4185204 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 97632374 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97632374 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6995580 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6184442 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13180022 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5776847 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4185218 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 9962065 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139289 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96747 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139292 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96744 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145935 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101283 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145938 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101280 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12772451 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10369634 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23142085 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12772451 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10369634 # number of overall hits -system.cpu0.dcache.overall_hits::total 23142085 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 196132 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 169321 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12772427 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10369660 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23142087 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12772427 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10369660 # number of overall hits +system.cpu0.dcache.overall_hits::total 23142087 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 196128 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 169325 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 365453 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 161355 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 88800 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 161354 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 88801 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 250155 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6647 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 357487 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 258121 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 357482 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 258126 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 615608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 357487 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 258121 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 357482 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 258126 # number of overall misses system.cpu0.dcache.overall_misses::total 615608 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353751 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13545473 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938216 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274004 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7191708 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353767 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13545475 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5938201 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4274019 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10212220 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145936 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101283 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145939 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101280 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145935 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101283 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145938 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101280 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13129938 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10627755 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23757693 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13129938 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10627755 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23757693 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027272 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026649 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13129909 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10627786 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23757695 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13129909 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10627786 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23757695 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027271 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020777 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024496 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045547 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045546 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044787 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027227 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024287 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024288 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027227 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024287 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024288 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -484,68 +526,110 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.writebacks::writebacks 592682 # number of writebacks system.cpu0.dcache.writebacks::total 592682 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7038595 # DTB read hits -system.cpu1.dtb.read_misses 4223 # DTB read misses -system.cpu1.dtb.write_hits 4778906 # DTB write hits -system.cpu1.dtb.write_misses 1249 # DTB write misses -system.cpu1.dtb.flush_tlb 1166 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7038606 # DTB read hits +system.cpu1.dtb.read_misses 4220 # DTB read misses +system.cpu1.dtb.write_hits 4778915 # DTB write hits +system.cpu1.dtb.write_misses 1252 # DTB write misses +system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2949 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2946 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 82 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 80 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7042818 # DTB read accesses -system.cpu1.dtb.write_accesses 4780155 # DTB write accesses +system.cpu1.dtb.read_accesses 7042826 # DTB read accesses +system.cpu1.dtb.write_accesses 4780167 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11817501 # DTB hits +system.cpu1.dtb.hits 11817521 # DTB hits system.cpu1.dtb.misses 5472 # DTB misses -system.cpu1.dtb.accesses 11822973 # DTB accesses -system.cpu1.itb.inst_hits 28886892 # ITB inst hits +system.cpu1.dtb.accesses 11822993 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 28886889 # ITB inst hits system.cpu1.itb.inst_misses 2463 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1166 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1597 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1658 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28889355 # ITB inst accesses -system.cpu1.itb.hits 28886892 # DTB hits +system.cpu1.itb.inst_accesses 28889352 # ITB inst accesses +system.cpu1.itb.hits 28886889 # DTB hits system.cpu1.itb.misses 2463 # DTB misses -system.cpu1.itb.accesses 28889355 # DTB accesses -system.cpu1.numCycles 4279988156 # number of cpu cycles simulated +system.cpu1.itb.accesses 28889352 # DTB accesses +system.cpu1.numCycles 4277971820 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28410548 # Number of instructions committed -system.cpu1.committedOps 35780226 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31730110 # Number of integer alu accesses +system.cpu1.committedInsts 28410542 # Number of instructions committed +system.cpu1.committedOps 35780270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 31886228 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses -system.cpu1.num_func_calls 928835 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3656569 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31730110 # number of integer instructions +system.cpu1.num_func_calls 928836 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3656561 # number of instructions that are conditional controls +system.cpu1.num_int_insts 31886228 # number of integer instructions system.cpu1.num_fp_insts 4905 # number of float instructions -system.cpu1.num_int_register_reads 160619995 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34566633 # number of times the integer registers were written +system.cpu1.num_int_register_reads 163367229 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34722740 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu1.num_mem_refs 12348580 # number of memory refs -system.cpu1.num_load_insts 7334866 # Number of load instructions -system.cpu1.num_store_insts 5013714 # Number of store instructions -system.cpu1.num_idle_cycles 4217686174.280304 # Number of idle cycles -system.cpu1.num_busy_cycles 62301981.719696 # Number of busy cycles +system.cpu1.num_mem_refs 12348595 # number of memory refs +system.cpu1.num_load_insts 7334868 # Number of load instructions +system.cpu1.num_store_insts 5013727 # Number of store instructions +system.cpu1.num_idle_cycles 4215699127.014197 # Number of idle cycles +system.cpu1.num_busy_cycles 62272692.985803 # Number of busy cycles system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 5c3361f47..367b15c5e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -146,13 +149,14 @@ predType=tournament [system.cpu.checker] type=O3Checker -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu dtb=system.cpu.checker.dtb eventq_index=0 exitOnError=false @@ -160,6 +164,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -176,10 +181,35 @@ updateOnError=true warnOnlyOnLoadError=true workload=system.cpu.workload +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[9] + [system.cpu.checker.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.dtb.walker @@ -187,32 +217,69 @@ walker=system.cpu.checker.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[7] [system.cpu.checker.isa] type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[8] [system.cpu.checker.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.itb.walker @@ -220,9 +287,10 @@ walker=system.cpu.checker.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[6] [system.cpu.checker.tracer] type=ExeTracer @@ -263,10 +331,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -274,6 +367,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -628,24 +722,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -653,6 +783,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -701,7 +832,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index dc275e0b8..9a11b77d6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:22 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:05:52 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second + 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0 + 0: system.cpu.isa: ISA system set to: 0 0x5d826c0 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 16981000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 8e11038e3..783b95f78 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16981000 # Number of ticks simulated final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35724 # Simulator instruction rate (inst/s) -host_op_rate 44574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132106037 # Simulator tick rate (ticks/s) -host_mem_usage 247896 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 39940 # Simulator instruction rate (inst/s) +host_op_rate 49834 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147693403 # Simulator tick rate (ticks/s) +host_mem_usage 267784 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,27 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -248,6 +269,27 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -273,6 +315,27 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 5742 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -294,6 +357,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -366,7 +450,7 @@ system.cpu.rename.ROBFullEvents 2 # Nu system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed @@ -383,7 +467,7 @@ system.cpu.iq.iqNonSpecInstsAdded 49 # Nu system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle @@ -570,7 +654,7 @@ system.cpu.ipc_total 0.135177 # IP system.cpu.int_regfile_reads 39210 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2977 # number of misc regfile reads +system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 9b066fde0..ecd158ad5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,7 +42,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true @@ -67,6 +68,7 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fetchBufferSize=64 @@ -85,6 +87,7 @@ interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -179,10 +182,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -190,6 +218,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -544,24 +573,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -569,6 +634,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -617,7 +683,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 5df86194c..c3c8ec2e1 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:21 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:05:41 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x578c380 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 16981000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 3ffee0645..20f1d1a3b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16981000 # Number of ticks simulated final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34743 # Simulator instruction rate (inst/s) -host_op_rate 43351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 128481440 # Simulator tick rate (ticks/s) -host_mem_usage 246872 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 45620 # Simulator instruction rate (inst/s) +host_op_rate 56920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 168691831 # Simulator tick rate (ticks/s) +host_mem_usage 267756 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -227,6 +227,27 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -248,6 +269,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -321,7 +363,7 @@ system.cpu.rename.ROBFullEvents 2 # Nu system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed @@ -338,7 +380,7 @@ system.cpu.iq.iqNonSpecInstsAdded 49 # Nu system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle @@ -525,7 +567,7 @@ system.cpu.ipc_total 0.135177 # IP system.cpu.int_regfile_reads 39210 # number of integer regfile reads system.cpu.int_regfile_writes 7985 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2977 # number of misc regfile reads +system.cpu.misc_regfile_reads 3239 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 1158c75dc..baee5cb0e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=checker dtb interrupts isa itb tracer workload +children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=system.cpu.checker clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -79,13 +82,14 @@ icache_port=system.membus.slave[1] [system.cpu.checker] type=DummyChecker -children=dtb isa itb tracer +children=dstage2_mmu dtb isa istage2_mmu itb tracer checker=Null clk_domain=system.cpu_clk_domain cpu_id=-1 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.checker.dstage2_mmu dtb=system.cpu.checker.dtb eventq_index=0 exitOnError=false @@ -93,6 +97,7 @@ function_trace=false function_trace_start=0 interrupts=Null isa=system.cpu.checker.isa +istage2_mmu=system.cpu.checker.istage2_mmu itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -109,10 +114,34 @@ updateOnError=false warnOnlyOnLoadError=true workload=system.cpu.workload +[system.cpu.checker.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb +tlb=system.cpu.checker.dtb + +[system.cpu.checker.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker + +[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + [system.cpu.checker.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.dtb.walker @@ -120,6 +149,7 @@ walker=system.cpu.checker.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -127,24 +157,59 @@ sys=system type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.checker.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb +tlb=system.cpu.checker.itb + +[system.cpu.checker.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker + +[system.cpu.checker.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system [system.cpu.checker.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.checker.itb.walker @@ -152,6 +217,7 @@ walker=system.cpu.checker.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system @@ -159,10 +225,35 @@ sys=system type=ExeTracer eventq_index=0 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -170,6 +261,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -182,24 +274,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -207,6 +335,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -250,7 +379,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 7509c2dae..c5ba01efb 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,11 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:32 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:13 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second + 0: system.cpu.checker.isa: ISA system set to: 0 0x4499a00 + 0: system.cpu.isa: ISA system set to: 0 0x4499a00 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 4b1e74a91..a171618e9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61907 # Simulator instruction rate (inst/s) -host_op_rate 77238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38693079 # Simulator tick rate (ticks/s) -host_mem_usage 237008 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 147367 # Simulator instruction rate (inst/s) +host_op_rate 183813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92059834 # Simulator tick rate (ticks/s) +host_mem_usage 256900 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9251001568 # Th system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -85,6 +127,27 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -106,6 +169,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -138,7 +222,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_reads 25360 # number of times the integer registers were read system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 8e0b67b72..02f18b1ff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges= memories=system.physmem @@ -41,13 +42,14 @@ voltage_domain=system.voltage_domain [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 fastmem=false @@ -55,6 +57,7 @@ function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -77,10 +80,35 @@ workload=system.cpu.workload dcache_port=system.membus.slave[2] icache_port=system.membus.slave[1] +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[6] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -88,6 +116,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -100,24 +129,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.membus.slave[5] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -125,6 +190,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -168,7 +234,7 @@ system=system use_default_range=false width=8 master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.physmem] type=SimpleMemory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 618f6d613..380d567ec 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:32 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:03 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5df7a00 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index ea0a0e09c..3aa0b8e66 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81917 # Simulator instruction rate (inst/s) -host_op_rate 102184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51187301 # Simulator tick rate (ticks/s) -host_mem_usage 236980 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 135849 # Simulator instruction rate (inst/s) +host_op_rate 169454 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84871687 # Simulator tick rate (ticks/s) +host_mem_usage 256868 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -39,6 +39,27 @@ system.membus.throughput 9251001568 # Th system.membus.data_through_bus 26555 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -60,6 +81,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -93,7 +135,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_reads 25360 # number of times the integer registers were read system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index bae9efedf..b833e8e3a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -41,19 +42,21 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -105,10 +108,35 @@ hit_latency=2 sequential_access=false size=262144 +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + [system.cpu.dtb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.dtb.walker @@ -116,6 +144,7 @@ walker=system.cpu.dtb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,24 +192,60 @@ eventq_index=0 type=ArmISA eventq_index=0 fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 id_isar3=17899825 id_isar4=268501314 id_isar5=0 -id_mmfr0=3 +id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 -id_mmfr3=4027589137 +id_mmfr3=34611729 id_pfr0=49 -id_pfr1=1 -midr=890224640 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB children=walker eventq_index=0 +is_stage2=false size=64 walker=system.cpu.itb.walker @@ -188,6 +253,7 @@ walker=system.cpu.itb.walker type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 +is_stage2=false num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -236,7 +302,7 @@ system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 6834abec2..16e7e5d49 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:24:06 -gem5 started Jan 22 2014 17:30:42 +gem5 compiled Jan 23 2014 12:08:08 +gem5 started Jan 23 2014 17:06:24 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second + 0: system.cpu.isa: ISA system set to: 0 0x5fe9040 info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 25969000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index a3962cb85..47befeaab 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84539 # Simulator instruction rate (inst/s) -host_op_rate 105013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 480681007 # Simulator tick rate (ticks/s) -host_mem_usage 245716 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 122117 # Simulator instruction rate (inst/s) +host_op_rate 151672 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 694181161 # Simulator tick rate (ticks/s) +host_mem_usage 266760 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -45,6 +45,27 @@ system.membus.reqLayer0.utilization 1.3 # La system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -66,6 +87,27 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -99,7 +141,7 @@ system.cpu.num_func_calls 203 # nu system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 28656 # number of times the integer registers were read +system.cpu.num_int_register_reads 28821 # number of times the integer registers were read system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |