diff options
24 files changed, 366 insertions, 192 deletions
diff --git a/src/arch/alpha/freebsd/system.cc b/src/arch/alpha/freebsd/system.cc index db0be29ab..f666de604 100644 --- a/src/arch/alpha/freebsd/system.cc +++ b/src/arch/alpha/freebsd/system.cc @@ -76,8 +76,9 @@ FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc) Addr ppc_vaddr = 0; Addr timer_vaddr = 0; - ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1); - timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2); + assert(NumArgumentRegs >= 3); + ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg[1]); + timer_vaddr = (Addr)tc->readIntReg(ArgumentReg[2]); virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency); virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY); diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index a267ac034..7dc7e5151 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -156,14 +156,12 @@ namespace AlphaISA const int ReturnAddressReg = 26; const int ReturnValueReg = 0; const int FramePointerReg = 15; - const int ArgumentReg0 = 16; - const int ArgumentReg1 = 17; - const int ArgumentReg2 = 18; - const int ArgumentReg3 = 19; - const int ArgumentReg4 = 20; - const int ArgumentReg5 = 21; + + const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; + const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); + const int SyscallNumReg = ReturnValueReg; - const int SyscallPseudoReturnReg = ArgumentReg4; + const int SyscallPseudoReturnReg = ArgumentReg[4]; const int SyscallSuccessReg = 19; const int LogVMPageSize = 13; // 8K bytes diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index 5ab6957a3..5d4403553 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -74,10 +74,10 @@ namespace MipsISA const int ReturnValueReg = 2; const int ReturnValueReg1 = 2; const int ReturnValueReg2 = 3; - const int ArgumentReg0 = 4; - const int ArgumentReg1 = 5; - const int ArgumentReg2 = 6; - const int ArgumentReg3 = 7; + + const int ArgumentReg[] = {4, 5, 6, 7}; + const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); + const int KernelReg0 = 26; const int KernelReg1 = 27; const int GlobalPointerReg = 28; @@ -87,7 +87,7 @@ namespace MipsISA const int SyscallNumReg = ReturnValueReg1; const int SyscallPseudoReturnReg = ReturnValueReg2; - const int SyscallSuccessReg = ArgumentReg3; + const int SyscallSuccessReg = ArgumentReg[3]; const int LogVMPageSize = 13; // 8K bytes const int VMPageSize = (1 << LogVMPageSize); diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 8b3ec36a6..0edbdec4b 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -69,14 +69,12 @@ namespace SparcISA const int ReturnAddressReg = 31; // post call, precall is 15 const int ReturnValueReg = 8; // Post return, 24 is pre-return. const int FramePointerReg = 30; - const int ArgumentReg0 = 8; - const int ArgumentReg1 = 9; - const int ArgumentReg2 = 10; - const int ArgumentReg3 = 11; - const int ArgumentReg4 = 12; - const int ArgumentReg5 = 13; + + const int ArgumentReg[] = {8, 9, 10, 11, 12, 13}; + const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); + // Some OS syscall use a second register (o1) to return a second value - const int SyscallPseudoReturnReg = ArgumentReg1; + const int SyscallPseudoReturnReg = ArgumentReg[1]; //XXX These numbers are bogus const int MaxInstSrcRegs = 8; diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 0776694ec..bc950301a 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -399,8 +399,9 @@ Sparc64LiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler64, spillSize); //Set up the thread context to start running the process - threadContexts[0]->setIntReg(ArgumentReg0, argc); - threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + assert(NumArgumentRegs >= 2); + threadContexts[0]->setIntReg(ArgumentReg[0], argc); + threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base); threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); Addr prog_entry = objFile->entryPoint(); @@ -627,8 +628,9 @@ Sparc32LiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler32, spillSize); //Set up the thread context to start running the process - //threadContexts[0]->setIntReg(ArgumentReg0, argc); - //threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + //assert(NumArgumentRegs >= 2); + //threadContexts[0]->setIntReg(ArgumentReg[0], argc); + //threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base); threadContexts[0]->setIntReg(StackPointerReg, stack_min); uint32_t prog_entry = objFile->entryPoint(); diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh index f90d6670e..ae03d176e 100644 --- a/src/arch/x86/insts/microldstop.hh +++ b/src/arch/x86/insts/microldstop.hh @@ -96,6 +96,62 @@ namespace X86ISA std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + template<class Context, class MemType> + Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const + { + Fault fault = NoFault; + int size = dataSize; + Addr alignedEA = EA & ~(dataSize - 1); + if (EA != alignedEA) + size *= 2; + switch(size) + { + case 1: + fault = xc->read(alignedEA, (uint8_t&)Mem, flags); + break; + case 2: + fault = xc->read(alignedEA, (uint16_t&)Mem, flags); + break; + case 4: + fault = xc->read(alignedEA, (uint32_t&)Mem, flags); + break; + case 8: + fault = xc->read(alignedEA, (uint64_t&)Mem, flags); + break; + default: + panic("Bad operand size %d!\n", size); + } + return fault; + } + + template<class Context, class MemType> + Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const + { + Fault fault = NoFault; + int size = dataSize; + Addr alignedEA = EA & ~(dataSize - 1); + if (EA != alignedEA) + size *= 2; + switch(size) + { + case 1: + fault = xc->write((uint8_t&)Mem, alignedEA, flags, 0); + break; + case 2: + fault = xc->write((uint16_t&)Mem, alignedEA, flags, 0); + break; + case 4: + fault = xc->write((uint32_t&)Mem, alignedEA, flags, 0); + break; + case 8: + fault = xc->write((uint64_t&)Mem, alignedEA, flags, 0); + break; + default: + panic("Bad operand size %d!\n", size); + } + return fault; + } }; } diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index c81aa666d..3b51f9d73 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -407,9 +407,29 @@ 0x7: iret(); } 0x1A: decode OPCODE_OP_BOTTOM3 { - 0x0: group2_Eb_1(); - 0x1: group2_Ev_1(); format Inst { + //0x0: group2_Eb_1(); + 0x0: decode MODRM_REG { + 0x0: ROL_1(Eb); + 0x1: ROR_1(Eb); + 0x2: RCL_1(Eb); + 0x3: RCR_1(Eb); + 0x4: SAL_1(Eb); + 0x5: SHR_1(Eb); + 0x6: SAL_1(Eb); + 0x7: SAR_1(Eb); + } + //0x1: group2_Ev_1(); + 0x1: decode MODRM_REG { + 0x0: ROL_1(Ev); + 0x1: ROR_1(Ev); + 0x2: RCL_1(Ev); + 0x3: RCR_1(Ev); + 0x4: SAL_1(Ev); + 0x5: SHR_1(Ev); + 0x6: SAL_1(Ev); + 0x7: SAR_1(Ev); + } //0x2: group2_Eb_Cl(); 0x2: decode MODRM_REG { 0x0: ROL(Eb,rCb); @@ -497,7 +517,7 @@ 0x6: decode MODRM_REG { 0x0: Inst::TEST(Eb,Iz); 0x1: Inst::TEST(Eb,Iz); - 0x2: not_Eb(); + 0x2: Inst::NOT(Eb); 0x3: Inst::NEG(Eb); 0x4: mul_Eb(); 0x5: imul_Eb(); @@ -508,7 +528,7 @@ 0x7: decode MODRM_REG { 0x0: Inst::TEST(Ev,Iz); 0x1: Inst::TEST(Ev,Iz); - 0x2: not_Ev(); + 0x2: Inst::NOT(Ev); 0x3: Inst::NEG(Ev); 0x4: mul_Ev(); 0x5: imul_Ev(); diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py index e104eaeed..7e5578a3c 100644 --- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -77,9 +77,9 @@ def macroop ADD_P_I { rdip t7 limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp add t1, t1, t2 - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop ADD_M_R @@ -92,9 +92,9 @@ def macroop ADD_M_R def macroop ADD_P_R { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp add t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop ADD_R_M @@ -106,7 +106,7 @@ def macroop ADD_R_M def macroop ADD_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp add reg, reg, t1 }; @@ -130,7 +130,7 @@ def macroop SUB_R_M def macroop SUB_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp sub reg, reg, t1 }; @@ -146,9 +146,9 @@ def macroop SUB_P_I { rdip t7 limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp sub t1, t1, t2 - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop SUB_M_R @@ -161,9 +161,9 @@ def macroop SUB_M_R def macroop SUB_P_R { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp sub t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop ADC_R_R @@ -189,9 +189,9 @@ def macroop ADC_P_I { rdip t7 limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp adc t1, t1, t2 - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop ADC_M_R @@ -204,9 +204,9 @@ def macroop ADC_M_R def macroop ADC_P_R { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp adc t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop ADC_R_M @@ -218,7 +218,7 @@ def macroop ADC_R_M def macroop ADC_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp adc reg, reg, t1 }; @@ -242,7 +242,7 @@ def macroop SBB_R_M def macroop SBB_R_P { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp sbb reg, reg, t1 }; @@ -258,9 +258,9 @@ def macroop SBB_P_I { rdip t7 limm t2, imm - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp sbb t1, t1, t2 - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop SBB_M_R @@ -273,9 +273,9 @@ def macroop SBB_M_R def macroop SBB_P_R { rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, ds, [0, t0, t7], disp sbb t1, t1, reg - st t1, ds, [scale, index, base], disp + st t1, ds, [0, t0, t7], disp }; def macroop NEG_R diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py index 04737edd1..bbc15f8fa 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/logical.py @@ -221,12 +221,27 @@ def macroop AND_P_R and t1, t1, reg st t1, ds, [scale, index, base], disp }; + +def macroop NOT_R +{ + limm t1, -1 + xor reg, reg, t1 +}; + +def macroop NOT_M +{ + limm t1, -1 + ld t2, ds, [scale, index, base], disp + xor t2, t2, t1 + st t2, ds, [scale, index, base], disp +}; + +def macroop NOT_P +{ + limm t1, -1 + rdip t7 + ld t2, ds, [0, t0, t7], disp + xor t2, t2, t1 + st t2, ds, [0, t0, t7], disp +}; ''' -#let {{ -#microcodeString = ''' -# def macroop NOT -# { -# Xor reg reg "0xFFFFFFFFFFFFFFFFULL" -# }; -#''' -#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py index 844288dbe..538e641ab 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py @@ -74,6 +74,26 @@ def macroop ROL_P_I st t1, ds, [0, t0, t7], disp }; +def macroop ROL_1_R +{ + roli reg, reg, 1 +}; + +def macroop ROL_1_M +{ + ld t1, ds, [scale, index, base], disp + roli t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop ROL_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + roli t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop ROL_R_R { rol reg, reg, regm @@ -114,15 +134,35 @@ def macroop ROR_P_I st t1, ds, [0, t0, t7], disp }; +def macroop ROR_1_R +{ + rori reg, reg, 1 +}; + +def macroop ROR_1_M +{ + ld t1, ds, [scale, index, base], disp + rori t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop ROR_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + rori t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop ROR_R_R { - rori reg, reg, regm + ror reg, reg, regm }; def macroop ROR_M_R { ld t1, ds, [scale, index, base], disp - rori t1, t1, reg + ror t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -130,7 +170,7 @@ def macroop ROR_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - rori t1, t1, reg + ror t1, t1, reg st t1, ds, [0, t0, t7], disp }; @@ -154,15 +194,35 @@ def macroop RCL_P_I st t1, ds, [0, t0, t7], disp }; +def macroop RCL_1_R +{ + rcli reg, reg, 1 +}; + +def macroop RCL_1_M +{ + ld t1, ds, [scale, index, base], disp + rcli t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop RCL_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + rcli t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop RCL_R_R { - rcli reg, reg, regm + rcl reg, reg, regm }; def macroop RCL_M_R { ld t1, ds, [scale, index, base], disp - rcli t1, t1, reg + rcl t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -170,7 +230,7 @@ def macroop RCL_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - rcli t1, t1, reg + rcl t1, t1, reg st t1, ds, [0, t0, t7], disp }; @@ -194,15 +254,35 @@ def macroop RCR_P_I st t1, ds, [0, t0, t7], disp }; +def macroop RCR_1_R +{ + rcri reg, reg, 1 +}; + +def macroop RCR_1_M +{ + ld t1, ds, [scale, index, base], disp + rcri t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop RCR_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + rcri t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop RCR_R_R { - rcri reg, reg, regm + rcr reg, reg, regm }; def macroop RCR_M_R { ld t1, ds, [scale, index, base], disp - rcri t1, t1, reg + rcr t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -210,7 +290,7 @@ def macroop RCR_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - rcri t1, t1, reg + rcr t1, t1, reg st t1, ds, [0, t0, t7], disp }; ''' diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py index b9c07b0ba..64eab3edc 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py +++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py @@ -74,15 +74,35 @@ def macroop SAL_P_I st t1, ds, [0, t0, t7], disp }; +def macroop SAL_1_R +{ + slli reg, reg, 1 +}; + +def macroop SAL_1_M +{ + ld t1, ds, [scale, index, base], disp + slli t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop SAL_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + slli t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop SAL_R_R { - slli reg, reg, regm + sll reg, reg, regm }; def macroop SAL_M_R { ld t1, ds, [scale, index, base], disp - slli t1, t1, reg + sll t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -90,7 +110,7 @@ def macroop SAL_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - slli t1, t1, reg + sll t1, t1, reg st t1, ds, [0, t0, t7], disp }; @@ -114,15 +134,35 @@ def macroop SHR_P_I st t1, ds, [0, t0, t7], disp }; +def macroop SHR_1_R +{ + srli reg, reg, 1 +}; + +def macroop SHR_1_M +{ + ld t1, ds, [scale, index, base], disp + srli t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop SHR_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + srli t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop SHR_R_R { - srli reg, reg, regm + srl reg, reg, regm }; def macroop SHR_M_R { ld t1, ds, [scale, index, base], disp - srli t1, t1, reg + srl t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -130,7 +170,7 @@ def macroop SHR_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - srli t1, t1, reg + srl t1, t1, reg st t1, ds, [0, t0, t7], disp }; @@ -154,15 +194,35 @@ def macroop SAR_P_I st t1, ds, [0, t0, t7], disp }; +def macroop SAR_1_R +{ + srai reg, reg, 1 +}; + +def macroop SAR_1_M +{ + ld t1, ds, [scale, index, base], disp + srai t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop SAR_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + srai t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop SAR_R_R { - srai reg, reg, regm + sra reg, reg, regm }; def macroop SAR_M_R { ld t1, ds, [scale, index, base], disp - srai t1, t1, reg + sra t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -170,21 +230,7 @@ def macroop SAR_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - srai t1, t1, reg + sra t1, t1, reg st t1, ds, [0, t0, t7], disp }; ''' -#let {{ -# class SAL(Inst): -# "GenFault ${new UnimpInstFault}" -# class SAR(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHL(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHR(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHLD(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHRD(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index ccf519963..18cbc6082 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -123,24 +123,9 @@ def template MicroLoadExecute {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - unsigned flags = 0; - switch(dataSize) - { - case 1: - fault = xc->read(EA, (uint8_t&)Mem, flags); - break; - case 2: - fault = xc->read(EA, (uint16_t&)Mem, flags); - break; - case 4: - fault = xc->read(EA, (uint32_t&)Mem, flags); - break; - case 8: - fault = xc->read(EA, (uint64_t&)Mem, flags); - break; - default: - panic("Bad operand size!\n"); - } + fault = read(xc, EA, Mem, 0); + int offset = EA & (dataSize - 1); + Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8); if(fault == NoFault) { @@ -167,24 +152,8 @@ def template MicroLoadInitiateAcc {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - unsigned flags = 0; - switch(dataSize) - { - case 1: - fault = xc->read(EA, (uint8_t&)Mem, flags); - break; - case 2: - fault = xc->read(EA, (uint16_t&)Mem, flags); - break; - case 4: - fault = xc->read(EA, (uint32_t&)Mem, flags); - break; - case 8: - fault = xc->read(EA, (uint64_t&)Mem, flags); - break; - default: - panic("Bad operand size!\n"); - } + int offset = EA & (dataSize - 1); + fault = read(xc, EA, Mem, offset); return fault; } @@ -201,6 +170,8 @@ def template MicroLoadCompleteAcc {{ %(op_rd)s; Mem = pkt->get<typeof(Mem)>(); + int offset = pkt->flags; + Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8); %(code)s; if(fault == NoFault) @@ -230,30 +201,13 @@ def template MicroStoreExecute {{ if(fault == NoFault) { - unsigned flags = 0; - uint64_t *res = 0; - switch(dataSize) + Mem = Mem << ((EA & (dataSize - 1)) * 8); + fault = write(xc, Mem, EA, 0); + if(fault == NoFault) { - case 1: - fault = xc->write((uint8_t&)Mem, EA, flags, res); - break; - case 2: - fault = xc->write((uint16_t&)Mem, EA, flags, res); - break; - case 4: - fault = xc->write((uint32_t&)Mem, EA, flags, res); - break; - case 8: - fault = xc->write((uint64_t&)Mem, EA, flags, res); - break; - default: - panic("Bad operand size!\n"); + %(op_wb)s; } } - if(fault == NoFault) - { - %(op_wb)s; - } return fault; } @@ -275,30 +229,13 @@ def template MicroStoreInitiateAcc {{ if(fault == NoFault) { - unsigned flags = 0; - uint64_t *res = 0; - switch(dataSize) + Mem = Mem << ((EA & (dataSize - 1)) * 8); + fault = write(xc, Mem, EA, 0); + if(fault == NoFault) { - case 1: - fault = xc->write((uint8_t&)Mem, EA, flags, res); - break; - case 2: - fault = xc->write((uint16_t&)Mem, EA, flags, res); - break; - case 4: - fault = xc->write((uint32_t&)Mem, EA, flags, res); - break; - case 8: - fault = xc->write((uint64_t&)Mem, EA, flags, res); - break; - default: - panic("Bad operand size!\n"); + %(op_wb)s; } } - if(fault == NoFault) - { - %(op_wb)s; - } return fault; } }}; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index c3f008993..bb34df7df 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -343,7 +343,7 @@ let {{ immCode = matcher.sub("imm8", code) if subtract: - secondSrc = "-op2, true" + secondSrc = "~op2, true" else: secondSrc = "op2" diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 4c02ee35e..63bcfead9 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -99,12 +99,17 @@ namespace X86ISA const int ReturnAddressReg = 0; const int ReturnValueReg = INTREG_RAX; const int FramePointerReg = INTREG_RBP; - const int ArgumentReg0 = INTREG_RDI; - const int ArgumentReg1 = INTREG_RSI; - const int ArgumentReg2 = INTREG_RDX; - const int ArgumentReg3 = INTREG_RCX; - const int ArgumentReg4 = INTREG_R8W; - const int ArgumentReg5 = INTREG_R9W; + const int ArgumentReg[] = { + INTREG_RDI, + INTREG_RSI, + INTREG_RDX, + //This argument register is r10 for syscalls and rcx for C. + INTREG_R10W, + //INTREG_RCX, + INTREG_R8W, + INTREG_R9W + }; + const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); // Some OS syscalls use a second register (rdx) to return a second // value diff --git a/src/arch/x86/linux/syscalls.cc b/src/arch/x86/linux/syscalls.cc index 30cfea49d..5c756ec7f 100644 --- a/src/arch/x86/linux/syscalls.cc +++ b/src/arch/x86/linux/syscalls.cc @@ -90,10 +90,10 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = { /* 6 */ SyscallDesc("lstat", unimplementedFunc), /* 7 */ SyscallDesc("poll", unimplementedFunc), /* 8 */ SyscallDesc("lseek", unimplementedFunc), - /* 9 */ SyscallDesc("mmap", unimplementedFunc), + /* 9 */ SyscallDesc("mmap", mmapFunc<X86Linux64>), /* 10 */ SyscallDesc("mprotect", unimplementedFunc), /* 11 */ SyscallDesc("munmap", unimplementedFunc), - /* 12 */ SyscallDesc("brk", unimplementedFunc), + /* 12 */ SyscallDesc("brk", obreakFunc), /* 13 */ SyscallDesc("rt_sigaction", unimplementedFunc), /* 14 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), /* 15 */ SyscallDesc("rt_sigreturn", unimplementedFunc), diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 7deb54945..09962fdb6 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -338,8 +338,9 @@ X86LiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); //Set up the thread context to start running the process - threadContexts[0]->setIntReg(ArgumentReg0, argc); - threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + assert(NumArgumentRegs >= 2); + threadContexts[0]->setIntReg(ArgumentReg[0], argc); + threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base); threadContexts[0]->setIntReg(StackPointerReg, stack_min); Addr prog_entry = objFile->entryPoint(); diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 1754300d2..7f8f0547b 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -293,14 +293,16 @@ template <class Impl> TheISA::IntReg AlphaO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid); } template <class Impl> void AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { - this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid); } template <class Impl> diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index d1135f048..09d73b4a2 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -196,14 +196,16 @@ template <class Impl> TheISA::IntReg MipsO3CPU<Impl>::getSyscallArg(int i, int tid) { - return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid); + assert(i < TheISA::NumArgumentRegs); + return this->readArchIntReg(MipsISA::ArgumentReg[i], tid); } template <class Impl> void MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid) { - this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid); + assert(i < TheISA::NumArgumentRegs); + this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid); } template <class Impl> diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 2e398577e..068057fc0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -270,8 +270,9 @@ template <class Impl> TheISA::IntReg SparcO3CPU<Impl>::getSyscallArg(int i, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); TheISA::IntReg val = this->readArchIntReg(idx, tid); if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) val = bits(val, 31, 0); @@ -282,8 +283,9 @@ template <class Impl> void SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) { + assert(i < TheISA::NumArgumentRegs); TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), - SparcISA::ArgumentReg0 + i); + SparcISA::ArgumentReg[i]); this->setArchIntReg(idx, val, tid); } diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 2432df55e..92b00af26 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -253,11 +253,17 @@ class OzoneCPU : public BaseCPU #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) - { return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); } + { + assert(i < TheISA::NumArgumentRegs); + return thread->renameTable[TheISA::ArgumentReg[i]]->readIntResult(); + } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) - { thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); } + { + assert(i < TheISA::NumArgumentRegs); + thread->renameTable[TheISA::ArgumentReg[i]]->setIntResult(i); + } void setSyscallReturn(SyscallReturn return_value) { cpu->setSyscallReturn(return_value, thread->readTid()); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index c20fe3d90..6c6d5f842 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -377,15 +377,17 @@ class SimpleThread : public ThreadState #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { + assert(i < TheISA::NumArgumentRegs); return regs.readIntReg(TheISA::flattenIntIndex(getTC(), - TheISA::ArgumentReg0 + i)); + TheISA::ArgumentReg[i])); } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) { + assert(i < TheISA::NumArgumentRegs); regs.setIntReg(TheISA::flattenIntIndex(getTC(), - TheISA::ArgumentReg0 + i), val); + TheISA::ArgumentReg[i]), val); } void setSyscallReturn(SyscallReturn return_value) diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index a7703be7c..70fb4d688 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -690,7 +690,7 @@ class Tru64 : public OperatingSystem tc->clearArchRegs(); - tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0)); + tc->setIntReg(TheISA::ArgumentReg[0], gtoh(attrp->registers.a0)); tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc)); tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp)); tc->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, uniq_val); diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc index 4db5df067..c84b25dab 100644 --- a/src/kern/tru64/tru64_events.cc +++ b/src/kern/tru64/tru64_events.cc @@ -51,7 +51,7 @@ BadAddrEvent::process(ThreadContext *tc) // annotation for vmunix::badaddr in: // simos/simulation/apps/tcl/osf/tlaser.tcl - uint64_t a0 = tc->readIntReg(ArgumentReg0); + uint64_t a0 = tc->readIntReg(ArgumentReg[0]); AddrRangeList resp; bool snoop; diff --git a/src/sim/process.cc b/src/sim/process.cc index c556ade12..7343039df 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -405,8 +405,9 @@ LiveProcess::argsInit(int intSize, int pageSize) copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); - threadContexts[0]->setIntReg(ArgumentReg0, argc); - threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + assert(NumArgumentRegs >= 2); + threadContexts[0]->setIntReg(ArgumentReg[0], argc); + threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base); threadContexts[0]->setIntReg(StackPointerReg, stack_min); Addr prog_entry = objFile->entryPoint(); |