diff options
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 1 | ||||
| -rw-r--r-- | src/mem/tport.cc | 5 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 7bab3012b..3b56c0a2e 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -823,7 +823,6 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) } if (mshr->promoteDeferredTargets()) { - assert(mshr->needsExclusive() && !blk->isWritable()); // avoid later read getting stale data while write miss is // outstanding.. see comment in timingAccess() blk->status &= ~BlkReadable; diff --git a/src/mem/tport.cc b/src/mem/tport.cc index ad5e95909..15c7fdf9f 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -103,11 +103,6 @@ SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) return; } - // list is non-empty and this is not the head, so event should - // already be scheduled - assert(waitingOnRetry || - (sendEvent->scheduled() && sendEvent->when() <= when)); - // list is non-empty & this belongs at the end if (when >= transmitList.back().tick) { transmitList.push_back(DeferredPacket(when, pkt)); |