diff options
| -rwxr-xr-x | src/arch/isa_parser.py | 4 | ||||
| -rw-r--r-- | src/arch/power/isa/decoder.isa | 2 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 20df0a7db..cbc8651d1 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -790,10 +790,8 @@ class MemOperand(Operand): return '' def makeDecl(self): - # Note that initializations in the declarations are solely - # to avoid 'uninitialized variable' errors from the compiler. # Declare memory data variable. - return '%s %s = 0;\n' % (self.ctype, self.base_name) + return '%s %s;\n' % (self.ctype, self.base_name) def makeRead(self, predRead): if self.read_code != None: diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 11d222390..30002fe33 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -309,10 +309,10 @@ decode OPCODE default Unknown::unknown() { 151: stwx({{ Mem = Rs; }}); 150: stwcx({{ bool store_performed = false; + Mem = Rs; if (Rsv) { if (RsvLen == 4) { if (RsvAddr == EA) { - Mem = Rs; store_performed = true; } } |