diff options
-rw-r--r-- | src/cpu/simple_thread.hh | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index c018e3e49..2b79c9708 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -241,25 +241,25 @@ class SimpleThread : public ThreadState FloatReg readFloatReg(int reg_idx, int width) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); return regs.readFloatReg(flatIndex, width); } FloatReg readFloatReg(int reg_idx) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); return regs.readFloatReg(flatIndex); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); return regs.readFloatRegBits(flatIndex, width); } FloatRegBits readFloatRegBits(int reg_idx) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); return regs.readFloatRegBits(flatIndex); } @@ -271,25 +271,25 @@ class SimpleThread : public ThreadState void setFloatReg(int reg_idx, FloatReg val, int width) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); regs.setFloatReg(flatIndex, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); regs.setFloatReg(flatIndex, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); regs.setFloatRegBits(flatIndex, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); regs.setFloatRegBits(flatIndex, val); } |