diff options
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 7 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 89c0e48c7..97ae7d0c0 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -293,7 +293,7 @@ let {{ buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;") buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False) buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False, - isRasPop = "op1 == INTREG_LR", isBranch = "dest == INTREG_PC") + isRasPop = "op2 == INTREG_LR", isBranch = "dest == INTREG_PC") buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;") buildDataInst("mvn", "Dest = resTemp = ~secondOp;") buildDataInst("movt", diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index efb8e470b..88e8fecd1 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -115,11 +115,12 @@ def template DataRegConstructor {{ flags[IsUncondControl] = true; else flags[IsCondControl] = true; - } - if (%(is_ras_pop)s) { - flags[IsReturn] = true; + if (%(is_ras_pop)s) { + flags[IsReturn] = true; + } } + } }}; |