diff options
| -rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 46 | ||||
| -rw-r--r-- | src/mem/slicc/ast/LocalVariableAST.py | 9 |
2 files changed, 33 insertions, 22 deletions
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index f9d5ffcab..9592e3881 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -390,10 +390,11 @@ machine(L1Cache, "AMD Hammer-like protocol") if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); } else { + Address l2_victim_addr := L2cacheMemory.cacheProbe(in_msg.LineAddress); trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(in_msg.LineAddress), - getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); + l2_victim_addr, + getL2CacheEntry(l2_victim_addr), + TBEs[l2_victim_addr]); } } @@ -412,18 +413,20 @@ machine(L1Cache, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room - if (L2cacheMemory.cacheAvail(L1IcacheMemory.cacheProbe(in_msg.LineAddress))) { + Address l1i_victim_addr := L1IcacheMemory.cacheProbe(in_msg.LineAddress); + if (L2cacheMemory.cacheAvail(l1i_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, - L1IcacheMemory.cacheProbe(in_msg.LineAddress), - getL1ICacheEntry(L1IcacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L1IcacheMemory.cacheProbe(in_msg.LineAddress)]); + l1i_victim_addr, + getL1ICacheEntry(l1i_victim_addr), + TBEs[l1i_victim_addr]); } else { + Address l2_victim_addr := L2cacheMemory.cacheProbe(l1i_victim_addr); // The L2 does not have room, so we replace a line from the L2 trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress)), - getL2CacheEntry(L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress))), - TBEs[L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.LineAddress))]); + l2_victim_addr, + getL2CacheEntry(l2_victim_addr), + TBEs[l2_victim_addr]); } } } @@ -444,10 +447,11 @@ machine(L1Cache, "AMD Hammer-like protocol") if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); } else { + Address l2_victim_addr := L2cacheMemory.cacheProbe(in_msg.LineAddress); trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(in_msg.LineAddress), - getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); + l2_victim_addr, + getL2CacheEntry(l2_victim_addr), + TBEs[l2_victim_addr]); } } @@ -465,18 +469,20 @@ machine(L1Cache, "AMD Hammer-like protocol") } } else { // No room in the L1, so we need to make room - if (L2cacheMemory.cacheAvail(L1DcacheMemory.cacheProbe(in_msg.LineAddress))) { + Address l1d_victim_addr := L1DcacheMemory.cacheProbe(in_msg.LineAddress); + if (L2cacheMemory.cacheAvail(l1d_victim_addr)) { // The L2 has room, so we move the line from the L1 to the L2 trigger(Event:L1_to_L2, - L1DcacheMemory.cacheProbe(in_msg.LineAddress), - getL1DCacheEntry(L1DcacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L1DcacheMemory.cacheProbe(in_msg.LineAddress)]); + l1d_victim_addr, + getL1DCacheEntry(l1d_victim_addr), + TBEs[l1d_victim_addr]); } else { + Address l2_victim_addr := L2cacheMemory.cacheProbe(l1d_victim_addr); // The L2 does not have room, so we replace a line from the L2 trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress)), - getL2CacheEntry(L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress))), - TBEs[L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.LineAddress))]); + l2_victim_addr, + getL2CacheEntry(l2_victim_addr), + TBEs[l2_victim_addr]); } } } diff --git a/src/mem/slicc/ast/LocalVariableAST.py b/src/mem/slicc/ast/LocalVariableAST.py index 82e73ba7a..b779415f3 100644 --- a/src/mem/slicc/ast/LocalVariableAST.py +++ b/src/mem/slicc/ast/LocalVariableAST.py @@ -30,10 +30,11 @@ from slicc.ast.StatementAST import StatementAST from slicc.symbols import Var class LocalVariableAST(StatementAST): - def __init__(self, slicc, type_ast, ident): + def __init__(self, slicc, type_ast, ident, pointer = False): super(LocalVariableAST, self).__init__(slicc) self.type_ast = type_ast self.ident = ident + self.pointer = pointer def __repr__(self): return "[LocalVariableAST: %r %r]" % (self.type_ast, self.ident) @@ -50,5 +51,9 @@ class LocalVariableAST(StatementAST): v = Var(self.symtab, self.ident, self.location, type, ident, self.pairs) self.symtab.newSymbol(v) - code += "%s* %s" % (type.c_ident, ident) + if self.pointer or str(type) == "TBE" or ( + "interface" in type and type["interface"] == "AbstractCacheEntry"): + code += "%s* %s" % (type.c_ident, ident) + else: + code += "%s %s" % (type.c_ident, ident) return type |