diff options
| -rw-r--r-- | src/arch/arm/isa.hh | 6 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 44 |
2 files changed, 38 insertions, 12 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 1711ee0be..aa905e500 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2017 ARM Limited + * Copyright (c) 2010, 2012-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -629,7 +629,7 @@ namespace ArmISA void serialize(CheckpointOut &cp) const { DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); - SERIALIZE_ARRAY(miscRegs, NumMiscRegs); + SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); SERIALIZE_SCALAR(highestELIs64); SERIALIZE_SCALAR(haveSecurity); @@ -641,7 +641,7 @@ namespace ArmISA void unserialize(CheckpointIn &cp) { DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); - UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs); + UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 8cfa01345..cb4dcab8c 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2017 ARM Limited + * Copyright (c) 2010-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -666,15 +666,32 @@ namespace ArmISA MISCREG_CBAR_EL1, // 598 MISCREG_CONTEXTIDR_EL2, // 599 + // These MISCREG_FREESLOT are available Misc Register + // slots for future registers to be implemented. + MISCREG_FREESLOT_1, // 600 + MISCREG_FREESLOT_2, // 601 + MISCREG_FREESLOT_3, // 602 + MISCREG_FREESLOT_4, // 603 + MISCREG_FREESLOT_5, // 604 + MISCREG_FREESLOT_6, // 605 + + // NUM_PHYS_MISCREGS specifies the number of actual physical + // registers, not considering the following pseudo-registers + // (dummy registers), like UNKNOWN, CP15_UNIMPL... + // Checkpointing should use this physical index when + // saving/restoring register values. + NUM_PHYS_MISCREGS = 606, // 606 + // Dummy registers - MISCREG_NOP, // 600 - MISCREG_RAZ, // 601 - MISCREG_CP14_UNIMPL, // 602 - MISCREG_CP15_UNIMPL, // 603 - MISCREG_A64_UNIMPL, // 604 - MISCREG_UNKNOWN, // 605 - - NUM_MISCREGS // 606 + MISCREG_NOP, + MISCREG_RAZ, + MISCREG_CP14_UNIMPL, + MISCREG_CP15_UNIMPL, + MISCREG_A64_UNIMPL, + MISCREG_UNKNOWN, + + // Total number of Misc Registers: Physical + Dummy + NUM_MISCREGS }; enum MiscRegInfo { @@ -1348,6 +1365,15 @@ namespace ArmISA "cbar_el1", "contextidr_el2", + "freeslot1", + "freeslot2", + "freeslot3", + "freeslot4", + "freeslot5", + "freeslot6", + + "num_phys_regs", + // Dummy registers "nop", "raz", |