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-rw-r--r--src/arch/x86/floatregfile.hh2
-rw-r--r--src/arch/x86/floatregs.hh18
-rw-r--r--src/arch/x86/insts/static_inst.cc14
-rw-r--r--src/arch/x86/isa/microasm.isa2
-rw-r--r--src/arch/x86/x86_traits.hh1
5 files changed, 34 insertions, 3 deletions
diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh
index 282cac796..14dda443f 100644
--- a/src/arch/x86/floatregfile.hh
+++ b/src/arch/x86/floatregfile.hh
@@ -101,7 +101,7 @@ namespace X86ISA
std::string getFloatRegName(RegIndex);
//Each 128 bit xmm register is broken into two effective 64 bit registers.
- const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs;
+ const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
const int NumFloatRegs = NumFloatArchRegs;
class FloatRegFile
diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh
index 552cf6371..b9d6a5c43 100644
--- a/src/arch/x86/floatregs.hh
+++ b/src/arch/x86/floatregs.hh
@@ -120,7 +120,17 @@ namespace X86ISA
FLOATREG_XMM15_LOW,
FLOATREG_XMM15_HIGH,
- NUM_FLOATREGS = FLOATREG_XMM_BASE + 2 * NumXMMRegs
+ FLOATREG_MICROFP_BASE = FLOATREG_XMM_BASE + 2 * NumXMMRegs,
+ FLOATREG_MICROFP0 = FLOATREG_MICROFP_BASE,
+ FLOATREG_MICROFP1,
+ FLOATREG_MICROFP2,
+ FLOATREG_MICROFP3,
+ FLOATREG_MICROFP4,
+ FLOATREG_MICROFP5,
+ FLOATREG_MICROFP6,
+ FLOATREG_MICROFP7,
+
+ NUM_FLOATREGS = FLOATREG_MICROFP_BASE + NumMicroFpRegs
};
static inline FloatRegIndex
@@ -146,6 +156,12 @@ namespace X86ISA
{
return (FloatRegIndex)(FLOATREG_XMM_BASE + 2 * index + 1);
}
+
+ static inline FloatRegIndex
+ FLOATREG_MICROFP(int index)
+ {
+ return (FloatRegIndex)(FLOATREG_MICROFP_BASE + index);
+ }
};
#endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 948a74bc1..4f6ec5390 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -192,7 +192,19 @@ namespace X86ISA
}
ccprintf(os, suffix);
} else if (reg < Ctrl_Base_DepTag) {
- ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
+ int fpindex = reg - FP_Base_DepTag;
+ if(fpindex < NumMMXRegs) {
+ ccprintf(os, "%%mmx%d", reg - FP_Base_DepTag);
+ return;
+ }
+ fpindex -= NumMMXRegs;
+ if(fpindex < NumXMMRegs) {
+ ccprintf(os, "%%xmm%d_%s", fpindex / 2,
+ (fpindex % 2) ? "high": "low");
+ return;
+ }
+ fpindex -= NumXMMRegs;
+ ccprintf(os, "%%ufp%d", fpindex);
} else {
switch (reg - Ctrl_Base_DepTag) {
default:
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index dcc20c708..579909506 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -75,6 +75,8 @@ let {{
# Add in symbols for the microcode registers
for num in range(15):
assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
+ for num in range(7):
+ assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
# Add in symbols for the segment descriptor registers
for letter in ("C", "D", "E", "F", "G", "S"):
assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 381a60a63..aa5b959d1 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -65,6 +65,7 @@ namespace X86ISA
const int NumMMXRegs = 8;
const int NumXMMRegs = 16;
+ const int NumMicroFpRegs = 8;
const int NumCRegs = 16;
const int NumDRegs = 8;