diff options
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 7 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 7 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/regfile.hh | 21 |
4 files changed, 38 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 6301864b7..4d8014445 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -478,6 +478,13 @@ class BaseDynInst : public ExecContext, public RefCounted _prevDestRegIdx[idx] = previous_rename; } + void taintDestRegs(void) + { + for (auto dstreg: _destRegIdx) { + cpu->setTaint(dstreg); + } + } + /** Renames a source logical register to the physical register which * has/will produce that logical register's result. * @todo: add in whether or not the source register is ready. diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index b298b9baa..2566cf12a 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1279,6 +1279,13 @@ FullO3CPU<Impl>::setMiscReg(int misc_reg, } template <class Impl> +void +FullO3CPU<Impl>::setTaint(PhysRegIdPtr phys_reg) +{ + regFile.setTaint(phys_reg); +} + +template <class Impl> uint64_t FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) { diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 19b9a34e0..23e6f7434 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -399,6 +399,9 @@ class FullO3CPU : public BaseO3CPU void setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid); + /** taint a register */ + void setTaint(PhysRegIdPtr phys_reg); + uint64_t readIntReg(PhysRegIdPtr phys_reg); TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 943df35b9..00b4ef045 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -182,6 +182,27 @@ class PhysRegFile return &miscRegIds[reg_idx]; } + /** Set a physical register as tainted */ + void setTaint(PhysRegIdPtr phys_reg) { + RegIndex idx = phys_reg->index(); + switch (phys_reg->classValue()) { + case IntRegClass: + intTaintMap[idx] = true; + break; + case FloatRegClass: + floatTaintMap[idx] = true; + break; + case CCRegClass: + ccTaintMap[idx] = true; + break; + case MiscRegClass: + miscTaintMap[idx] = true; + break; + default: + break; + } + } + /** Reads an integer register. */ uint64_t readIntReg(PhysRegIdPtr phys_reg) const { |