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-rw-r--r--src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py6
-rw-r--r--src/arch/x86/isa/microops/fpop.isa9
2 files changed, 13 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
index 4e230513c..5a19aabd9 100644
--- a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
+++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
@@ -69,13 +69,15 @@ def macroop FSTP_R {
};
def macroop FSTP_M {
- movfp ufp1, st(0), spm=1
+ movfp ufp1, st(0)
stfp ufp1, seg, sib, disp
+ pop87
};
def macroop FSTP_P {
- movfp ufp1, st(0), spm=1
+ movfp ufp1, st(0)
rdip t7
stfp ufp1, seg, riprel, disp
+ pop87
};
'''
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index 142138fb2..8a77914d9 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -411,4 +411,13 @@ let {{
class chsfp(FpUnaryOp):
code = 'FpDestReg = (-1) * (FpSrcReg1);'
flag_code = 'FSW = FSW & (~CC1Bit);'
+
+ class Pop87(FpUnaryOp):
+ def __init__(self, spm=1, UpdateFTW=True):
+ super(Pop87, self).__init__( \
+ "InstRegIndex(FLOATREG_MICROFP0)", \
+ "InstRegIndex(FLOATREG_MICROFP0)", \
+ spm=spm, SetStatus=False, UpdateFTW=UpdateFTW)
+
+ code = ''
}};