diff options
| -rw-r--r-- | src/cpu/BaseCPU.py | 3 | ||||
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 4 | ||||
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 4 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 7ec79ad0a..cd82207cd 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -51,7 +51,6 @@ from Bus import CoherentBus from InstTracer import InstTracer from ExeTracer import ExeTracer from MemObject import MemObject -from BranchPredictor import BranchPredictor from ClockDomain import * default_tracer = ExeTracer() @@ -210,8 +209,6 @@ class BaseCPU(MemObject): dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] - branchPred = Param.BranchPredictor(NULL, "Branch Predictor") - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index e29a29556..4caf254c4 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -68,4 +68,6 @@ class InOrderCPU(BaseCPU): div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") - branchPred = BranchPredictor(numThreads = Parent.numThreads) + branchPred = Param.BranchPredictor(BranchPredictor(numThreads = + Parent.numThreads), + "Branch Predictor") diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index f46388b4c..e19881248 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -125,7 +125,9 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - branchPred = BranchPredictor(numThreads = Parent.numThreads) + branchPred = Param.BranchPredictor(BranchPredictor(numThreads = + Parent.numThreads), + "Branch Predictor") needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', "Enable TSO Memory model") |