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-rw-r--r--dev/ide_ctrl.cc19
-rw-r--r--dev/ide_disk.cc11
-rw-r--r--python/m5/config.py10
-rw-r--r--python/m5/convert.py10
-rw-r--r--python/m5/objects/Root.mpy1
-rw-r--r--python/m5/objects/SimConsole.mpy2
-rw-r--r--sim/universe.cc12
-rwxr-xr-xutil/stats/stats.py101
8 files changed, 67 insertions, 99 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 037de1dea..857cdeb78 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -289,15 +289,16 @@ IdeController::ReadConfig(int offset, int size, uint8_t *data)
memcpy((void *)data, (void *)&pci_regs[offset], size);
}
- DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
- origOffset, offset, size, *(uint32_t *)data);
+ DPRINTF(IdeCtrl, "PCI read offset: %#x (%#x) size: %#x data: %#x\n",
+ origOffset, offset, size,
+ (*(uint32_t *)data) & (0xffffffff >> 8 * (4 - size)));
}
void
IdeController::WriteConfig(int offset, int size, uint32_t data)
{
- DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
- offset, size, data);
+ DPRINTF(IdeCtrl, "PCI write offset: %#x size: %#x data: %#x\n",
+ offset, size, data & (0xffffffff >> 8 * (4 - size)));
// do standard write stuff if in standard PCI space
if (offset < PCI_DEVICE_SPECIFIC) {
@@ -438,8 +439,9 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
memcpy((void *)data, &bmi_regs[offset], req->size);
}
- DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
- offset, req->size, *(uint32_t *)data);
+ DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
+ offset, req->size,
+ (*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));
return No_Fault;
}
@@ -458,8 +460,9 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
byte = (req->size == sizeof(uint8_t)) ? true : false;
cmdBlk = (type == COMMAND_BLOCK) ? true : false;
- DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
- offset, req->size, *(uint32_t *)data);
+ DPRINTF(IdeCtrl, "write from offset: %#x size: %#x data: %#x\n",
+ offset, req->size,
+ (*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));
uint8_t oldVal, newVal;
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index bfaf3d3aa..213fc6a97 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -336,7 +336,8 @@ IdeDisk::dmaPrdReadDone()
physmem->dma_addr(curPrdAddr, sizeof(PrdEntry_t)),
sizeof(PrdEntry_t));
- DPRINTF(IdeDisk, "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
+ DPRINTF(IdeDisk,
+ "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
curPrd.getBaseAddr(), pciToDma(curPrd.getBaseAddr()),
curPrd.getByteCount(), (cmdBytesLeft/SectorSize),
curPrd.getEOT(), curSector);
@@ -609,10 +610,10 @@ void
IdeDisk::abortDma()
{
if (dmaState == Dma_Idle)
- panic("Inconsistent DMA state, should be in Dma_Start or Dma_Transfer!\n");
+ panic("Inconsistent DMA state, should be Start or Transfer!");
if (devState != Transfer_Data_Dma && devState != Prepare_Data_Dma)
- panic("Inconsistent device state, should be in Transfer or Prepare!\n");
+ panic("Inconsistent device state, should be Transfer or Prepare!\n");
updateState(ACT_CMD_ERROR);
}
@@ -732,7 +733,7 @@ IdeDisk::startCommand()
void
IdeDisk::intrPost()
{
- DPRINTF(IdeDisk, "IDE Disk Posting Interrupt\n");
+ DPRINTF(IdeDisk, "Posting Interrupt\n");
if (intrPending)
panic("Attempt to post an interrupt with one pending\n");
@@ -746,7 +747,7 @@ IdeDisk::intrPost()
void
IdeDisk::intrClear()
{
- DPRINTF(IdeDisk, "IDE Disk Clearing Interrupt\n");
+ DPRINTF(IdeDisk, "Clearing Interrupt\n");
if (!intrPending)
panic("Attempt to clear a non-pending interrupt\n");
diff --git a/python/m5/config.py b/python/m5/config.py
index a791bbebf..e260c57a7 100644
--- a/python/m5/config.py
+++ b/python/m5/config.py
@@ -1140,10 +1140,12 @@ class UInt32(CheckedInt): cppname = 'uint32_t'; size = 32; unsigned = True
class Int64(CheckedInt): cppname = 'int64_t'; size = 64; unsigned = False
class UInt64(CheckedInt): cppname = 'uint64_t'; size = 64; unsigned = True
-class Counter(CheckedInt): cppname = 'Counter'; size = 64; unsigned = True
-class Tick(CheckedInt): cppname = 'Tick'; size = 64; unsigned = True
+class Counter(CheckedInt): cppname = 'Counter'; size = 64; unsigned = True
+class Tick(CheckedInt): cppname = 'Tick'; size = 64; unsigned = True
+class TcpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True
+class UdpPort(CheckedInt): cppname = 'uint16_t'; size = 16; unsigned = True
-class Percent(CheckedInt): cppname = 'int'; min = 0; max = 100
+class Percent(CheckedInt): cppname = 'int'; min = 0; max = 100
class MemorySize(CheckedInt):
cppname = 'uint64_t'
@@ -1283,7 +1285,7 @@ class NullSimObject(object):
pass
def _convert(cls, value):
- if value == Nxone:
+ if value == None:
return
if isinstance(value, cls):
diff --git a/python/m5/convert.py b/python/m5/convert.py
index 6ccefd2fc..a89303687 100644
--- a/python/m5/convert.py
+++ b/python/m5/convert.py
@@ -153,15 +153,15 @@ def toNetworkBandwidth(value):
raise TypeError, "wrong type '%s' should be str" % type(value)
if value.endswith('Tbps'):
- return float(value[:-3]) * tera
+ return float(value[:-4]) * tera
elif value.endswith('Gbps'):
- return float(value[:-3]) * giga
+ return float(value[:-4]) * giga
elif value.endswith('Mbps'):
- return float(value[:-3]) * mega
+ return float(value[:-4]) * mega
elif value.endswith('kbps'):
- return float(value[:-3]) * kilo
+ return float(value[:-4]) * kilo
elif value.endswith('bps'):
- return float(value[:-2])
+ return float(value[:-3])
else:
return float(value)
diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy
index c535bd2dc..2493dc4ff 100644
--- a/python/m5/objects/Root.mpy
+++ b/python/m5/objects/Root.mpy
@@ -7,7 +7,6 @@ simobj Root(SimObject):
type = 'Root'
frequency = Param.RootFrequency('200MHz', "tick frequency")
output_file = Param.String('cout', "file to dump simulator output to")
- full_system = Param.Bool("Full system simulation?")
hier = HierParams(do_data = False, do_events = True)
checkpoint = Param.String('', "Checkpoint file")
stats = Statistics()
diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy
index 3588a949d..53ddaa25c 100644
--- a/python/m5/objects/SimConsole.mpy
+++ b/python/m5/objects/SimConsole.mpy
@@ -1,6 +1,6 @@
simobj ConsoleListener(SimObject):
type = 'ConsoleListener'
- port = Param.UInt16(3456, "listen port")
+ port = Param.TcpPort(3456, "listen port")
simobj SimConsole(SimObject):
type = 'SimConsole'
diff --git a/sim/universe.cc b/sim/universe.cc
index 8419e1fe4..5ae41eefd 100644
--- a/sim/universe.cc
+++ b/sim/universe.cc
@@ -42,7 +42,6 @@
using namespace std;
Tick curTick = 0;
-bool fullSystem;
ostream *outputStream;
ostream *configStream;
@@ -86,7 +85,6 @@ class Root : public SimObject
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
- Param<bool> full_system;
Param<Tick> frequency;
Param<string> output_file;
@@ -94,7 +92,6 @@ END_DECLARE_SIM_OBJECT_PARAMS(Root)
BEGIN_INIT_SIM_OBJECT_PARAMS(Root)
- INIT_PARAM(full_system, "full system simulation"),
INIT_PARAM(frequency, "tick frequency"),
INIT_PARAM(output_file, "file to dump simulator output to")
@@ -107,15 +104,6 @@ CREATE_SIM_OBJECT(Root)
panic("only one root object allowed!");
created = true;
- fullSystem = full_system;
-
-#ifdef FULL_SYSTEM
- if (!fullSystem)
- panic("FULL_SYSTEM compiled and configuration not full_system");
-#else
- if (fullSystem)
- panic("FULL_SYSTEM not compiled but configuration is full_system");
-#endif
outputStream = simout.find(output_file);
Root *root = new Root(getInstanceName());
diff --git a/util/stats/stats.py b/util/stats/stats.py
index eedb006a0..5f5b6b86e 100755
--- a/util/stats/stats.py
+++ b/util/stats/stats.py
@@ -55,14 +55,10 @@ def unique(list):
map(set.__setitem__, list, [])
return set.keys()
-def graphdata68(runs, options, tag, label, value):
- import info
- configs = ['ste', 'hte', 'htd', 'ocm', 'occ', 'ocp' ]
- benchmarks = [ 'm', 's', 'snt', 'nb1', 'w1', 'w2', 'w3', 'w4', 'nm', 'ns', 'nw1', 'nw2', 'nw3' ]
- dmas = [ 'x' ]
- caches = [ '2', '4' ]
+#benchmarks = [ 'm', 's', 'snt', 'nb1', 'w1', 'w2', 'w3', 'w4', 'nm', 'ns', 'nw1', 'nw2', 'nw3' ]
- names = []
+def graphdata(runs, options, tag, label, value):
+ import info
bench_system = {
'm' : 'client',
@@ -86,27 +82,42 @@ def graphdata68(runs, options, tag, label, value):
'nw3' : 'natbox'
}
+ system_configs = {
+ 's1' : 'Uni 4GHz',
+ 'm1' : 'Uni 6GHz',
+ 'f1' : 'Uni 8GHz',
+ 'q1' : 'Uni 10GHz',
+ 's2' : 'Dual 4GHz',
+ 'm2' : 'Dual 6GHz',
+ 's4' : 'Quad 4GHz',
+ 'm4' : 'Quad 6GHz' }
+
+ configs = ['ste', 'hte', 'htd', 'ocm', 'occ', 'ocp' ]
+ benchmarks = [ 'm', 'snt', 'w2', 'nm', 'nw2' ]
+ caches = [ '0', '2', '4' ]
+
+ names = []
for bench in benchmarks:
if bench_system[bench] != options.system:
continue
- for dma in dmas:
- for cache in caches:
- names.append([bench, dma, cache])
+ for cache in caches:
+ names.append([bench, cache])
- for bench,dma,cache in names:
- base = '%s.%s.%s' % (bench, dma, cache)
- fname = 'data/%s.%s.68.dat' % (tag, base)
+ for bench,cache in names:
+ base = '%s.%s' % (bench, cache)
+ fname = 'data/uni.%s.%s.dat' % (tag, base)
f = open(fname, 'w')
print >>f, '#set TITLE = '
print >>f, '#set ylbl = %s' % label
#print >>f, '#set sublabels = %s' % ' '.join(configs)
print >>f, '#set sublabels = ste hte htd ocm occ ocs'
- for speed,freq in zip(['s', 'm', 'f', 'q'],['4GHz', '6GHz','8GHz', '10GHz']):
- print >>f, '"%s"' % freq,
+ for speed in ('s1', 'm1', 'f1', 'q1'):
+ label = system_configs[speed]
+ print >>f, '"%s"' % label,
for conf in configs:
- name = '%s.%s.%s.%s.%s' % (conf, bench, dma, cache, speed)
+ name = '%s.%s.%s.%s' % (conf, bench, cache, speed)
run = info.source.allRunNames[name]
info.display_run = run.run;
val = float(value)
@@ -117,65 +128,32 @@ def graphdata68(runs, options, tag, label, value):
print >>f
f.close()
-def graphdata(runs, options, tag, label, value):
- if options.graph68:
- graphdata68(runs, options, tag, label, value)
- return
-
- import info
configs = ['ste', 'hte', 'htd', 'ocm', 'occ', 'ocp' ]
- #benchmarks = [ 'm', 's', 'nb1', 'nb2', 'nt1', 'nt2', 'w1', 'w2', 'w3', 'w4', 'ns', 'nm', 'nw1', 'nw2', 'nw3' ]
- #benchmarks = [ 'm', 's', 'nb1', 'nb2', 'nt1', 'w1', 'w2', 'w3', 'ns', 'nm', 'w1s' ]
- benchmarks = [ 'm', 's', 'nb1', 'nb2', 'w1', 'w2', 'w3', 'w4', 'ns', 'nm', 'nw1', 'snt' ]
- #dmas = [ 'x', 'd', 'b' ]
- dmas = [ 'x' ]
- caches = [ '2', '4' ]
+ benchmarks = [ 'w2']
+ caches = [ '0', '2', '4' ]
names = []
-
- bench_system = {
- 'm' : 'client',
- 's' : 'client',
- 'snt' : 'client',
- 'nb1' : 'server',
- 'nb2' : 'server',
- 'nt1' : 'server',
- 'nt2' : 'server',
- 'w1' : 'server',
- 'w2' : 'server',
- 'w3' : 'server',
- 'w4' : 'server',
- 'w1s' : 'server',
- 'w2s' : 'server',
- 'w3s' : 'server',
- 'ns' : 'natbox',
- 'nm' : 'natbox',
- 'nw1' : 'natbox',
- 'nw2' : 'natbox',
- 'nw3' : 'natbox'
- }
-
for bench in benchmarks:
if bench_system[bench] != options.system:
continue
- for dma in dmas:
- for cache in caches:
- names.append([bench, dma, cache])
+ for cache in caches:
+ names.append([bench, cache])
- for bench,dma,cache in names:
- base = '%s.%s.%s' % (bench, dma, cache)
- fname = 'data/%s.%s.dat' % (tag, base)
+ for bench,cache in names:
+ base = '%s.%s' % (bench, cache)
+ fname = 'data/mp.%s.%s.dat' % (tag, base)
f = open(fname, 'w')
print >>f, '#set TITLE = '
print >>f, '#set ylbl = %s' % label
#print >>f, '#set sublabels = %s' % ' '.join(configs)
print >>f, '#set sublabels = ste hte htd ocm occ ocs'
- for speed,freq in zip(['s', 'q'],['4GHz','10GHz']):
- print >>f, '"%s"' % freq,
+ for speed in ('s2', 'm2', 's4', 'm4'):
+ label = system_configs[speed]
+ print >>f, '"%s"' % label,
for conf in configs:
- name = '%s.%s.%s.%s.%s' % (conf, bench, dma, cache, speed)
+ name = '%s.%s.%s.%s' % (conf, bench, cache, speed)
run = info.source.allRunNames[name]
info.display_run = run.run;
val = float(value)
@@ -744,13 +722,10 @@ if __name__ == '__main__':
options.get = None
options.binned = False
options.graph = False
- options.graph68 = False
options.ticks = False
opts, args = getopts(sys.argv[1:], '-6BEFGd:g:h:pr:s:u:T:')
for o,a in opts:
- if o == '-6':
- options.graph68 = True
if o == '-B':
options.binned = True
if o == '-E':
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-21 17:27:54 +0000