diff options
| -rwxr-xr-x | arch/isa_parser.py | 10 | ||||
| -rw-r--r-- | arch/mips/isa/base.isa | 2 | ||||
| -rw-r--r-- | arch/mips/isa/decoder.isa | 2 | ||||
| -rw-r--r-- | arch/mips/isa/formats/basic.isa | 2 | ||||
| -rw-r--r-- | arch/mips/isa/formats/branch.isa | 87 | ||||
| -rw-r--r-- | arch/mips/isa/operands.isa | 7 | ||||
| -rw-r--r-- | arch/mips/isa_traits.hh | 2 | ||||
| -rw-r--r-- | cpu/base.hh | 4 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 40 | ||||
| -rw-r--r-- | cpu/static_inst.hh | 10 |
10 files changed, 120 insertions, 46 deletions
diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 3fbb5276b..864a6a8a7 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1355,6 +1355,7 @@ class MemOperand(Operand): def makeAccSize(self): return self.size + class NPCOperand(Operand): def makeConstructor(self): return '' @@ -1365,6 +1366,15 @@ class NPCOperand(Operand): def makeWrite(self): return 'xc->setNextPC(%s);\n' % self.base_name +class NNPCOperand(Operand): + def makeConstructor(self): + return '' + + def makeRead(self): + return '%s = xc->readPC() + 8;\n' % self.base_name + + def makeWrite(self): + return 'xc->setNextNPC(%s);\n' % self.base_name def buildOperandNameMap(userDict, lineno): global operandNameMap diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 99fa302c0..db37cf49c 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -16,7 +16,7 @@ output header {{ // Constructor. MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) - : StaticInst<SPARCISA>(mnem, _machInst, __opClass) + : StaticInst<MIPSISA>(mnem, _machInst, __opClass) { } diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 997badb25..f46024f15 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -168,7 +168,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode REGIMM_LO { format Trap { 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); - 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); + 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa index 24c397685..3b62aa5c3 100644 --- a/arch/mips/isa/formats/basic.isa +++ b/arch/mips/isa/formats/basic.isa @@ -40,7 +40,7 @@ def template BasicExecute {{ if(fault == No_Fault) { - %(op_wb)s; + %(op_wb)s; } return fault; } diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index 75e7830d0..1f7a6f330 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -45,12 +45,12 @@ output header {{ { protected: /// target address (signed) Displacement . - int32_t targetOffset; + int32_t disp; /// Constructor. Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), - targetOffset(OFFSET << 2) + disp(OFFSET << 2) { } @@ -67,12 +67,12 @@ output header {{ { protected: /// target address (signed) Displacement . - int32_t targetOffset; + int32_t disp; /// Constructor. Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), - targetOffset(OFFSET << 2) + disp(OFFSET << 2) { } @@ -116,6 +116,12 @@ output decoder {{ } Addr + BranchLikely::branchTarget(Addr branchPC) const + { + return branchPC + 4 + disp; + } + + Addr Jump::branchTarget(ExecContext *xc) const { Addr NPC = xc->readPC() + 4; @@ -181,6 +187,44 @@ output decoder {{ } std::string + BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // There's only one register arg (RA), but it could be + // either a source (the condition for conditional + // branches) or a destination (the link reg for + // unconditional branches) + if (_numSrcRegs > 0) { + printReg(ss, _srcRegIdx[0]); + ss << ","; + } + else if (_numDestRegs > 0) { + printReg(ss, _destRegIdx[0]); + ss << ","; + } + +#ifdef SS_COMPATIBLE_DISASSEMBLY + if (_numSrcRegs == 0 && _numDestRegs == 0) { + printReg(ss, 31); + ss << ","; + } +#endif + + Addr target = pc + 4 + disp; + + std::string str; + if (symtab && symtab->findSymbol(target, str)) + ss << str; + else + ccprintf(ss, "0x%x", target); + + return ss.str(); + } + + std::string Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; @@ -205,20 +249,18 @@ output decoder {{ } }}; - -def template JumpOrBranchDecode {{ - return (RD == 0) - ? (StaticInst<MipsISA> *)new %(class_name)s(machInst) - : (StaticInst<MipsISA> *)new %(class_name)sAndLink(machInst); -}}; - def format Branch(code,*flags) {{ - code = 'bool cond;\n' + code + '\n' + code = 'bool cond;\n\t' + code + '\n' - if flags == 'IsLink': - code += 'R31 = NPC + 8\n' + #Add Link Code if Link instruction + strlen = len(name) + if name[strlen-2:] == 'al': + code += 'R31 = NPC + 4;\n' - code += '\nif (cond) NPC = NPC + disp;\n'; + # condition code + code += 'if (cond) {' + code += ' NPC = NPC + disp;\n' + code += ' NNPC = NNPC + disp;\n } \n' iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl')) @@ -228,11 +270,20 @@ def format Branch(code,*flags) {{ exec_output = BasicExecute.subst(iop) }}; + def format BranchLikely(code,*flags) {{ - code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; + code = 'bool cond;\n\t\t\t' + code + + #Add Link Code if Link instruction + strlen = len(name) + if name[strlen-3:] == 'all': + code += 'R31 = NPC + 4;\n' + + #condition code + code += 'if (cond) {' + code += ' NPC = NPC + disp;\n' + code += ' NNPC = NNPC + disp;\n } \n' - if flags == 'IsLink': - code += 'R31 = NPC + 8\n' iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl','IsCondDelaySlot')) diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa index cf6f10e0b..77035f04c 100644 --- a/arch/mips/isa/operands.isa +++ b/arch/mips/isa/operands.isa @@ -16,6 +16,7 @@ def operands {{ 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), + 'R31': ('IntReg', 'uw','R31','IsInteger', 4), 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), 'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4), @@ -24,12 +25,12 @@ def operands {{ 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2), 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), - 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4) + 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), + 'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4) #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), # The next two are hacks for non-full-system call-pal emulation #'R0': ('IntReg', 'uq', '0', None, 1), - #'R16': ('IntReg', 'uq', '16', None, 1) }}; diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 55e9c0dcb..e171737a3 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -430,6 +430,8 @@ class MipsISA Addr pc; // Program Counter Addr npc; // Next Program Counter + Addr nnpc; // Next next program Counter + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/cpu/base.hh b/cpu/base.hh index ab52e7b81..82a47bf4c 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -36,7 +36,7 @@ #include "cpu/sampler/sampler.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" -#include "arch/isa_traits.hh" +#include "targetarch/isa_traits.hh" #if FULL_SYSTEM class System; @@ -141,6 +141,8 @@ class BaseCPU : public SimObject virtual void startup(); virtual void regStats(); + virtual void activateWhenReady(int tid) {}; + void registerExecContexts(); /// Prepare for another CPU to take over execution. When it is diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 7e905e7d3..f11d69273 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -86,7 +86,7 @@ class ExecContext Active, /// Temporarily inactive. Entered while waiting for - /// synchronization, etc. + /// initialization,synchronization, etc. Suspended, /// Permanently shut down. Entered when target executes @@ -101,6 +101,8 @@ class ExecContext public: Status status() const { return _status; } + void setStatus(Status newStatus) { _status = newStatus; } + /// Set the status to Active. Optional delay indicates number of /// cycles to wait before beginning execution. void activate(int delay = 1); @@ -212,17 +214,17 @@ class ExecContext int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -237,7 +239,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault * dummyTranslation(MemReqPtr &req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -246,17 +248,17 @@ class ExecContext // put the asid in the upper 16 bits of the paddr req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return NoFault; + return No_Fault; } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -264,7 +266,7 @@ class ExecContext #endif template <class T> - Fault * read(MemReqPtr &req, T &data) + Fault read(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { @@ -274,14 +276,14 @@ class ExecContext } #endif - Fault * error; + Fault error; error = mem->read(req, data); data = LittleEndianGuest::gtoh(data); return error; } template <class T> - Fault * write(MemReqPtr &req, T &data) + Fault write(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) @@ -307,7 +309,7 @@ class ExecContext << "on cpu " << req->xc->cpu_id << std::endl; } - return NoFault; + return No_Fault; } else req->xc->storeCondFailures = 0; } @@ -339,7 +341,7 @@ class ExecContext inst = new_inst; } - Fault * instRead(MemReqPtr &req) + Fault instRead(MemReqPtr &req) { return mem->read(req, inst); } @@ -418,13 +420,13 @@ class ExecContext } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault); - Fault * setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault &fault); + Fault setIpr(int idx, uint64_t val); int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } - Fault * hwrei(); + Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault * fault); + void ev5_trap(Fault fault); bool simPalCheck(int palFunc); #endif @@ -434,7 +436,7 @@ class ExecContext * @todo How to do this properly so it's dependent upon ISA only? */ - void trap(Fault * fault); + void trap(Fault fault); #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 6be30cd31..333a6f1ca 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -36,7 +36,7 @@ #include "base/refcnt.hh" #include "encumbered/cpu/full/op_class.hh" #include "sim/host.hh" -#include "arch/isa_traits.hh" +#include "targetarch/isa_traits.hh" // forward declarations struct AlphaSimpleImpl; @@ -113,6 +113,8 @@ class StaticInstBase : public RefCounted IsSerializing, ///< Serializes pipeline: won't execute until all /// older instructions have committed. + IsSerializeBefore, + IsSerializeAfter, IsMemBarrier, ///< Is a memory barrier IsWriteBarrier, ///< Is a write barrier @@ -196,7 +198,11 @@ class StaticInstBase : public RefCounted bool isUncondCtrl() const { return flags[IsUncondControl]; } bool isThreadSync() const { return flags[IsThreadSync]; } - bool isSerializing() const { return flags[IsSerializing]; } + bool isSerializing() const { return flags[IsSerializing] || + flags[IsSerializeBefore] || + flags[IsSerializeAfter]; } + bool isSerializeBefore() const { return flags[IsSerializeBefore]; } + bool isSerializeAfter() const { return flags[IsSerializeAfter]; } bool isMemBarrier() const { return flags[IsMemBarrier]; } bool isWriteBarrier() const { return flags[IsWriteBarrier]; } bool isNonSpeculative() const { return flags[IsNonSpeculative]; } |