diff options
63 files changed, 640 insertions, 1937 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index ae8ab519f..16a158f0d 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -58,6 +58,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY Entry lookup(Address); void changePermission(Address, AccessPermission); bool isTagPresent(Address); + void profileMiss(CacheMsg); } // TBE fields @@ -259,6 +260,12 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles()); } + action(p_profileMiss, "p", desc="Profile cache miss") { + peek(mandatoryQueue_in, CacheMsg) { + cacheMemory.profileMiss(in_msg); + } + } + action(r_load_hit, "r", desc="Notify sequencer the load completed.") { DEBUG_EXPR(cacheMemory[address].DataBlk); sequencer.readCallback(address, cacheMemory[address].DataBlk); @@ -326,6 +333,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY v_allocateTBE; i_allocateL1CacheBlock; a_issueRequest; + p_profileMiss; m_popMandatoryQueue; } @@ -333,6 +341,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY v_allocateTBE; i_allocateL1CacheBlock; a_issueRequest; + p_profileMiss; m_popMandatoryQueue; } diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index a275e4b8d..fa8903d47 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -129,9 +129,9 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D if (dmaRequestQueue_in.isReady()) { peek(dmaRequestQueue_in, DMARequestMsg) { if (in_msg.Type == DMARequestType:READ) { - trigger(Event:DMA_READ, in_msg.PhysicalAddress); + trigger(Event:DMA_READ, in_msg.LineAddress); } else if (in_msg.Type == DMARequestType:WRITE) { - trigger(Event:DMA_WRITE, in_msg.PhysicalAddress); + trigger(Event:DMA_WRITE, in_msg.LineAddress); } else { error("Invalid message"); } @@ -267,6 +267,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D peek(memQueue_in, MemoryMsg) { enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { out_msg.PhysicalAddress := address; + out_msg.LineAddress := address; out_msg.Type := DMAResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); @@ -281,6 +282,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D peek(requestQueue_in, RequestMsg) { enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { out_msg.PhysicalAddress := address; + out_msg.LineAddress := address; out_msg.Type := DMAResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); @@ -292,6 +294,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") { out_msg.PhysicalAddress := address; + out_msg.LineAddress := address; out_msg.Type := DMAResponseType:ACK; out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Writeback_Control; @@ -355,12 +358,6 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D } } - action(dw_writeDMAData, "dw", desc="DMA Write data to memory") { - peek(dmaRequestQueue_in, DMARequestMsg) { - directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len); - } - } - action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") { directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len); } diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index 1f929cf9b..d5de18552 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -39,9 +39,9 @@ machine(DMA, "DMA Controller") { if (dmaRequestQueue_in.isReady()) { peek(dmaRequestQueue_in, DMARequestMsg) { if (in_msg.Type == DMARequestType:READ ) { - trigger(Event:ReadRequest, in_msg.PhysicalAddress); + trigger(Event:ReadRequest, in_msg.LineAddress); } else if (in_msg.Type == DMARequestType:WRITE) { - trigger(Event:WriteRequest, in_msg.PhysicalAddress); + trigger(Event:WriteRequest, in_msg.LineAddress); } else { error("Invalid request type"); } @@ -53,9 +53,9 @@ machine(DMA, "DMA Controller") { if (dmaResponseQueue_in.isReady()) { peek( dmaResponseQueue_in, DMAResponseMsg) { if (in_msg.Type == DMAResponseType:ACK) { - trigger(Event:Ack, in_msg.PhysicalAddress); + trigger(Event:Ack, in_msg.LineAddress); } else if (in_msg.Type == DMAResponseType:DATA) { - trigger(Event:Data, in_msg.PhysicalAddress); + trigger(Event:Data, in_msg.LineAddress); } else { error("Invalid response type"); } @@ -67,6 +67,7 @@ machine(DMA, "DMA Controller") { peek(dmaRequestQueue_in, DMARequestMsg) { enqueue(reqToDirectory_out, DMARequestMsg) { out_msg.PhysicalAddress := address; + out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -80,6 +81,7 @@ machine(DMA, "DMA Controller") { peek(dmaRequestQueue_in, DMARequestMsg) { enqueue(reqToDirectory_out, DMARequestMsg) { out_msg.PhysicalAddress := address; + out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm index 56c2e2e01..8c0afed2e 100644 --- a/src/mem/protocol/MI_example-msg.sm +++ b/src/mem/protocol/MI_example-msg.sm @@ -104,6 +104,7 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") { structure(DMARequestMsg, desc="...", interface="NetworkMessage") { DMARequestType Type, desc="Request type (read/write)"; Address PhysicalAddress, desc="Physical address for this request"; + Address LineAddress, desc="Line address for this request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; int Offset, desc="The offset into the datablock"; @@ -114,6 +115,7 @@ structure(DMARequestMsg, desc="...", interface="NetworkMessage") { structure(DMAResponseMsg, desc="...", interface="NetworkMessage") { DMAResponseType Type, desc="Response type (DATA/ACK)"; Address PhysicalAddress, desc="Physical address for this request"; + Address LineAddress, desc="Line address for this request"; NetDest Destination, desc="Destination"; DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc index 7e2715ff9..3928e94e6 100644 --- a/src/mem/ruby/buffers/MessageBuffer.cc +++ b/src/mem/ruby/buffers/MessageBuffer.cc @@ -32,7 +32,6 @@ */ #include "mem/ruby/buffers/MessageBuffer.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/system/System.hh" MessageBuffer::MessageBuffer() @@ -323,7 +322,6 @@ void MessageBuffer::clear() void MessageBuffer::recycle() { - // const int RubyConfig::getRecycleLatency() = 3; DEBUG_MSG(QUEUE_COMP,MedPrio,"recycling " + m_name); assert(isReady()); MessageBufferNode node = m_prio_heap.extractMin(); diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index b6899d1ac..c48152354 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -107,16 +107,6 @@ private: inline Address line_address(const Address& addr) { Address temp(addr); temp.makeLineAddress(); return temp; } -/* -inline -Address next_stride_address(const Address& addr, int stride) { - Address temp = addr; - temp.makeNextStrideAddress(stride); - temp.setAddress(temp.maskHighOrderBits(ADDRESS_WIDTH-RubyConfig::memorySizeBits())); // surpress wrap-around problem - return temp; -} -*/ - // Output operator declaration ostream& operator<<(ostream& out, const Address& obj); // comparison operator declaration @@ -207,17 +197,6 @@ integer_t Address::memoryModuleIndex() const { integer_t index = bitSelect(RubySystem::getBlockSizeBits()+RubySystem::getMemorySizeBits(), ADDRESS_WIDTH); assert (index >= 0); - /* - if (index >= RubyConfig::memoryModuleBlocks()) { - cerr << " memoryBits: " << RubySystem::getMemorySizeBits() << " memorySizeBits: " << RubySystem::getMemorySizeBits() - << " Address: " << "[" << hex << "0x" << m_address << "," << " line 0x" << maskLowOrderBits(RubySystem::getBlockSizeBits()) << dec << "]" << flush - << "error: limit exceeded. " << - " getDataBlockBits: " << RubySystem::getBlockSizeBits() << - " memoryModuleBlocks: " << RubyConfig::memoryModuleBlocks() << - " index: " << index << endl; - } - assert (index < RubyConfig::memoryModuleBlocks()); - */ return index; // Index indexHighPortion = address.bitSelect(MEMORY_SIZE_BITS-1, PAGE_SIZE_BITS+NUMBER_OF_MEMORY_MODULE_BITS); diff --git a/src/mem/ruby/common/DataBlock.hh b/src/mem/ruby/common/DataBlock.hh index 2a0811f76..ccd73c36b 100644 --- a/src/mem/ruby/common/DataBlock.hh +++ b/src/mem/ruby/common/DataBlock.hh @@ -108,8 +108,8 @@ void DataBlock::print(ostream& out) const { int size = RubySystem::getBlockSizeBytes(); out << "[ "; - for (int i = 0; i < size; i+=4) { - out << hex << *((uint32*)(&(m_data[i]))) << " "; + for (int i = 0; i < size; i++) { + out << setw(2) << setfill('0') << hex << "0x" << (int)m_data[i] << " "; } out << dec << "]" << flush; } diff --git a/src/mem/ruby/common/NetDest.cc b/src/mem/ruby/common/NetDest.cc index 390d5ee8e..32771235f 100644 --- a/src/mem/ruby/common/NetDest.cc +++ b/src/mem/ruby/common/NetDest.cc @@ -37,7 +37,6 @@ */ #include "mem/ruby/common/NetDest.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/protocol/Protocol.hh" NetDest::NetDest() diff --git a/src/mem/ruby/common/NetDest.hh b/src/mem/ruby/common/NetDest.hh index 20aac5108..1dcee7b7a 100644 --- a/src/mem/ruby/common/NetDest.hh +++ b/src/mem/ruby/common/NetDest.hh @@ -48,7 +48,6 @@ #include "mem/gems_common/Vector.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/MachineID.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Set.hh" #include "mem/protocol/MachineType.hh" diff --git a/src/mem/ruby/common/Set.cc b/src/mem/ruby/common/Set.cc index 2c64ad3bc..f7dd24356 100644 --- a/src/mem/ruby/common/Set.cc +++ b/src/mem/ruby/common/Set.cc @@ -41,7 +41,6 @@ #include "mem/ruby/common/Set.hh" #include "mem/ruby/system/System.hh" -#include "mem/ruby/config/RubyConfig.hh" #if __amd64__ || __LP64__ #define __64BITS__ @@ -512,7 +511,7 @@ void Set::setSize(int size) #endif // __32BITS__ // decide whether to use dynamic or static alloction - if(m_nArrayLen<=NUMBER_WORDS_PER_SET) { // constant defined in RubyConfig.hh + if(m_nArrayLen<=NUMBER_WORDS_PER_SET) { // constant defined in RubySystem.hh // its OK to use the static allocation, and it will // probably be faster (as m_nArrayLen is already in the // cache and they will probably share the same cache line) diff --git a/src/mem/ruby/common/Set.hh b/src/mem/ruby/common/Set.hh index 43fa5b45e..a22da914c 100644 --- a/src/mem/ruby/common/Set.hh +++ b/src/mem/ruby/common/Set.hh @@ -45,10 +45,10 @@ #ifndef SET_H #define SET_H +#include "mem/ruby/system/System.hh" #include "mem/ruby/common/Global.hh" #include "mem/gems_common/Vector.hh" #include "mem/ruby/system/NodeID.hh" -#include "mem/ruby/config/RubyConfig.hh" // gibson 05/20/05 // enum PresenceBit {NotPresent, Present}; diff --git a/src/mem/ruby/common/SubBlock.hh b/src/mem/ruby/common/SubBlock.hh index 3bc09e1d0..753666a17 100644 --- a/src/mem/ruby/common/SubBlock.hh +++ b/src/mem/ruby/common/SubBlock.hh @@ -37,7 +37,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Address.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/DataBlock.hh" #include "mem/gems_common/Vector.hh" diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb index 7dffb3957..d43e384e5 100644 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ b/src/mem/ruby/config/MI_example-homogeneous.rb @@ -10,10 +10,10 @@ require "cfg.rb" # default values -num_cores = 16 +num_cores = 2 L1_CACHE_SIZE_KB = 32 L1_CACHE_ASSOC = 8 -L1_CACHE_LATENCY = 2 +L1_CACHE_LATENCY = 1 num_memories = 2 memory_size_mb = 1024 NUM_DMA = 1 diff --git a/src/mem/ruby/config/RubyConfig.cc b/src/mem/ruby/config/RubyConfig.cc deleted file mode 100644 index 4ecec4da6..000000000 --- a/src/mem/ruby/config/RubyConfig.cc +++ /dev/null @@ -1,250 +0,0 @@ - -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * RubyConfig.cc - * - * Description: See RubyConfig.hh - * - * $Id$ - * - */ - -#include "mem/ruby/config/RubyConfig.hh" -//#include "mem/protocol/protocol_name.hh" -#include "mem/gems_common/util.hh" - -#define CONFIG_DEF_FILE "mem/ruby/config/config.hh" - -#define ERROR_MSG(MESSAGE)\ -{\ - cerr << "Fatal Error: in fn "\ - << __PRETTY_FUNCTION__ << " in "\ - << __FILE__ << ":"\ - << __LINE__ << ": "\ - << (MESSAGE) << endl << flush;\ - abort();\ -} - -// declare all configuration variables -#define PARAM_BOOL( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - bool RubyConfig::m_##NAME = DEFAULT_VALUE; -#define PARAM_STRING( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - const char* RubyConfig::m_##NAME = DEFAULT_VALUE; -#define PARAM_ULONG( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - uint64 RubyConfig::m_##NAME = DEFAULT_VALUE; -#define PARAM( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - int RubyConfig::m_##NAME = DEFAULT_VALUE; -#define PARAM_ARRAY( NAME, TYPE, DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - TYPE* RubyConfig::m_##NAME = NULL; -#define PARAM_ARRAY2D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - TYPE** RubyConfig::m_##NAME = NULL; -#define PARAM_ARRAY3D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, D3_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - TYPE*** RubyConfig::m_##NAME = NULL; -#include CONFIG_DEF_FILE -#undef PARAM_BOOL -#undef PARAM_STRING -#undef PARAM_ULONG -#undef PARAM -#undef PARAM_ARRAY -#undef PARAM_ARRAY2D -#undef PARAM_ARRAY3D - -#define CHECK_POWER_OF_2(N) { if (!is_power_of_2(N)) { ERROR_MSG(#N " must be a power of 2."); }} -#define CHECK_ZERO(N) { if (N != 0) { ERROR_MSG(#N " must be zero at initialization."); }} -#define CHECK_NON_ZERO(N) { if (N == 0) { ERROR_MSG(#N " must be non-zero."); }} - -uint32 RubyConfig::m_data_block_mask; - -void RubyConfig::reset() -{ - #define PARAM_BOOL( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = DEFAULT_VALUE; -#define PARAM_STRING( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = DEFAULT_VALUE; -#define PARAM_ULONG( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = DEFAULT_VALUE; -#define PARAM( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = DEFAULT_VALUE; -#define PARAM_ARRAY( NAME, TYPE, DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = new TYPE[DEFAULT_ARRAY_SIZE]; \ - for (int i=0; i<DEFAULT_ARRAY_SIZE; i++) \ - m_##NAME[i] = DEFAULT_VALUE; -#define PARAM_ARRAY2D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = new TYPE*[D1_DEFAULT_ARRAY_SIZE]; \ - for (int i=0; i<D1_DEFAULT_ARRAY_SIZE; i++) { \ - m_##NAME[i] = new TYPE[D2_DEFAULT_ARRAY_SIZE]; \ - for (int j=0; j<D2_DEFAULT_ARRAY_SIZE; j++) \ - m_##NAME[i][j] = DEFAULT_VALUE; \ - } -#define PARAM_ARRAY3D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, D3_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - m_##NAME = new TYPE**[D1_DEFAULT_ARRAY_SIZE]; \ - for (int i=0; i<D1_DEFAULT_ARRAY_SIZE; i++) { \ - m_##NAME[i] = new TYPE*[D2_DEFAULT_ARRAY_SIZE]; \ - for (int j=0; j<D2_DEFAULT_ARRAY_SIZE; j++) { \ - m_##NAME[i][j] = new TYPE[D3_DEFAULT_ARRAY_SIZE]; \ - for (int k=0; k<D3_DEFAULT_ARRAY_SIZE; k++) \ - m_##NAME[i][j][k] = DEFUALT_VALUE; \ - } \ - } -#include CONFIG_DEF_FILE -#undef PARAM_BOOL -#undef PARAM_STRING -#undef PARAM_ULONG -#undef PARAM -#undef PARAM_ARRAY -#undef PARAM_ARRAY2D -#undef PARAM_ARRAY3D -} - -void RubyConfig::init() -{ - /* - // MemoryControl: - CHECK_NON_ZERO(m_MEM_BUS_CYCLE_MULTIPLIER); - CHECK_NON_ZERO(m_BANKS_PER_RANK); - CHECK_NON_ZERO(m_RANKS_PER_DIMM); - CHECK_NON_ZERO(m_DIMMS_PER_CHANNEL); - CHECK_NON_ZERO(m_BANK_QUEUE_SIZE); - CHECK_NON_ZERO(m_BankBusyTime); - CHECK_NON_ZERO(m_MEM_CTL_LATENCY); - CHECK_NON_ZERO(m_REFRESH_PERIOD); - CHECK_NON_ZERO(m_BASIC_BUS_BUSY_TIME); - - CHECK_POWER_OF_2(m_BANKS_PER_RANK); - CHECK_POWER_OF_2(m_RANKS_PER_DIMM); - CHECK_POWER_OF_2(m_DIMMS_PER_CHANNEL); - - CHECK_NON_ZERO(m_MemorySizeBytes); - // CHECK_NON_ZERO(m_DATA_BLOCK_BYTES); - CHECK_NON_ZERO(m_NUM_PROCESSORS); - CHECK_NON_ZERO(m_ProcsPerChip); - - if (m_NUM_L2_BANKS == 0) { // defaults to number of ruby nodes - m_NUM_L2_BANKS = m_NUM_PROCESSORS; - } - if (m_NUM_MEMORIES == 0) { // defaults to number of ruby nodes - m_NUM_MEMORIES = m_NUM_PROCESSORS; - } - - CHECK_ZERO(m_MEMORY_SIZE_BITS); - CHECK_ZERO(m_NUM_PROCESSORS_BITS); - CHECK_ZERO(m_NUM_CHIP_BITS); - CHECK_ZERO(m_NUM_L2_BANKS_BITS); - CHECK_ZERO(m_NUM_MEMORIES_BITS); - CHECK_ZERO(m_PROCS_PER_CHIP_BITS); - CHECK_ZERO(m_NUM_L2_BANKS_PER_CHIP); - CHECK_ZERO(m_NUM_L2_BANKS_PER_CHIP_BITS); - CHECK_ZERO(m_NUM_MEMORIES_BITS); - CHECK_ZERO(m_MEMORY_MODULE_BLOCKS); - CHECK_ZERO(m_MEMORY_MODULE_BITS); - CHECK_ZERO(m_NUM_MEMORIES_PER_CHIP); - - CHECK_POWER_OF_2(m_MemorySizeBytes); - CHECK_POWER_OF_2(m_NUM_PROCESSORS); - CHECK_POWER_OF_2(m_NUM_L2_BANKS); - CHECK_POWER_OF_2(m_NUM_MEMORIES); - CHECK_POWER_OF_2(m_ProcsPerChip); - - assert(m_NUM_PROCESSORS >= m_ProcsPerChip); // obviously can't have less processors than procs/chip - m_NUM_CHIPS = m_NUM_PROCESSORS/m_ProcsPerChip; - assert(m_NUM_L2_BANKS >= m_NUM_CHIPS); // cannot have a single L2cache across multiple chips - - m_NUM_L2_BANKS_PER_CHIP = m_NUM_L2_BANKS/m_NUM_CHIPS; - - if (m_NUM_CHIPS > m_NUM_MEMORIES) { - m_NUM_MEMORIES_PER_CHIP = 1; // some chips have a memory, others don't - } else { - m_NUM_MEMORIES_PER_CHIP = m_NUM_MEMORIES/m_NUM_CHIPS; - } - - m_NUM_CHIP_BITS = log_int(m_NUM_CHIPS); - m_MEMORY_SIZE_BITS = log_int(m_MemorySizeBytes); - - m_data_block_mask = ~ (~0 << m_DATA_BLOCK_BITS); - - m_NUM_PROCESSORS_BITS = log_int(m_NUM_PROCESSORS); - m_NUM_L2_BANKS_BITS = log_int(m_NUM_L2_BANKS); - m_NUM_L2_BANKS_PER_CHIP_BITS = log_int(m_NUM_L2_BANKS_PER_CHIP); - m_NUM_MEMORIES_BITS = log_int(m_NUM_MEMORIES); - m_PROCS_PER_CHIP_BITS = log_int(m_ProcsPerChip); - - m_MEMORY_MODULE_BITS = m_MEMORY_SIZE_BITS - m_DATA_BLOCK_BITS - m_NUM_MEMORIES_BITS; - m_MEMORY_MODULE_BLOCKS = (int64(1) << m_MEMORY_MODULE_BITS); - - */ - - // Randomize the execution - // srandom(m_RandomSeed); -} - -static void print_parameters(ostream& out) -{ - -#define print_true(NAME) -#define print_false(NAME) \ - out << #NAME << ": " << RubyConfig::get##NAME () << endl - -#define PARAM(NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR) { print_##CUSTOM_ACCESSOR(NAME); } -#define PARAM_UINT(NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR) { print_##CUSTOM_ACCESSOR(NAME); } -#define PARAM_ULONG(NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR) { print_##CUSTOM_ACCESSOR(NAME); } -#define PARAM_BOOL(NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR) { print_##CUSTOM_ACCESSOR(NAME); } -#define PARAM_DOUBLE(NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR) { print_##CUSTOM_ACCESSOR(NAME); } -#define PARAM_STRING(NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR) { print_##CUSTOM_ACCESSOR(NAME); } -#define PARAM_ARRAY( NAME, TYPE, DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) { out << #NAME << ": ARRAY" << endl; } -#define PARAM_ARRAY2D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) { out << #NAME << ": ARRAY2D" << endl; } -#define PARAM_ARRAY3D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, D3_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) { out << #NAME << ": ARRAY3D" << endl; } -#include "mem/ruby/config/config.hh" -#undef PARAM -#undef PARAM_UINT -#undef PARAM_ULONG -#undef PARAM_BOOL -#undef PARAM_DOUBLE -#undef PARAM_STRING -#undef PARAM_ARRAY -#undef PARAM_ARRAY2D -#undef PARAM_ARRAY3D -} - -void RubyConfig::printConfiguration(ostream& out) { - out << "Ruby Configuration" << endl; - out << "------------------" << endl; - - //out << "protocol: " << CURRENT_PROTOCOL << endl; - out << "compiled_at: " << __TIME__ << ", " << __DATE__ << endl; - // out << "RUBY_DEBUG: " << bool_to_string(RUBY_DEBUG) << endl; - - char buffer[100]; - gethostname(buffer, 50); - out << "hostname: " << buffer << endl; - - print_parameters(out); -} - - diff --git a/src/mem/ruby/config/RubyConfig.hh b/src/mem/ruby/config/RubyConfig.hh deleted file mode 100644 index 8ad733385..000000000 --- a/src/mem/ruby/config/RubyConfig.hh +++ /dev/null @@ -1,229 +0,0 @@ - -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * RubyConfig.hh - * - * Description: This class has only static members and class methods, - * and thus should never need to be instantiated. - * - * $Id$ - * - */ - -#ifndef RUBYCONFIG_H -#define RUBYCONFIG_H - -#include <cstdlib> -#include <string> -#include <ostream> -#include <assert.h> - -#include "mem/ruby/common/TypeDefines.hh" - -// Set paramterization -/* - * This defines the number of longs (32-bits on 32 bit machines, - * 64-bit on 64-bit AMD machines) to use to hold the set... - * the default is 4, allowing 128 or 256 different members - * of the set. - * - * This should never need to be changed for correctness reasons, - * though increasing it will increase performance for larger - * set sizes at the cost of a (much) larger memory footprint - * - */ -const int NUMBER_WORDS_PER_SET = 4; - -using namespace std; - -class RubyConfig { -public: - - // CACHE BLOCK CONFIG VARIBLES - static uint32 dataBlockMask() { return m_data_block_mask; } - - static int numberOfDMA() { return 1; } - static int numberOfDMAPerChip() { return 1; } - static int DMATransitionsPerCycle() { return 1; } - - // SUPPORTED PHYSICAL MEMORY CONFIG VARIABLES - // static int memoryModuleBits() { return m_MEMORY_MODULE_BITS; } - // static int64 memoryModuleBlocks() { return m_MEMORY_MODULE_BLOCKS; } - - // defines the number of simics processors (power of 2) - // static int numberOfProcessors() { return m_NUM_PROCESSORS; } - // static int procsPerChipBits() { return m_PROCS_PER_CHIP_BITS; } - // static int numberOfProcsPerChip() { return m_ProcsPerChip; } - // static int numberOfChips() { return m_NUM_CHIPS; } - - // MACHINE INSTANIATION CONFIG VARIABLES - // ------------------------------------- - // L1 CACHE MACHINES - // defines the number of L1banks - idependent of ruby chips (power of 2) - // NOTE - no protocols currently supports L1s != processors, just a placeholder - - // DIRECTORY/MEMORY MACHINES - // defines the number of ruby memories - idependent of ruby chips (power of 2) - // static int memoryBits() { return m_NUM_MEMORIES_BITS; } - // static int numberOfDirectory() { return numberOfMemories(); } - // static int numberOfMemories() { return m_NUM_MEMORIES; } - // static int numberOfDirectoryPerChip() { return m_NUM_MEMORIES_PER_CHIP; } - // static int DirectoryTransitionsPerCycle() { return m_DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE; } - - // ---- END MACHINE SPECIFIC VARIABLES ---- - - // VARIABLE MEMORY RESPONSE LATENCY - // *** NOTE *** This is where variation is added to the simulation - // see Alameldeen et al. HPCA 2003 for further details -// static int getMemoryLatency() { return m_MEMORY_RESPONSE_LATENCY_MINUS_2+(random() % 5); } - - static void reset(); - static void init(); - static void printConfiguration(std::ostream& out); - - // Memory Controller - -// static int memBusCycleMultiplier () { return m_MEM_BUS_CYCLE_MULTIPLIER; } -/* static int banksPerRank () { return m_BANKS_PER_RANK; } - static int ranksPerDimm () { return m_RANKS_PER_DIMM; } - static int dimmsPerChannel () { return m_DIMMS_PER_CHANNEL; } - static int bankBit0 () { return m_BANK_BIT_0; } - static int rankBit0 () { return m_RANK_BIT_0; } - static int dimmBit0 () { return m_DIMM_BIT_0; } - static int bankQueueSize () { return m_BANK_QUEUE_SIZE; } - static int bankBusyTime () { return m_BankBusyTime; } - static int rankRankDelay () { return m_RANK_RANK_DELAY; } - static int readWriteDelay () { return m_READ_WRITE_DELAY; } - static int basicBusBusyTime () { return m_BASIC_BUS_BUSY_TIME; } - static int memCtlLatency () { return m_MEM_CTL_LATENCY; } - static int refreshPeriod () { return m_REFRESH_PERIOD; } - static int tFaw () { return m_TFAW; } - static int memRandomArbitrate () { return m_MEM_RANDOM_ARBITRATE; } - static int memFixedDelay () { return m_MEM_FIXED_DELAY; } -*/ - /* cache accessors */ - static int getCacheIDFromParams(int level, int num, string split_type) { - // TODO: this function - return 0; - } - -#define accessor_true( TYPE, NAME ) -#define accessor_false( TYPE, NAME ) \ - static TYPE get##NAME() { return m_##NAME; } \ - static void set##NAME(TYPE val) { m_##NAME = val; } - -#define array_accessor_true( TYPE, NAME, DEFAULT_ARRAY_SIZE ) -#define array_accessor_false( TYPE, NAME, DEFAULT_ARRAY_SIZE ) \ - static TYPE get##NAME(int idx) { \ - assert(m_##NAME != NULL); \ - return m_##NAME[idx]; \ - } \ - static void set##NAME(int idx, TYPE val) { \ - if(m_##NAME == NULL) { \ - assert(DEFAULT_ARRAY_SIZE > 0); \ - m_##NAME = new TYPE[DEFAULT_ARRAY_SIZE]; \ - } \ - m_##NAME[idx] = val; \ - } - -#define array2d_accessor_true( TYPE, NAME ) -#define array2d_accessor_false( TYPE, NAME ) \ - static TYPE get##NAME(int idx1, int idx2) { return m_##NAME[idx1][idx2]; } \ - static void set##NAME(int idx1, int idx2, TYPE val) { m_##NAME[idx1][idx2] = val; } - -#define array3d_accessor_true( TYPE, NAME ) -#define array3d_accessor_false( TYPE, NAME ) \ - static TYPE get##NAME(int idx1, int idx2, int idx3) { return m_##NAME[idx1][idx2][idx3]; } \ - static void set##NAME(int idx1, int idx2, int idx3, TYPE val) { m_##NAME[idx1][idx2][idx3] = val; } - -#define PARAM( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - accessor_##CUSTOM_ACCESSOR(int32,NAME) -#define PARAM_UINT( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - accessor_##CUSTOM_ACCESSOR(uint32,NAME) -#define PARAM_ULONG( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - accessor_##CUSTOM_ACCESSOR(uint64,NAME) -#define PARAM_BOOL( NAME, DEFAULT_VALUE,CUSTOM_ACCESSOR ) \ - accessor_##CUSTOM_ACCESSOR(bool,NAME) -#define PARAM_DOUBLE( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - accessor_##CUSTOM_ACCESSOR(double,NAME) -#define PARAM_STRING( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - accessor_##CUSTOM_ACCESSOR(const char*,NAME) -#define PARAM_ARRAY( NAME, TYPE, DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - array_accessor_##CUSTOM_ACCESSOR(TYPE, NAME, DEFAULT_ARRAY_SIZE) -#define PARAM_ARRAY2D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - array2d_accessor_##CUSTOM_ACCESSOR(TYPE, NAME) -#define PARAM_ARRAY3D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, D3_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - array3d_accessor_##CUSTOM_ACCESSOR(TYPE, NAME) -#include "mem/ruby/config/config.hh" -#undef PARAM -#undef PARAM_UINT -#undef PARAM_ULONG -#undef PARAM_BOOL -#undef PARAM_DOUBLE -#undef PARAM_STRING -#undef PARAM_ARRAY -#undef PARAM_ARRAY2D -#undef PARAM_ARRAY3D - -private: - static uint32 m_data_block_mask; - -#define PARAM( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static int32 m_##NAME; -#define PARAM_UINT( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static uint32 m_##NAME; -#define PARAM_ULONG( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static uint64 m_##NAME; -#define PARAM_BOOL( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static bool m_##NAME; -#define PARAM_DOUBLE( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static double m_##NAME; -#define PARAM_STRING( NAME, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static const char *m_##NAME; -#define PARAM_ARRAY( NAME, TYPE, DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static TYPE* m_##NAME; -#define PARAM_ARRAY2D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static TYPE** m_##NAME; -#define PARAM_ARRAY3D( NAME, TYPE, D1_DEFAULT_ARRAY_SIZE, D2_DEFAULT_ARRAY_SIZE, D3_DEFAULT_ARRAY_SIZE, DEFAULT_VALUE, CUSTOM_ACCESSOR ) \ - static TYPE*** m_##NAME; -#include "mem/ruby/config/config.hh" -#undef PARAM -#undef PARAM_UINT -#undef PARAM_ULONG -#undef PARAM_BOOL -#undef PARAM_DOUBLE -#undef PARAM_STRING -#undef PARAM_ARRAY -#undef PARAM_ARRAY2D -#undef PARAM_ARRAY3D - -}; - -#endif //RUBYCONFIG_H diff --git a/src/mem/ruby/config/SConscript b/src/mem/ruby/config/SConscript index 05ed2d27d..bf8352576 100644 --- a/src/mem/ruby/config/SConscript +++ b/src/mem/ruby/config/SConscript @@ -33,4 +33,3 @@ Import('*') if not env['RUBY']: Return() -Source('RubyConfig.cc') diff --git a/src/mem/ruby/eventqueue/RubyEventQueue.cc b/src/mem/ruby/eventqueue/RubyEventQueue.cc index 1a4159f1d..3adc0d22e 100644 --- a/src/mem/ruby/eventqueue/RubyEventQueue.cc +++ b/src/mem/ruby/eventqueue/RubyEventQueue.cc @@ -32,7 +32,6 @@ */ #include "mem/ruby/eventqueue/RubyEventQueue.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Consumer.hh" #include "mem/ruby/profiler/Profiler.hh" #include "mem/ruby/system/System.hh" diff --git a/src/mem/ruby/filters/AbstractBloomFilter.hh b/src/mem/ruby/filters/AbstractBloomFilter.hh index 7e37a6e06..89aeb25a6 100644 --- a/src/mem/ruby/filters/AbstractBloomFilter.hh +++ b/src/mem/ruby/filters/AbstractBloomFilter.hh @@ -39,7 +39,6 @@ #define ABSTRACT_BLOOM_FILTER_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" class AbstractBloomFilter { diff --git a/src/mem/ruby/filters/BlockBloomFilter.hh b/src/mem/ruby/filters/BlockBloomFilter.hh index 205b4172d..be9faa443 100644 --- a/src/mem/ruby/filters/BlockBloomFilter.hh +++ b/src/mem/ruby/filters/BlockBloomFilter.hh @@ -40,7 +40,6 @@ #include "mem/gems_common/Map.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/BulkBloomFilter.hh b/src/mem/ruby/filters/BulkBloomFilter.hh index 2dbdb6612..089531791 100644 --- a/src/mem/ruby/filters/BulkBloomFilter.hh +++ b/src/mem/ruby/filters/BulkBloomFilter.hh @@ -40,7 +40,6 @@ #include "mem/gems_common/Map.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/GenericBloomFilter.cc b/src/mem/ruby/filters/GenericBloomFilter.cc index f4198ef40..22c75d64c 100644 --- a/src/mem/ruby/filters/GenericBloomFilter.cc +++ b/src/mem/ruby/filters/GenericBloomFilter.cc @@ -36,7 +36,6 @@ */ #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/GenericBloomFilter.hh" diff --git a/src/mem/ruby/filters/GenericBloomFilter.hh b/src/mem/ruby/filters/GenericBloomFilter.hh index 4ff65f404..edee22f84 100644 --- a/src/mem/ruby/filters/GenericBloomFilter.hh +++ b/src/mem/ruby/filters/GenericBloomFilter.hh @@ -39,7 +39,6 @@ #define GENERIC_BLOOM_FILTER_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/H3BloomFilter.hh b/src/mem/ruby/filters/H3BloomFilter.hh index cde923b0b..360000540 100644 --- a/src/mem/ruby/filters/H3BloomFilter.hh +++ b/src/mem/ruby/filters/H3BloomFilter.hh @@ -42,7 +42,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/system/System.hh" #include "mem/ruby/profiler/Profiler.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/LSB_CountingBloomFilter.hh b/src/mem/ruby/filters/LSB_CountingBloomFilter.hh index 7a0f71fad..bfa2673fe 100644 --- a/src/mem/ruby/filters/LSB_CountingBloomFilter.hh +++ b/src/mem/ruby/filters/LSB_CountingBloomFilter.hh @@ -40,7 +40,6 @@ #include "mem/gems_common/Map.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/MultiBitSelBloomFilter.hh b/src/mem/ruby/filters/MultiBitSelBloomFilter.hh index 390b7c37c..360cbfdff 100644 --- a/src/mem/ruby/filters/MultiBitSelBloomFilter.hh +++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.hh @@ -42,7 +42,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/system/System.hh" #include "mem/ruby/profiler/Profiler.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/MultiGrainBloomFilter.hh b/src/mem/ruby/filters/MultiGrainBloomFilter.hh index 66a32ecd4..4e9bc70a2 100644 --- a/src/mem/ruby/filters/MultiGrainBloomFilter.hh +++ b/src/mem/ruby/filters/MultiGrainBloomFilter.hh @@ -40,7 +40,6 @@ #include "mem/gems_common/Map.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/filters/NonCountingBloomFilter.hh b/src/mem/ruby/filters/NonCountingBloomFilter.hh index 27045ebc9..fd23fbdf7 100644 --- a/src/mem/ruby/filters/NonCountingBloomFilter.hh +++ b/src/mem/ruby/filters/NonCountingBloomFilter.hh @@ -40,7 +40,6 @@ #include "mem/gems_common/Map.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/filters/AbstractBloomFilter.hh" diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index 5730d6591..17fbaab22 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -50,7 +50,6 @@ #include "mem/ruby/system/NodeID.hh" #include "mem/protocol/MessageSizeType.hh" #include "mem/ruby/system/System.hh" -#include "mem/ruby/config/RubyConfig.hh" class NetDest; class MessageBuffer; diff --git a/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh b/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh index 33af28a7e..0a450c002 100644 --- a/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh +++ b/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh @@ -40,7 +40,6 @@ #include "mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh" #include "mem/gems_common/util.hh" -#include "mem/ruby/config/RubyConfig.hh" class NetworkConfig { private: @@ -65,80 +64,11 @@ class NetworkConfig { m_using_network_testing = atoi(argv[i+1].c_str()); } } -// static bool isGarnetNetwork() {return RubyConfig::getUsingGarnetNetwork(); } -// static bool isDetailNetwork() {return RubyConfig::getUsingDetailNetwork(); } bool isNetworkTesting() {return m_using_network_testing; } int getFlitSize() {return m_flit_size; } int getNumPipeStages() {return m_number_of_pipe_stages; } int getVCsPerClass() {return m_vcs_per_class; } int getBufferSize() {return m_buffer_size; } - // This is no longer used. See config/rubyconfig.defaults to set Garnet parameters. - static void readNetConfig() - { - /* - string filename = "network/garnet-flexible-pipeline/"; - filename += NETCONFIG_DEFAULTS; - - if (g_SIMICS) { - filename = "../../../ruby/"+filename; - } - ifstream NetconfigFile( filename.c_str(), ios::in); - if(!NetconfigFile.is_open()) - { - cout << filename << endl; - cerr << "Network Configuration file cannot be opened\n"; - exit(1); - } - - string line = ""; - - while(!NetconfigFile.eof()) - { - getline(NetconfigFile, line, '\n'); - string var = string_split(line, ':'); - - if(!var.compare("RubyConfig::getUsingGarnetNetwork()")) - { - if(!line.compare("true")) - RubyConfig::getUsingGarnetNetwork() = true; - else - RubyConfig::getUsingGarnetNetwork() = false; - } - if(!var.compare("RubyConfig::getUsingDetailNetwork()")) - { - if(!line.compare("true")) - RubyConfig::getUsingDetailNetwork() = true; - else - RubyConfig::getUsingDetailNetwork() = false; - } - if(!var.compare("g_NETWORK_TESTING")) - { - if(!line.compare("true")) - g_NETWORK_TESTING = true; - else - g_NETWORK_TESTING = false; - } - if(!var.compare("RubyConfig::getFlitSize()")) - RubyConfig::getFlitSize() = atoi(line.c_str()); - if(!var.compare("RubyConfig::getNumberOfPipeStages()")) - RubyConfig::getNumberOfPipeStages() = atoi(line.c_str()); - if(!var.compare("RubyConfig::getVCSPerClass()")) - RubyConfig::getVCSPerClass() = atoi(line.c_str()); - if(!var.compare("RubyConfig::getBufferSize()")) - RubyConfig::getBufferSize() = atoi(line.c_str()); - } - NetconfigFile.close(); - */ - /* - cout << "RubyConfig::getUsingGarnetNetwork() = " << RubyConfig::getUsingGarnetNetwork() << endl; - cout << "RubyConfig::getUsingDetailNetwork() = " << RubyConfig::getUsingDetailNetwork() << endl; - cout << "g_NETWORK_TESTING = " << g_NETWORK_TESTING << endl; - cout << "RubyConfig::getFlitSize() = " << RubyConfig::getFlitSize() << endl; - cout << "RubyConfig::getNumberOfPipeStages() = " << RubyConfig::getNumberOfPipeStages() << endl; - cout << "RubyConfig::getVCSPerClass()= " << RubyConfig::getVCSPerClass() << endl; - cout << "RubyConfig::getBufferSize() = " << RubyConfig::getBufferSize() << endl; - */ - } }; diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc index b617ae939..02fc8db2a 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.cc +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc @@ -88,9 +88,7 @@ void PerfectSwitch::addOutPort(const Vector<MessageBuffer*>& out, const NetDest& m_out.insertAtBottom(out); m_routing_table.insertAtBottom(routing_table_entry); - // if (RubyConfig::getPrintTopology()) { - m_out_link_vec.insertAtBottom(out); - // } + m_out_link_vec.insertAtBottom(out); } void PerfectSwitch::clearRoutingTables() @@ -187,7 +185,6 @@ void PerfectSwitch::wakeup() assert(m_link_order.size() == m_routing_table.size()); assert(m_link_order.size() == m_out.size()); //changed by SS -// if (RubyConfig::getAdaptiveRouting()) { if (m_network_ptr->getAdaptiveRouting()) { if (m_network_ptr->isVNetOrdered(vnet)) { // Don't adaptively route diff --git a/src/mem/ruby/network/simple/PtToPtTopology.cc b/src/mem/ruby/network/simple/PtToPtTopology.cc deleted file mode 100644 index 9d178dbcc..000000000 --- a/src/mem/ruby/network/simple/PtToPtTopology.cc +++ /dev/null @@ -1,82 +0,0 @@ - -#include "mem/protocol/MachineType.hh" -#include "mem/ruby/network/simple/PtToPtTopology.hh" - -// one internal node per chip, point to point links between chips -void PtToPtTopology::construct() -{ - Vector< Vector < SwitchID > > nodePairs; // node pairs extracted from the file - Vector<int> latencies; // link latencies for each link extracted - Vector<int> bw_multis; // bw multipliers for each link extracted - - Vector < SwitchID > nodes; - nodes.setSize(2); - - // number of inter-chip switches - int numberOfChipSwitches = m_nodes/MachineType_base_level(MachineType_NUM); - // two switches per machine node grouping - // one intra-chip switch and one inter-chip switch per chip - for(int i=0; i<numberOfChipSwitches; i++){ - SwitchID new_switch = newSwitchID(); - new_switch = newSwitchID(); - } - - makeSwitchesPerChip(nodePairs, latencies, bw_multis, numberOfChipSwitches); - - // connect intra-chip switch to inter-chip switch - for (int chip = 0; chip < RubyConfig::getNumberOfChips(); chip++) { - - int latency = m_network_ptr->getOnChipLinkLatency(); // internal link latency - int bw_multiplier = 10; // external link bw multiplier of the global bandwidth - - nodes[0] = chip+m_nodes*2; - nodes[1] = chip+m_nodes*2+RubyConfig::getNumberOfChips(); - - // insert link - nodePairs.insertAtBottom(nodes); - latencies.insertAtBottom(latency); - bw_multis.insertAtBottom(bw_multiplier); - - // opposite direction link - Vector < SwitchID > otherDirectionNodes; - otherDirectionNodes.setSize(2); - otherDirectionNodes[0] = nodes[1]; - otherDirectionNodes[1] = nodes[0]; - nodePairs.insertAtBottom(otherDirectionNodes); - latencies.insertAtBottom(latency); - bw_multis.insertAtBottom(bw_multiplier); - } - - // point-to-point network between chips - for (int chip = 0; chip < RubyConfig::getNumberOfChips(); chip++) { - for (int other_chip = chip+1; other_chip < RubyConfig::getNumberOfChips(); other_chip++) { - - int latency = m_network_ptr->getOffChipLinkLatency(); // external link latency - int bw_multiplier = 1; // external link bw multiplier of the global bandwidth - - nodes[0] = chip+m_nodes*2+RubyConfig::getNumberOfChips(); - nodes[1] = other_chip+m_nodes*2+RubyConfig::getNumberOfChips(); - - // insert link - nodePairs.insertAtBottom(nodes); - latencies.insertAtBottom(latency); - bw_multis.insertAtBottom(bw_multiplier); - - // opposite direction link - Vector < SwitchID > otherDirectionNodes; - otherDirectionNodes.setSize(2); - otherDirectionNodes[0] = nodes[1]; - otherDirectionNodes[1] = nodes[0]; - nodePairs.insertAtBottom(otherDirectionNodes); - latencies.insertAtBottom(latency); - bw_multis.insertAtBottom(bw_multiplier); - } - } - - // add links - ASSERT(nodePairs.size() == latencies.size() && latencies.size() == bw_multis.size()) - for (int k = 0; k < nodePairs.size(); k++) { - ASSERT(nodePairs[k].size() == 2); - addLink(nodePairs[k][0], nodePairs[k][1], latencies[k], bw_multis[k]); - } -} diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc index e5cbfefd8..497c602d1 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.cc +++ b/src/mem/ruby/network/simple/SimpleNetwork.cc @@ -101,42 +101,7 @@ void SimpleNetwork::init(const vector<string> & argv) } m_topology_ptr->createLinks(false); // false because this isn't a reconfiguration } -/* -SimpleNetwork::SimpleNetwork(int nodes) -{ - m_nodes = MachineType_base_number(MachineType_NUM); - - m_virtual_networks = RubyConfig::getNumberOfVirtualNetworks(); - m_endpoint_switches.setSize(m_nodes); - - m_in_use.setSize(m_virtual_networks); - m_ordered.setSize(m_virtual_networks); - for (int i = 0; i < m_virtual_networks; i++) { - m_in_use[i] = false; - m_ordered[i] = false; - } - // Allocate to and from queues - m_toNetQueues.setSize(m_nodes); - m_fromNetQueues.setSize(m_nodes); - for (int node = 0; node < m_nodes; node++) { - m_toNetQueues[node].setSize(m_virtual_networks); - m_fromNetQueues[node].setSize(m_virtual_networks); - for (int j = 0; j < m_virtual_networks; j++) { - m_toNetQueues[node][j] = new MessageBuffer; - m_fromNetQueues[node][j] = new MessageBuffer; - } - } - - // Setup the network switches - m_topology_ptr = new Topology(this, m_nodes); - int number_of_switches = m_topology_ptr->numSwitches(); - for (int i=0; i<number_of_switches; i++) { - m_switch_ptr_vector.insertAtBottom(new Switch(i, this)); - } - m_topology_ptr->createLinks(false); // false because this isn't a reconfiguration -} -*/ void SimpleNetwork::reset() { for (int node = 0; node < m_nodes; node++) { diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc index ce69c47be..64cb2a33a 100644 --- a/src/mem/ruby/network/simple/Throttle.cc +++ b/src/mem/ruby/network/simple/Throttle.cc @@ -103,9 +103,7 @@ void Throttle::addLinks(const Vector<MessageBuffer*>& in_vec, const Vector<Messa } } - // if (RubyConfig::getPrintTopology()) { - m_out_link_vec.insertAtBottom(out_vec); - // } + m_out_link_vec.insertAtBottom(out_vec); } void Throttle::addVirtualNetwork(MessageBuffer* in_ptr, MessageBuffer* out_ptr) diff --git a/src/mem/ruby/network/simple/Topology.cc b/src/mem/ruby/network/simple/Topology.cc index 3535f790b..dedf79d58 100644 --- a/src/mem/ruby/network/simple/Topology.cc +++ b/src/mem/ruby/network/simple/Topology.cc @@ -40,7 +40,6 @@ #include "mem/ruby/common/NetDest.hh" #include "mem/ruby/network/Network.hh" #include "mem/protocol/TopologyType.hh" -//#include "mem/ruby/config/RubyConfig.hh" #include "mem/gems_common/util.hh" #include "mem/protocol/MachineType.hh" #include "mem/protocol/Protocol.hh" @@ -294,82 +293,6 @@ void Topology::createLinks(bool isReconfiguration) } } } -/* -void Topology::makeSwitchesPerChip(Vector< Vector < SwitchID > > &nodePairs, Vector<int> &latencies, Vector<int> &bw_multis, int numberOfChipSwitches) -{ - - Vector < SwitchID > nodes; // temporary buffer - nodes.setSize(2); - - Vector<bool> endpointConnectionExist; // used to ensure all endpoints are connected to the network - endpointConnectionExist.setSize(m_nodes); - // initialize endpoint check vector - for (int k = 0; k < endpointConnectionExist.size(); k++) { - endpointConnectionExist[k] = false; - } - - Vector<int> componentCount; - componentCount.setSize(MachineType_NUM); - for (MachineType mType = MachineType_FIRST; mType < MachineType_NUM; ++mType) { - componentCount[mType] = 0; - } - - // components to/from network links - // TODO: drh5: bring back chips!!! - for (int chip = 0; chip < RubyConfig::getNumberOfChips(); chip++) { - for (MachineType mType = MachineType_FIRST; mType < MachineType_NUM; ++mType) { - for (int component = 0; component < MachineType_base_count(mType); component++) { - - int latency = -1; - int bw_multiplier = -1; // internal link bw multiplier of the global bandwidth - if (mType != MachineType_Directory) { - latency = RubyConfig::getOnChipLinkLatency(); // internal link latency - bw_multiplier = 10; // internal link bw multiplier of the global bandwidth - } else { - latency = RubyConfig::getNetworkLinkLatency(); // local memory latency - bw_multiplier = 1; // local memory link bw multiplier of the global bandwidth - } - nodes[0] = MachineType_base_number(mType)+componentCount[mType]; - nodes[1] = chip+m_nodes*2; // this is the chip's internal switch id # - - // insert link - nodePairs.insertAtBottom(nodes); - latencies.insertAtBottom(latency); - bw_multis.insertAtBottom(bw_multiplier); - //bw_multis.insertAtBottom(componentCount[mType]+MachineType_base_number((MachineType)mType)); - - // opposite direction link - Vector < SwitchID > otherDirectionNodes; - otherDirectionNodes.setSize(2); - otherDirectionNodes[0] = nodes[1]; - otherDirectionNodes[1] = nodes[0]+m_nodes; - nodePairs.insertAtBottom(otherDirectionNodes); - latencies.insertAtBottom(latency); - bw_multis.insertAtBottom(bw_multiplier); - - assert(!endpointConnectionExist[nodes[0]]); - endpointConnectionExist[nodes[0]] = true; - componentCount[mType]++; - } - } - } - - // make sure all enpoints are connected in the soon to be created network - for (int k = 0; k < endpointConnectionExist.size(); k++) { - if (endpointConnectionExist[k] == false) { - cerr << "Error: Unconnected Endpoint: " << k << endl; - exit(1); - } - } - - // secondary check to ensure we saw the correct machine counts - for (MachineType mType = MachineType_FIRST; mType < MachineType_NUM; ++mType) { - assert(componentCount[mType] == MachineType_base_count((MachineType)mType)); - } - -} -*/ - SwitchID Topology::newSwitchID() { diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh index 5bb0cc545..2761d6de8 100644 --- a/src/mem/ruby/profiler/AccessTraceForAddress.hh +++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh @@ -38,7 +38,6 @@ #define ACCESSTRACEFORADDRESS_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/AccessModeType.hh" diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc index 516e73ae9..fad8d51b4 100644 --- a/src/mem/ruby/profiler/CacheProfiler.cc +++ b/src/mem/ruby/profiler/CacheProfiler.cc @@ -48,7 +48,7 @@ CacheProfiler::CacheProfiler(string description) { m_description = description; m_requestTypeVec_ptr = new Vector<int>; - m_requestTypeVec_ptr->setSize(int(GenericRequestType_NUM)); + m_requestTypeVec_ptr->setSize(int(CacheRequestType_NUM)); clearStats(); } @@ -70,30 +70,22 @@ void CacheProfiler::printStats(ostream& out) const out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl; double trans_executed = double(g_system_ptr->getProfiler()->getTotalTransactionsExecuted()); - double inst_executed = double(g_system_ptr->getProfiler()->getTotalInstructionsExecuted()); out << description << "_misses_per_transaction: " << double(m_misses) / trans_executed << endl; - out << description << "_misses_per_instruction: " << double(m_misses) / inst_executed << endl; - out << description << "_instructions_per_misses: "; - if (m_misses > 0) { - out << inst_executed / double(m_misses) << endl; - } else { - out << "NaN" << endl; - } out << endl; int requests = 0; - for(int i=0; i<int(GenericRequestType_NUM); i++) { + for(int i=0; i<int(CacheRequestType_NUM); i++) { requests += m_requestTypeVec_ptr->ref(i); } assert(m_misses == requests); if (requests > 0) { - for(int i=0; i<int(GenericRequestType_NUM); i++){ + for(int i=0; i<int(CacheRequestType_NUM); i++){ if (m_requestTypeVec_ptr->ref(i) > 0) { - out << description << "_request_type_" << GenericRequestType_to_string(GenericRequestType(i)) << ": " + out << description << "_request_type_" << CacheRequestType_to_string(CacheRequestType(i)) << ": " << (100.0 * double((m_requestTypeVec_ptr->ref(i)))) / double(requests) << "%" << endl; } @@ -116,7 +108,7 @@ void CacheProfiler::printStats(ostream& out) const void CacheProfiler::clearStats() { - for(int i=0; i<int(GenericRequestType_NUM); i++) { + for(int i=0; i<int(CacheRequestType_NUM); i++) { m_requestTypeVec_ptr->ref(i) = 0; } m_requestSize.clear(); @@ -130,7 +122,7 @@ void CacheProfiler::clearStats() } } -void CacheProfiler::addStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit) +void CacheProfiler::addStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit) { m_misses++; diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh index 00beeb484..6d7c163cb 100644 --- a/src/mem/ruby/profiler/CacheProfiler.hh +++ b/src/mem/ruby/profiler/CacheProfiler.hh @@ -44,7 +44,7 @@ #include "mem/ruby/common/Histogram.hh" #include "mem/protocol/AccessModeType.hh" #include "mem/protocol/PrefetchBit.hh" -#include "mem/protocol/GenericRequestType.hh" +#include "mem/protocol/CacheRequestType.hh" template <class TYPE> class Vector; @@ -60,7 +60,7 @@ public: void printStats(ostream& out) const; void clearStats(); - void addStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit); + void addStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit); void print(ostream& out) const; private: diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc index e067d3a0f..e8aa7edf9 100644 --- a/src/mem/ruby/profiler/Profiler.cc +++ b/src/mem/ruby/profiler/Profiler.cc @@ -98,31 +98,6 @@ Profiler::Profiler(const string & name) m_stats_period = 1000000; // Default m_periodic_output_file_ptr = &cerr; -//changed by SS -/* - // for MemoryControl: - m_memReq = 0; - m_memBankBusy = 0; - m_memBusBusy = 0; - m_memReadWriteBusy = 0; - m_memDataBusBusy = 0; - m_memTfawBusy = 0; - m_memRefresh = 0; - m_memRead = 0; - m_memWrite = 0; - m_memWaitCycles = 0; - m_memInputQ = 0; - m_memBankQ = 0; - m_memArbWait = 0; - m_memRandBusy = 0; - m_memNotOld = 0; - - - int totalBanks = RubyConfig::banksPerRank() - * RubyConfig::ranksPerDimm() - * RubyConfig::dimmsPerChannel(); - m_memBankCount.setSize(totalBanks); -*/ } Profiler::~Profiler() @@ -405,9 +380,9 @@ void Profiler::printStats(ostream& out, bool short_stats) out << endl; - m_L1D_cache_profiler_ptr->printStats(out); - m_L1I_cache_profiler_ptr->printStats(out); - m_L2_cache_profiler_ptr->printStats(out); + // m_L1D_cache_profiler_ptr->printStats(out); + // m_L1I_cache_profiler_ptr->printStats(out); + // m_L2_cache_profiler_ptr->printStats(out); out << endl; @@ -798,25 +773,6 @@ void Profiler::clearStats() m_ruby_start = g_eventQueue_ptr->getTime(); } -void Profiler::addPrimaryStatSample(const CacheMsg& msg, NodeID id) -{ - if (Protocol::m_TwoLevelCache) { - if (msg.getType() == CacheRequestType_IFETCH) { - addL1IStatSample(msg, id); - } else { - addL1DStatSample(msg, id); - } - // profile the address after an L1 miss (outside of the processor for CMP) - if (Protocol::m_CMP) { - addAddressTraceSample(msg, id); - } - } else { - addL2StatSample(CacheRequestType_to_GenericRequestType(msg.getType()), - msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id); - addAddressTraceSample(msg, id); - } -} - void Profiler::profileConflictingRequests(const Address& addr) { assert(addr == line_address(addr)); @@ -830,39 +786,6 @@ void Profiler::profileConflictingRequests(const Address& addr) m_conflicting_map_ptr->add(addr, current_time); } -void Profiler::addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id) -{ - addSecondaryStatSample(CacheRequestType_to_GenericRequestType(requestType), type, msgSize, pfBit, id); -} - -void Profiler::addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id) -{ - addL2StatSample(requestType, type, msgSize, pfBit, id); -} - -void Profiler::addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id) -{ - m_perProcTotalMisses[id]++; - if (type == AccessModeType_SupervisorMode) { - m_perProcSupervisorMisses[id]++; - } else { - m_perProcUserMisses[id]++; - } - m_L2_cache_profiler_ptr->addStatSample(requestType, type, msgSize, pfBit); -} - -void Profiler::addL1DStatSample(const CacheMsg& msg, NodeID id) -{ - m_L1D_cache_profiler_ptr->addStatSample(CacheRequestType_to_GenericRequestType(msg.getType()), - msg.getAccessMode(), msg.getSize(), msg.getPrefetch()); -} - -void Profiler::addL1IStatSample(const CacheMsg& msg, NodeID id) -{ - m_L1I_cache_profiler_ptr->addStatSample(CacheRequestType_to_GenericRequestType(msg.getType()), - msg.getAccessMode(), msg.getSize(), msg.getPrefetch()); -} - void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id) { if (msg.getType() != CacheRequestType_IFETCH) { @@ -870,7 +793,7 @@ void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id) // Note: The following line should be commented out if you want to // use the special profiling that is part of the GS320 protocol - // NOTE: Unless PROFILE_HOT_LINES or RubyConfig::getProfileAllInstructions() are enabled, nothing will be profiled by the AddressProfiler + // NOTE: Unless PROFILE_HOT_LINES is enabled, nothing will be profiled by the AddressProfiler m_address_profiler_ptr->addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false); } } @@ -1080,30 +1003,6 @@ int64 Profiler::getTotalTransactionsExecuted() const } -// The following case statement converts CacheRequestTypes to GenericRequestTypes -// allowing all profiling to be done with a single enum type instead of slow strings -GenericRequestType Profiler::CacheRequestType_to_GenericRequestType(const CacheRequestType& type) { - switch (type) { - case CacheRequestType_LD: - return GenericRequestType_LD; - break; - case CacheRequestType_ST: - return GenericRequestType_ST; - break; - case CacheRequestType_ATOMIC: - return GenericRequestType_ATOMIC; - break; - case CacheRequestType_IFETCH: - return GenericRequestType_IFETCH; - break; - case CacheRequestType_NULL: - return GenericRequestType_NULL; - break; - default: - ERROR_MSG("Unexpected cache request type"); - } -} - void Profiler::rubyWatch(int id){ //int rn_g1 = 0;//SIMICS_get_register_number(id, "g1"); uint64 tr = 0;//SIMICS_read_register(id, rn_g1); diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 4731c7138..4549e3ea7 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -58,7 +58,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/protocol/GenericMachineType.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Histogram.hh" #include "mem/ruby/common/Consumer.hh" #include "mem/protocol/AccessModeType.hh" @@ -127,9 +126,6 @@ public: AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } - void addPrimaryStatSample(const CacheMsg& msg, NodeID id); - void addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id); - void addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id); void addAddressTraceSample(const CacheMsg& msg, NodeID id); void profileRequest(const string& requestStr); @@ -207,12 +203,6 @@ public: private: //added by SS vector<string> m_memory_control_names; - // Private Methods - void addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id); - void addL1DStatSample(const CacheMsg& msg, NodeID id); - void addL1IStatSample(const CacheMsg& msg, NodeID id); - - GenericRequestType CacheRequestType_to_GenericRequestType(const CacheRequestType& type); // Private copy constructor and assignment operator Profiler(const Profiler& obj); diff --git a/src/mem/ruby/profiler/StoreTrace.hh b/src/mem/ruby/profiler/StoreTrace.hh index a71636364..5cdf7ce41 100644 --- a/src/mem/ruby/profiler/StoreTrace.hh +++ b/src/mem/ruby/profiler/StoreTrace.hh @@ -38,7 +38,6 @@ #define StoreTrace_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Histogram.hh" diff --git a/src/mem/ruby/recorder/Tracer.cc b/src/mem/ruby/recorder/Tracer.cc index 5b1e4274b..a0a3b22b7 100644 --- a/src/mem/ruby/recorder/Tracer.cc +++ b/src/mem/ruby/recorder/Tracer.cc @@ -37,7 +37,6 @@ #include "mem/ruby/eventqueue/RubyEventQueue.hh" #include "mem/gems_common/PrioHeap.hh" #include "mem/ruby/system/System.hh" -#include "mem/ruby/config/RubyConfig.hh" //added by SS Tracer::Tracer(const string & name) @@ -130,8 +129,8 @@ int Tracer::playbackTrace(string filename) ok = record.input(in); // Clear the statistics after warmup -/* if (counter == RubyConfig::getTraceWarmupLength()) { - cout << "Clearing stats after warmup of length " << RubyConfig::getTraceWarmupLength() << endl; +/* if (counter == m_warmup_length) { + cout << "Clearing stats after warmup of length " << m_warmup_length << endl; g_system_ptr->clearStats(); } */ diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh index 9ece7ae65..cd3cdbe48 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -35,7 +35,6 @@ #define COMPONENTMAPPINGFNS_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/MachineID.hh" #include "mem/ruby/common/Address.hh" @@ -62,77 +61,6 @@ #define MACHINETYPE_L3CACHE_ENUM MachineType_NUM #endif -/* -#ifdef MACHINETYPE_PersistentArbiter -#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_PersistentArbiter -#else -#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_NUM -#endif -*/ -/* -inline MachineID map_Address_to_L2Cache(const Address & addr) -{ - int L2bank = 0; - MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), - RubySystem::getBlockSizeBits() + RubyConfig::getNumberOfCachesPerLevel(2)-1); - mach.num = L2bank; - return mach; -} - -// input parameter is the base ruby node of the L1 cache -// returns a value between 0 and total_L2_Caches_within_the_system -inline -MachineID map_L1CacheMachId_to_L2Cache(const Address& addr, MachineID L1CacheMachId) -{ - return map_Address_to_L2Cache(addr); - - int L2bank = 0; - MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; - - if (RubyConfig::L2CachePerChipBits() > 0) { - if (RubyConfig::getMAP_L2BANKS_TO_LOWEST_BITS()) { - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), - RubySystem::getBlockSizeBits()+RubyConfig::L2CachePerChipBits()-1); - } else { - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS(), - RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS()+RubyConfig::L2CachePerChipBits()-1); - } - } - - assert(L2bank < RubyConfig::numberOfL2CachePerChip()); - assert(L2bank >= 0); - - mach.num = RubyConfig::L1CacheNumToL2Base(L1CacheMachId.num)*RubyConfig::numberOfL2CachePerChip() // base # - + L2bank; // bank # - assert(mach.num < RubyConfig::numberOfL2Cache()); - return mach; - -} - - -// used to determine the correct L2 bank -// input parameter is the base ruby node of the L2 cache -// returns a value between 0 and total_L2_Caches_within_the_system - -inline -MachineID map_L2ChipId_to_L2Cache(const Address& addr, NodeID L2ChipId) -{ - return map_Address_to_L2Cache(addr); - - assert(L2ChipId < RubyConfig::numberOfChips()); - - int L2bank = 0; - MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), - RubySystem::getBlockSizeBits() + RubyConfig::numberOfCachesPerLevel(2)-1); - mach.num = L2bank; - return mach - -} - */ - - // used to determine the home directory // returns a value between 0 and total_directories_within_the_system inline @@ -157,29 +85,8 @@ MachineID map_Address_to_DMA(const Address & addr) return dma; } -/* -inline -NetDest getOtherLocalL1IDs(MachineID L1) -{ - int start = (L1.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip(); - NetDest ret; - - assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); - - for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { - if (i != L1.num) { - MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; - ret.add( mach ); - } - } - - return ret; -} -*/ - extern inline NodeID machineIDToNodeID(MachineID machID) { - // return machID.num%RubyConfig::numberOfChips(); return machID.num; } @@ -193,22 +100,7 @@ extern inline NodeID L1CacheMachIDToProcessorNum(MachineID machID) assert(machID.type == MachineType_L1Cache); return machID.num; } -/* -extern inline NodeID L2CacheMachIDToChipID(MachineID machID) -{ - assert(machID.type == MACHINETYPE_L2CACHE_ENUM); - int L2bank = machID.num; - int banks_seen = 0; - for (int i=0;i<RubyConfig::getNumberOfChips();i++) { - for (int j=0;j<RubyConfig::getNumberOfCachesPerLevelPerChip(2,i);j++) { - if (banks_seen == L2bank) - return i; - banks_seen++; - } - } - assert(0); -} -*/ + extern inline MachineID getL1MachineID(NodeID L1RubyNode) { MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode}; diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc index 6a12af385..883edd3c8 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc @@ -79,33 +79,11 @@ void profile_sharing(const Address& addr, AccessType type, NodeID requestor, con g_system_ptr->getProfiler()->profileSharing(addr, type, requestor, sharers, owner); } -void profile_miss(const CacheMsg& msg, NodeID id) -{ - // CMP profile address after L1 misses, not L2 - ASSERT (!Protocol::m_CMP); - g_system_ptr->getProfiler()->addAddressTraceSample(msg, id); - - g_system_ptr->getProfiler()->profileConflictingRequests(msg.getLineAddress()); - - g_system_ptr->getProfiler()->addSecondaryStatSample(msg.getType(), - msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id); -} - -void profile_L1Cache_miss(const CacheMsg& msg, NodeID id) -{ - g_system_ptr->getProfiler()->addPrimaryStatSample(msg, id); -} - void profileMsgDelay(int virtualNetwork, int delayCycles) { g_system_ptr->getProfiler()->profileMsgDelay(virtualNetwork, delayCycles); } -void profile_L2Cache_miss(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID nodeID) -{ - g_system_ptr->getProfiler()->addSecondaryStatSample(requestType, type, msgSize, pfBit, nodeID); -} - void profile_token_retry(const Address& addr, AccessType type, int count) { g_system_ptr->getProfiler()->getAddressProfiler()->profileRetry(addr, type, count); diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index d8692951e..e4e20c99a 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -43,7 +43,6 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/MachineID.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/protocol/CacheMsg.hh" #include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/CacheRequestType.hh" @@ -112,19 +111,6 @@ extern inline int MessageSizeTypeToInt(MessageSizeType size_type) return MessageSizeType_to_int(size_type); } -/* -extern inline int numberOfNodes() -{ - return RubyConfig::numberOfChips(); -} -*/ -/* -extern inline int numberOfL1CachePerChip() -{ - return RubyConfig::getNumberOfCachesPerLevelPerChip(1,0); -} -*/ - extern inline bool long_enough_ago(Time event) { return ((get_time() - event) > 200); @@ -171,40 +157,6 @@ extern inline Time time_to_int(Time time) return time; } -/* -extern inline bool getFilteringEnabled() -{ - return RubyConfig::getFilteringEnabled(); -} - - -extern inline int getRetryThreshold() -{ - return RubyConfig::getRetryThreshold(); -} - -extern inline int getFixedTimeoutLatency() -{ - return RubyConfig::getFixedTimeoutLatency(); -} - -extern inline int N_tokens() -{ - // return N+1 to handle clean writeback - return RubyConfig::getProcsPerChip() + 1; - // return 1; -} - -extern inline bool distributedPersistentEnabled() -{ - return RubyConfig::getDistributedPersistentEnabled(); -} - -extern inline bool getDynamicTimeoutEnabled() -{ - return RubyConfig::getDynamicTimeoutEnabled(); -} -*/ // Appends an offset to an address extern inline Address setOffset(Address addr, int offset) { diff --git a/src/mem/ruby/system/AbstractMemOrCache.hh b/src/mem/ruby/system/AbstractMemOrCache.hh index 641c117de..845ce66ea 100644 --- a/src/mem/ruby/system/AbstractMemOrCache.hh +++ b/src/mem/ruby/system/AbstractMemOrCache.hh @@ -11,7 +11,6 @@ #define ABSTRACT_MEM_OR_CACHE_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" class AbstractMemOrCache { diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 625d5ce59..cfaa229a5 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -52,6 +52,8 @@ #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" #include "mem/ruby/system/System.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" +#include "mem/ruby/profiler/CacheProfiler.hh" +#include "mem/protocol/CacheMsg.hh" #include <vector> class CacheMemory { @@ -111,6 +113,8 @@ public: // Set this address to most recently used void setMRU(const Address& address); + void profileMiss(const CacheMsg & msg); + void getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes ); void setMemoryValue(const Address& addr, char* value, @@ -123,6 +127,8 @@ public: void print(ostream& out) const; void printData(ostream& out) const; + void printStats(ostream& out) const; + private: // Private Methods @@ -154,51 +160,15 @@ private: AbstractReplacementPolicy *m_replacementPolicy_ptr; + CacheProfiler* m_profiler_ptr; + int m_cache_num_sets; int m_cache_num_set_bits; int m_cache_assoc; static Vector< CacheMemory* > m_all_caches; }; -/* -inline -CacheMemory* CacheMemory::getCache(int cache_id) -{ - assert(cache_id < RubyConfig::getNumberOfCaches()); - if (m_all_caches[cache_id] == NULL) { - cerr << "ERROR: Tried to obtain CacheMemory that hasn't been created yet." << endl; - assert(0); - } - return m_all_caches[cache_id]; -} - -inline -CacheMemory* CacheMemory::createCache(int level, int num, char split_type_c, AbstractCacheEntry* (*entry_factory)()) -{ - string split_type; - switch(split_type_c) { - case 'i': - split_type = "instruction"; break; - case 'd': - split_type = "data"; break; - default: - split_type = "unified"; break; - } - int cache_id = RubyConfig::getCacheIDFromParams(level, num, split_type); - assert(cache_id < RubyConfig::getNumberOfCaches()); - if (m_all_caches.size() == 0) { - m_all_caches.setSize(RubyConfig::getNumberOfCaches()); - for (int i=0; i<m_all_caches.size(); i++) - m_all_caches[i] = NULL; - } - string type = RubyConfig::getCacheType(cache_id); - if ( type == "SetAssociativeCache" ) { - m_all_caches[cache_id] = new CacheMemory(cache_id, entry_factory); - } - return m_all_caches[cache_id]; -} -*/ // Output operator declaration //ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj); @@ -220,6 +190,7 @@ inline CacheMemory::CacheMemory(const string & name) : m_cache_name(name) { + m_profiler_ptr = new CacheProfiler(name); } inline @@ -266,43 +237,7 @@ void CacheMemory::init(const vector<string> & argv) } } } -/* -inline -CacheMemory::CacheMemory(int cache_id, AbstractCacheEntry* (*entry_factory)()) -{ - string split_type; - - m_cache_id = cache_id; - m_entry_factory = entry_factory; - - m_cache_num_set_bits = RubyConfig::getNumberOfCacheSetBits(cache_id); - m_cache_num_sets = RubyConfig::getNumberOfCacheSets(cache_id); - m_cache_assoc = RubyConfig::getCacheAssoc(cache_id); - split_type = RubyConfig::getCacheSplitType(cache_id); - m_is_instruction_only_cache = m_is_data_only_cache = false; - if (split_type == "instruction") - m_is_instruction_only_cache = true; - else if (split_type == "data") - m_is_data_only_cache = true; - else - assert(split_type == "unified"); - if(RubyConfig::getCacheReplacementPolicy(cache_id) == "PSEUDO_LRU") - m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc); - else if(RubyConfig::getCacheReplacementPolicy(cache_id) == "LRU") - m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc); - else - assert(false); - - m_cache.setSize(m_cache_num_sets); - for (int i = 0; i < m_cache_num_sets; i++) { - m_cache[i].setSize(m_cache_assoc); - for (int j = 0; j < m_cache_assoc; j++) { - m_cache[i][j] = m_entry_factory(); - } - } -} -*/ inline CacheMemory::~CacheMemory() { @@ -570,6 +505,13 @@ void CacheMemory::setMRU(const Address& address) } inline +void CacheMemory::profileMiss(const CacheMsg & msg) +{ + m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(), + msg.getSize(), msg.getPrefetch()); +} + +inline void CacheMemory::recordCacheContents(CacheRecorder& tr) const { for (int i = 0; i < m_cache_num_sets; i++) { @@ -620,6 +562,12 @@ void CacheMemory::printData(ostream& out) const } inline +void CacheMemory::printStats(ostream& out) const +{ + m_profiler_ptr->printStats(out); +} + +inline void CacheMemory::getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes ){ AbstractCacheEntry& entry = lookup(line_address(addr)); diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index 8f7b1c912..58ec7bb45 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -29,6 +29,7 @@ void DMASequencer::init(const vector<string> & argv) m_mandatory_q_ptr = m_controller->getMandatoryQueue(); m_is_busy = false; + m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); } int64_t DMASequencer::makeRequest(const RubyRequest & request) @@ -53,7 +54,7 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request) assert(0); } - assert(!m_is_busy); + assert(!m_is_busy); // only support one outstanding DMA request m_is_busy = true; active_request.start_paddr = paddr; @@ -66,14 +67,15 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request) DMARequestMsg msg; msg.getPhysicalAddress() = Address(paddr); + msg.getLineAddress() = line_address(msg.getPhysicalAddress()); msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ; - msg.getOffset() = paddr & RubyConfig::dataBlockMask(); - msg.getLen() = (msg.getOffset() + len) < RubySystem::getBlockSizeBytes() ? - (msg.getOffset() + len) : + msg.getOffset() = paddr & m_data_block_mask; + msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ? + len : RubySystem::getBlockSizeBytes() - msg.getOffset(); if (write) { msg.getType() = DMARequestType_WRITE; - msg.getDataBlk().setData(data, 0, msg.getLen()); + msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen()); } else { msg.getType() = DMARequestType_READ; } @@ -94,15 +96,20 @@ void DMASequencer::issueNext() } DMARequestMsg msg; - msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed); - assert((msg.getPhysicalAddress().getAddress() & RubyConfig::dataBlockMask()) == 0); + msg.getPhysicalAddress() = Address(active_request.start_paddr + + active_request.bytes_completed); + assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0); + msg.getLineAddress() = line_address(msg.getPhysicalAddress()); msg.getOffset() = 0; - msg.getType() = active_request.write ? DMARequestType_WRITE : DMARequestType_READ; - msg.getLen() = active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? - active_request.len - active_request.bytes_completed : - RubySystem::getBlockSizeBytes(); + msg.getType() = (active_request.write ? DMARequestType_WRITE : + DMARequestType_READ); + msg.getLen() = (active_request.len - + active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? + active_request.len - active_request.bytes_completed : + RubySystem::getBlockSizeBytes()); if (active_request.write) { - msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen()); + msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], + 0, msg.getLen()); msg.getType() = DMARequestType_WRITE; } else { msg.getType() = DMARequestType_READ; @@ -117,8 +124,10 @@ void DMASequencer::dataCallback(const DataBlock & dblk) int len = active_request.bytes_issued - active_request.bytes_completed; int offset = 0; if (active_request.bytes_completed == 0) - offset = active_request.start_paddr & RubyConfig::dataBlockMask(); - memcpy(&active_request.data[active_request.bytes_completed], dblk.getData(offset, len), len); + offset = active_request.start_paddr & m_data_block_mask; + assert( active_request.write == false ); + memcpy(&active_request.data[active_request.bytes_completed], + dblk.getData(offset, len), len); issueNext(); } diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index 2665549e3..1f60b95ec 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -41,6 +41,7 @@ private: int m_version; AbstractController* m_controller; bool m_is_busy; + uint64_t m_data_block_mask; DMARequest active_request; int num_active_requests; MessageBuffer* m_mandatory_q_ptr; diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc index 294d57de2..b279d21af 100644 --- a/src/mem/ruby/system/DirectoryMemory.cc +++ b/src/mem/ruby/system/DirectoryMemory.cc @@ -39,7 +39,6 @@ #include "mem/ruby/system/System.hh" #include "mem/ruby/system/DirectoryMemory.hh" #include "mem/ruby/slicc_interface/RubySlicc_Util.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/gems_common/util.hh" diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh index 9d647822c..90c9273e5 100644 --- a/src/mem/ruby/system/PerfectCacheMemory.hh +++ b/src/mem/ruby/system/PerfectCacheMemory.hh @@ -42,7 +42,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/gems_common/Map.hh" #include "mem/protocol/AccessPermission.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/slicc_interface/AbstractChip.hh" diff --git a/src/mem/ruby/system/ProcessorInterface.hh b/src/mem/ruby/system/ProcessorInterface.hh deleted file mode 100644 index d76e29f65..000000000 --- a/src/mem/ruby/system/ProcessorInterface.hh +++ /dev/null @@ -1,45 +0,0 @@ - -struct ProcessorRequest { - vector<CacheRequest*> cache_requests; -}; - -class ProcessorInterface { - -public: - - void read_atomic(const Address & paddr, void* data, int len) { - assert(paddr.getLineAddress() + RubyConfig::dataBlockBytes() >= paddr + len); - // for now, atomics can't span two blocks. Maybe fix this later - } - - void read(const Address & paddr, const Address & rip, AccessModeType atype, void* data, const int len) { - - // create the CacheRequests - ProcessorRequest* this_request = new ProcessorRequest; - Address split_addr = paddr; - int len_remaining = len; - while (split_addr.getAddress() < paddr.getAddress() + len) { - int split_len = (split_addr.getAddress() + len_remaining <= split_addr.getLineAddress() + RubyConfig::dataBlockBytes()) ? - len_remaining : - RubyConfig::dataBlockBytes() - split_addr.getOffset(); - CacheRequest creq = new CacheRequest( line_address(split_addr), - split_addr, - CacheRequestType_LD, - rip, - atype, - split_len, - PretchBit_No, - laddr, - 0); // SMT thread id); - this_request->cache_requests.push_back(creq); - split_addr += split_len; - len_remaining -= split_len; - } - outstanding_requests.push_back(this_request); - - } - -private: - vector<ProcessorRequest*> outstanding_requests; - Sequencer* m_sequencer; -}; diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 1587aa5fa..693e931aa 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -490,183 +490,3 @@ void Sequencer::checkCoherence(const Address& addr) { #endif } -/* -bool Sequencer::getRubyMemoryValue(const Address& addr, char* value, - unsigned int size_in_bytes ) -{ - bool found = false; - const Address lineAddr = line_address(addr); - DataBlock data; - PhysAddress paddr(addr); - DataBlock* dataPtr = &data; - - MachineID l2_mach = map_L2ChipId_to_L2Cache(addr, m_chip_ptr->getID() ); - int l2_ver = l2_mach.num%RubyConfig::numberOfL2CachePerChip(); - - if (Protocol::m_TwoLevelCache) { - if(Protocol::m_CMP){ - assert(n->m_L2Cache_L2cacheMemory_vec[l2_ver] != NULL); - } - else{ - assert(n->m_L1Cache_cacheMemory_vec[m_version] != NULL); - } - } - - if (n->m_L1Cache_L1IcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_IFETCH, dataPtr)){ - n->m_L1Cache_L1IcacheMemory_vec[m_version]->getMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (n->m_L1Cache_L1DcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L1Cache_L1DcacheMemory_vec[m_version]->getMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (Protocol::m_CMP && n->m_L2Cache_L2cacheMemory_vec[l2_ver]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L2Cache_L2cacheMemory_vec[l2_ver]->getMemoryValue(addr, value, size_in_bytes); - found = true; - // } else if (n->TBE_TABLE_MEMBER_VARIABLE->isPresent(lineAddr)){ -// ASSERT(n->TBE_TABLE_MEMBER_VARIABLE->isPresent(lineAddr)); -// L1Cache_TBE tbeEntry = n->TBE_TABLE_MEMBER_VARIABLE->lookup(lineAddr); - -// int offset = addr.getOffset(); -// for(int i=0; i<size_in_bytes; ++i){ -// value[i] = tbeEntry.getDataBlk().getByte(offset + i); -// } - -// found = true; - } else { - // Address not found - //cout << " " << m_chip_ptr->getID() << " NOT IN CACHE, Value at Directory is: " << (int) value[0] << endl; - n = dynamic_cast<Chip*>(g_system_ptr->getChip(map_Address_to_DirectoryNode(addr)/RubyConfig::numberOfDirectoryPerChip())); - int dir_version = map_Address_to_DirectoryNode(addr)%RubyConfig::numberOfDirectoryPerChip(); - for(unsigned int i=0; i<size_in_bytes; ++i){ - int offset = addr.getOffset(); - value[i] = n->m_Directory_directory_vec[dir_version]->lookup(lineAddr).m_DataBlk.getByte(offset + i); - } - // Address not found - //WARN_MSG("Couldn't find address"); - //WARN_EXPR(addr); - found = false; - } - return true; -} - -bool Sequencer::setRubyMemoryValue(const Address& addr, char *value, - unsigned int size_in_bytes) { - char test_buffer[64]; - - // idea here is that coherent cache should find the - // latest data, the update it - bool found = false; - const Address lineAddr = line_address(addr); - PhysAddress paddr(addr); - DataBlock data; - DataBlock* dataPtr = &data; - Chip* n = dynamic_cast<Chip*>(m_chip_ptr); - - MachineID l2_mach = map_L2ChipId_to_L2Cache(addr, m_chip_ptr->getID() ); - int l2_ver = l2_mach.num%RubyConfig::numberOfL2CachePerChip(); - - assert(n->m_L1Cache_L1IcacheMemory_vec[m_version] != NULL); - assert(n->m_L1Cache_L1DcacheMemory_vec[m_version] != NULL); - if (Protocol::m_TwoLevelCache) { - if(Protocol::m_CMP){ - assert(n->m_L2Cache_L2cacheMemory_vec[l2_ver] != NULL); - } - else{ - assert(n->m_L1Cache_cacheMemory_vec[m_version] != NULL); - } - } - - if (n->m_L1Cache_L1IcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_IFETCH, dataPtr)){ - n->m_L1Cache_L1IcacheMemory_vec[m_version]->setMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (n->m_L1Cache_L1DcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L1Cache_L1DcacheMemory_vec[m_version]->setMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (Protocol::m_CMP && n->m_L2Cache_L2cacheMemory_vec[l2_ver]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L2Cache_L2cacheMemory_vec[l2_ver]->setMemoryValue(addr, value, size_in_bytes); - found = true; - } else { - // Address not found - n = dynamic_cast<Chip*>(g_system_ptr->getChip(map_Address_to_DirectoryNode(addr)/RubyConfig::numberOfDirectoryPerChip())); - int dir_version = map_Address_to_DirectoryNode(addr)%RubyConfig::numberOfDirectoryPerChip(); - for(unsigned int i=0; i<size_in_bytes; ++i){ - int offset = addr.getOffset(); - n->m_Directory_directory_vec[dir_version]->lookup(lineAddr).m_DataBlk.setByte(offset + i, value[i]); - } - found = false; - } - - if (found){ - found = getRubyMemoryValue(addr, test_buffer, size_in_bytes); - assert(found); - if(value[0] != test_buffer[0]){ - WARN_EXPR((int) value[0]); - WARN_EXPR((int) test_buffer[0]); - ERROR_MSG("setRubyMemoryValue failed to set value."); - } - } - - return true; -} -*/ -/* - -void -Sequencer::rubyMemAccess(const uint64 paddr, char* data, const int len, const AccessType type) -{ - if ( type == AccessType_Read || type == AccessType_Write ) { - // need to break up the packet data - uint64 guest_ptr = paddr; - Vector<DataBlock*> datablocks; - while (paddr + len != guest_ptr) { - Address addr(guest_ptr); - Address line_addr = line_address(addr); - - int bytes_copied; - if (addr.getOffset() == 0) { - bytes_copied = (guest_ptr + RubyConfig::dataBlockBytes() > paddr + len)? - (paddr + len - guest_ptr): - RubyConfig::dataBlockBytes(); - } else { - bytes_copied = RubyConfig::dataBlockBytes() - addr.getOffset(); - if (guest_ptr + bytes_copied > paddr + len) - bytes_copied = paddr + len - guest_ptr; - } - - // first we need to find all data blocks that have to be updated for a write - // and the highest block for a read - for(int i=0;i<RubyConfig::numberOfProcessors();i++) { - if (Protocol::m_TwoLevelCache){ - if(m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[i]->isTagPresent(line_address(addr))) - datablocks.insertAtBottom(&m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[i]->lookup(line_addr).getDataBlk()); - if(m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[i]->isTagPresent(line_address(addr))) - datablocks.insertAtBottom(&m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[i]->lookup(line_addr).getDataBlk()); - } else { - if(m_chip_ptr->m_L1Cache_cacheMemory_vec[i]->isTagPresent(line_address(addr))) - datablocks.insertAtBottom(&m_chip_ptr->m_L1Cache_cacheMemory_vec[i]->lookup(line_addr).getDataBlk()); - } - } - if (Protocol::m_TwoLevelCache){ - int l2_bank = map_L2ChipId_to_L2Cache(addr, 0).num; // TODO: ONLY WORKS WITH CMP!!! - if (m_chip_ptr->m_L2Cache_L2cacheMemory_vec[l2_bank]->isTagPresent(line_address(Address(paddr)))) { - datablocks.insertAtBottom(&m_chip_ptr->m_L2Cache_L2cacheMemory_vec[l2_bank]->lookup(addr).getDataBlk()); - } - } - assert(dynamic_cast<Chip*>(m_chip_ptr)->m_Directory_directory_vec.size() > map_Address_to_DirectoryNode(addr)); - DirectoryMemory* dir = dynamic_cast<Chip*>(m_chip_ptr)->m_Directory_directory_vec[map_Address_to_DirectoryNode(addr)]; - Directory_Entry& entry = dir->lookup(line_addr); - datablocks.insertAtBottom(&entry.getDataBlk()); - - if (pkt->isRead()){ - datablocks[0]->copyData(pkt_data, addr.getOffset(), bytes_copied); - } else {// pkt->isWrite() { - for (int i=0;i<datablocks.size();i++) - datablocks[i]->setData(pkt_data, addr.getOffset(), bytes_copied); - } - - guest_ptr += bytes_copied; - pkt_data += bytes_copied; - datablocks.clear(); - } -} - -*/ diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 254f5a092..9b55e9781 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -38,7 +38,6 @@ #define SEQUENCER_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Consumer.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/AccessModeType.hh" diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc index e922d0bbf..2c24c9ade 100644 --- a/src/mem/ruby/system/System.cc +++ b/src/mem/ruby/system/System.cc @@ -278,16 +278,7 @@ RubySystem::RubySystem(const vector <RubyObjConf> & sys_conf) RubySystem::~RubySystem() { - /* - for (int i=0; i < MachineType_base_level(MachineType_NUM); i++) { - for (int j=0; j < RubyConfig::getNumberOfControllersPerType(i); j++ ) { - delete m_controllers[i][j]; - } - } - delete m_network_ptr; - delete m_profiler_ptr; - delete m_tracer_ptr; - */ + } void RubySystem::printSystemConfig(ostream & out) @@ -307,8 +298,6 @@ void RubySystem::printSystemConfig(ostream & out) void RubySystem::printConfig(ostream& out) { out << "\n================ Begin RubySystem Configuration Print ================\n\n"; - // RubyConfig::printConfiguration(out); - // out << endl; printSystemConfig(out); for (map<string, AbstractController*>::const_iterator it = m_controllers.begin(); it != m_controllers.end(); it++) { @@ -346,6 +335,10 @@ void RubySystem::printStats(ostream& out) m_profiler_ptr->printStats(out); m_network_ptr->printStats(out); + for (map<string, CacheMemory*>::const_iterator it = m_caches.begin(); + it != m_caches.end(); it++) { + (*it).second->printStats(out); + } for (map<string, AbstractController*>::const_iterator it = m_controllers.begin(); it != m_controllers.end(); it++) { (*it).second->printStats(out); @@ -367,19 +360,7 @@ void RubySystem::clearStats() const void RubySystem::recordCacheContents(CacheRecorder& tr) const { - /* - for (int i = 0; i < m_chip_vector.size(); i++) { - for (int m_version = 0; m_version < RubyConfig::numberOfProcsPerChip(); m_version++) { - if (Protocol::m_TwoLevelCache) { - m_chip_vector[i]->m_L1Cache_L1IcacheMemory_vec[m_version]->setAsInstructionCache(true); - m_chip_vector[i]->m_L1Cache_L1DcacheMemory_vec[m_version]->setAsInstructionCache(false); - } else { - m_chip_vector[i]->m_L1Cache_cacheMemory_vec[m_version]->setAsInstructionCache(false); - } - } - m_chip_vector[i]->recordCacheContents(tr); - } - */ + } #ifdef CHECK_COHERENCE diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh index 8cbeb2b0e..dbf4dbc78 100644 --- a/src/mem/ruby/system/System.hh +++ b/src/mem/ruby/system/System.hh @@ -61,6 +61,20 @@ class DirectoryMemory; class Topology; class MemoryControl; +/* + * This defines the number of longs (32-bits on 32 bit machines, + * 64-bit on 64-bit AMD machines) to use to hold the set... + * the default is 4, allowing 128 or 256 different members + * of the set. + * + * This should never need to be changed for correctness reasons, + * though increasing it will increase performance for larger + * set sizes at the cost of a (much) larger memory footprint + * + */ +const int NUMBER_WORDS_PER_SET = 4; + + struct RubyObjConf { string type; string name; diff --git a/src/mem/ruby/tester/RaceyPseudoThread.cc b/src/mem/ruby/tester/RaceyPseudoThread.cc index c681c0a7e..7d23b7286 100644 --- a/src/mem/ruby/tester/RaceyPseudoThread.cc +++ b/src/mem/ruby/tester/RaceyPseudoThread.cc @@ -21,7 +21,6 @@ */ #include "mem/ruby/tester/RaceyPseudoThread.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/tester/RaceyDriver.hh" #include "gzstream.hh" diff --git a/src/mem/slicc/ast/EnqueueStatementAST.cc b/src/mem/slicc/ast/EnqueueStatementAST.cc index 744dfe1eb..8be0378c9 100644 --- a/src/mem/slicc/ast/EnqueueStatementAST.cc +++ b/src/mem/slicc/ast/EnqueueStatementAST.cc @@ -77,7 +77,7 @@ void EnqueueStatementAST::generate(string& code, Type* return_type_ptr) const code += ".enqueue(out_msg"; if (getPairs().exist("latency")) { - code += ", RubyConfig::get" + getPairs().lookup("latency") + "()"; + code += ", m_LATENCY_" + getPairs().lookup("latency"); } code += ");\n"; diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc index 64c7ae24a..e042f9aa0 100644 --- a/src/mem/slicc/symbols/StateMachine.cc +++ b/src/mem/slicc/symbols/StateMachine.cc @@ -314,7 +314,7 @@ void StateMachine::printControllerH(ostream& out, string component) out << " NodeID m_version;" << endl; out << " Network* m_net_ptr;" << endl; out << " MachineID m_machineID;" << endl; - out << " static " << component << "_Profiler s_profiler;" << endl; + out << " " << component << "_Profiler s_profiler;" << endl; out << " static int m_num_controllers;" << endl; // internal function protypes @@ -392,10 +392,6 @@ void StateMachine::printControllerC(ostream& out, string component) out << "stringstream " << component << "_" << "transitionComment;" << endl; out << "#define APPEND_TRANSITION_COMMENT(str) (" << component << "_" << "transitionComment << str)" << endl; - out << "/** \\brief static profiler defn */" << endl; - out << component << "_Profiler " << component << "_Controller::s_profiler;" << endl; - out << endl; - out << "/** \\brief constructor */" << endl; out << component << "_Controller::" << component // << "_Controller(int version, Network* net_ptr)" << endl; @@ -478,6 +474,7 @@ void StateMachine::printControllerC(ostream& out, string component) // initialize objects out << " // Objects" << endl; + out << " s_profiler.setVersion(m_version);" << endl; for(int i=0; i < numObjects(); i++) { const Var* var = m_objs[i]; if (!var->existPair("network")) { @@ -722,11 +719,12 @@ void StateMachine::printControllerC(ostream& out, string component) out << "{" << endl; out << " DEBUG_MSG(GENERATED_COMP, HighPrio,\"executing\");" << endl; //added by SS -//instead of rubyconfig:: --> it should point to m_latency... +//it should point to m_latency... //so I should change the string output of this lookup - string c_code_string = action.lookupPair("c_code"); + string c_code_string = action.lookupPair("c_code"); +/* size_t found = c_code_string.find("RubyConfig::get"); if (found!=string::npos){ //found --> replace it with local access @@ -744,7 +742,7 @@ void StateMachine::printControllerC(ostream& out, string component) } } } - +*/ // add here: if (strncmp(component.c_str(), "L1Cache", 7) == 0) { if (c_code_string.find("writeCallback") != string::npos) { @@ -1116,6 +1114,7 @@ void StateMachine::printProfilerH(ostream& out, string component) out << "class " << component << "_Profiler {" << endl; out << "public:" << endl; out << " " << component << "_Profiler();" << endl; + out << " void setVersion(int version);" << endl; out << " void countTransition(" << component << "_State state, " << component << "_Event event);" << endl; out << " void possibleTransition(" << component << "_State state, " << component << "_Event event);" << endl; out << " void dumpStats(ostream& out) const;" << endl; @@ -1124,6 +1123,7 @@ void StateMachine::printProfilerH(ostream& out, string component) out << " int m_counters[" << component << "_State_NUM][" << component << "_Event_NUM];" << endl; out << " int m_event_counters[" << component << "_Event_NUM];" << endl; out << " bool m_possible[" << component << "_State_NUM][" << component << "_Event_NUM];" << endl; + out << " int m_version;" << endl; out << "};" << endl; out << "#endif // " << component << "_PROFILER_H" << endl; } @@ -1150,6 +1150,12 @@ void StateMachine::printProfilerC(ostream& out, string component) out << " }" << endl; out << "}" << endl; + // setVersion + out << "void " << component << "_Profiler::setVersion(int version)" << endl; + out << "{" << endl; + out << " m_version = version;" << endl; + out << "}" << endl; + // Clearstats out << "void " << component << "_Profiler::clearStats()" << endl; out << "{" << endl; @@ -1180,7 +1186,7 @@ void StateMachine::printProfilerC(ostream& out, string component) // dumpStats out << "void " << component << "_Profiler::dumpStats(ostream& out) const" << endl; out << "{" << endl; - out << " out << \" --- " << component << " ---\" << endl;" << endl; + out << " out << \" --- " << component << " \" << m_version << \" ---\" << endl;" << endl; out << " out << \" - Event Counts -\" << endl;" << endl; out << " for (int event = 0; event < " << component << "_Event_NUM; event++) {" << endl; out << " int count = m_event_counters[event];" << endl; diff --git a/src/mem/slicc/symbols/Type.cc b/src/mem/slicc/symbols/Type.cc index 75f72af02..eb53cc7b9 100644 --- a/src/mem/slicc/symbols/Type.cc +++ b/src/mem/slicc/symbols/Type.cc @@ -583,7 +583,6 @@ void Type::printEnumC(string path) const out << endl; out << "#include \"mem/protocol/" << type_name << ".hh\"" << endl; if (m_isMachineType) { - out << "#include \"mem/ruby/config/RubyConfig.hh\"" << endl; out << "#include \"mem/protocol/ControllerFactory.hh\"" << endl; for( int i = 0; i<size; i++ ) { out << "#include \"mem/protocol/" << m_enum_vec[i] << "_Controller.hh\"" << endl; @@ -675,7 +674,7 @@ void Type::printEnumC(string path) const out << " }" << endl; out << "}" << endl; - out << "/** \\brief returns the machine type for each base vector index used by NetDest and RubyConfig" << endl; + out << "/** \\brief returns the machine type for each base vector index used by NetDest" << endl; out << " * " << endl; out << " * \\return the MachineTYpe" << endl; out << " */" << endl; @@ -762,29 +761,6 @@ void Type::printEnumC(string path) const out << endl; -// out << "/** \\brief returns the total number of components for each machine" << endl; -// out << " * \\return the total number of components for each machine" << endl; -// out << " */" << endl; -// out << "int " << type_name << "_chip_count(const " << type_name << "& obj, int chip_id)" << endl; -// out << "{" << endl; -// out << " switch(obj) {" << endl; - -// // For each field -// for( int i = 0; i<size; i++ ) { -// out << " case " << type_name << "_" << m_enum_vec[i] << ":" << endl; -// out << " return RubyConfig::getNumberOfControllersPerTypePerChip(MachineType_base_level(MachineType_" << m_enum_vec[i] << "), chip_id);" << endl; -// } - -// // total num -// out << " case " << type_name << "_NUM:" << endl; -// // Trailer -// out << " default:" << endl; -// out << " ERROR_MSG(\"Invalid range for type " << type_name << "\");" << endl; -// out << " return -1;" << endl; -// out << " }" << endl; -// out << "}" << endl; - - } // Write the file diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index f3de8638c..455d5bfef 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -376,27 +376,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/13/2009 11:35:28 +Real time: Jul/19/2009 15:34:56 Profiler Stats -------------- -Elapsed_time_in_seconds: 2022 -Elapsed_time_in_minutes: 33.7 -Elapsed_time_in_hours: 0.561667 -Elapsed_time_in_days: 0.0234028 +Elapsed_time_in_seconds: 2553 +Elapsed_time_in_minutes: 42.55 +Elapsed_time_in_hours: 0.709167 +Elapsed_time_in_days: 0.0295486 -Virtual_time_in_seconds: 2021.58 -Virtual_time_in_minutes: 33.693 -Virtual_time_in_hours: 0.56155 -Virtual_time_in_days: 0.56155 +Virtual_time_in_seconds: 2552.07 +Virtual_time_in_minutes: 42.5345 +Virtual_time_in_hours: 0.708908 +Virtual_time_in_days: 0.708908 -Ruby_current_time: 31820151 +Ruby_current_time: 31814465 Ruby_start_time: 1 -Ruby_cycles: 31820150 +Ruby_cycles: 31814464 mbytes_resident: 150.715 -mbytes_total: 1502.57 -resident_ratio: 0.10031 +mbytes_total: 1502.59 +resident_ratio: 0.100309 Total_misses: 0 total_misses: 0 [ 0 0 0 0 0 0 0 0 ] @@ -404,8 +404,8 @@ user_misses: 0 [ 0 0 0 0 0 0 0 0 ] supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] instruction_executed: 8 [ 1 1 1 1 1 1 1 1 ] -ruby_cycles_executed: 254561208 [ 31820151 31820151 31820151 31820151 31820151 31820151 31820151 31820151 ] -cycles_per_instruction: 3.18202e+07 [ 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 3.18202e+07 ] +ruby_cycles_executed: 254515720 [ 31814465 31814465 31814465 31814465 31814465 31814465 31814465 31814465 ] +cycles_per_instruction: 3.18145e+07 [ 3.18145e+07 3.18145e+07 3.18145e+07 3.18145e+07 3.18145e+07 3.18145e+07 3.18145e+07 3.18145e+07 ] misses_per_thousand_instructions: 0 [ 0 0 0 0 0 0 0 0 ] transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] @@ -414,65 +414,29 @@ instructions_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - Memory control: - memory_total_requests: 1388715 - memory_reads: 694429 - memory_writes: 694183 - memory_refreshes: 66292 - memory_total_request_delays: 425693933 - memory_delays_per_request: 306.538 - memory_delays_in_input_queue: 88373140 - memory_delays_behind_head_of_bank_queue: 256981406 - memory_delays_stalled_at_head_of_bank_queue: 80339387 - memory_stalls_for_bank_busy: 12139365 + memory_total_requests: 1388468 + memory_reads: 694293 + memory_writes: 694043 + memory_refreshes: 66280 + memory_total_request_delays: 426683648 + memory_delays_per_request: 307.305 + memory_delays_in_input_queue: 87635910 + memory_delays_behind_head_of_bank_queue: 258531255 + memory_delays_stalled_at_head_of_bank_queue: 80516483 + memory_stalls_for_bank_busy: 12165032 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 24629486 - memory_stalls_for_arbitration: 15620225 - memory_stalls_for_bus: 20514147 + memory_stalls_for_anti_starvation: 24715948 + memory_stalls_for_arbitration: 15631815 + memory_stalls_for_bus: 20544794 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 5993792 - memory_stalls_for_read_read_turnaround: 1442372 - accesses_per_bank: 43402 43980 43964 43739 43710 43747 43506 43532 43547 43624 43342 43416 43254 43432 43341 43250 43106 42949 43234 43065 43413 43176 43043 43299 43329 43484 43093 43217 43454 43098 43443 43526 + memory_stalls_for_read_write_turnaround: 6014461 + memory_stalls_for_read_read_turnaround: 1444433 + accesses_per_bank: 43313 43907 44020 43692 43588 43833 44012 43419 43405 43526 43433 43395 43597 43293 43128 43416 43269 43509 43139 43194 43419 43535 43304 43225 43160 43143 43188 43018 42886 43118 43257 43127 Busy Controller Counts: -L1Cache-0:1 L1Cache-1:0 L1Cache-2:0 L1Cache-3:1 L1Cache-4:0 L1Cache-5:1 L1Cache-6:0 L1Cache-7:1 +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:1 L1Cache-6:0 L1Cache-7:0 Directory-0:0 DMA-0:0 @@ -480,17 +444,17 @@ DMA-0:0 Busy Bank Count:0 L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 4 max: 138 count: 2136422 average: 36.2389 | standard deviation: 28.1349 | 22715 77616 157380 245532 298784 278507 205386 131825 40504 9739 11231 15799 21344 28483 36739 45490 53163 60852 65683 67036 63571 56722 46590 35450 25175 16208 9482 5035 2491 1142 469 171 72 29 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +L2TBE_usage: [binsize: 4 max: 134 count: 2136875 average: 36.3375 | standard deviation: 28.2827 | 23454 78361 154838 242576 298777 279946 206526 134119 41748 9990 11123 15179 20545 27694 35924 44642 53192 60320 64615 65514 62260 55913 47160 36948 26700 17667 10728 5693 2725 1295 483 159 53 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 747605 average: 11.7824 | standard deviation: 3.40678 | 0 997 2734 5419 9667 16098 24151 33909 44874 55287 64490 70115 72444 71660 68466 64469 142825 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 748260 average: 11.8029 | standard deviation: 3.40671 | 0 1091 2889 5609 9615 15772 23675 33311 44184 55041 64248 70323 72503 72248 68934 64870 143947 ] store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 20830 count: 747528 average: 3863.27 | standard deviation: 2352.2 | 21197 1955 3662 6575 8813 8466 7701 8621 10114 11916 13705 13785 12268 13061 16083 17253 16187 16362 17426 17486 17061 18610 19198 16898 15842 17763 18373 16107 15849 16696 15292 13911 14597 15479 13585 11985 12812 13601 11408 10656 11428 10946 9456 9397 9955 9349 7687 8042 8461 7253 6426 6656 6870 5596 5078 5702 5311 4329 4222 4357 4026 3301 3344 3639 2991 2681 2723 2690 2146 1949 2075 1944 1561 1439 1490 1277 1090 1076 1107 889 733 862 724 613 514 543 494 370 351 377 357 283 268 267 209 179 175 209 158 130 155 108 86 75 90 81 51 69 45 48 52 44 45 41 24 34 36 25 24 25 23 22 18 11 11 15 10 11 9 11 10 10 12 14 6 5 5 3 4 2 2 1 0 3 1 3 0 1 3 0 2 0 3 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 20500 count: 485823 average: 3861.58 | standard deviation: 2351.5 | 13803 1269 2389 4255 5726 5414 5043 5609 6667 7717 8866 8913 7980 8569 10484 11191 10527 10646 11361 11421 11081 12192 12531 10960 10325 11558 11878 10584 10224 10716 9989 9010 9440 10102 8765 7759 8324 8806 7395 6843 7441 7190 6180 6082 6482 6098 5072 5224 5537 4711 4121 4343 4393 3630 3273 3660 3469 2812 2734 2825 2660 2125 2150 2328 1950 1773 1783 1766 1382 1289 1318 1248 994 946 961 846 730 719 747 605 453 544 463 398 333 331 302 252 222 246 235 182 168 169 148 122 112 138 102 78 101 65 53 55 51 53 37 44 24 35 37 25 29 23 16 20 22 15 17 19 13 11 13 8 8 12 4 7 7 10 6 8 7 9 2 3 3 3 4 1 2 1 0 3 1 2 0 0 2 0 1 0 2 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 128 max: 20830 count: 261705 average: 3866.39 | standard deviation: 2353.52 | 7394 686 1273 2320 3087 3052 2658 3012 3447 4199 4839 4872 4288 4492 5599 6062 5660 5716 6065 6065 5980 6418 6667 5938 5517 6205 6495 5523 5625 5980 5303 4901 5157 5377 4820 4226 4488 4795 4013 3813 3987 3756 3276 3315 3473 3251 2615 2818 2924 2542 2305 2313 2477 1966 1805 2042 1842 1517 1488 1532 1366 1176 1194 1311 1041 908 940 924 764 660 757 696 567 493 529 431 360 357 360 284 280 318 261 215 181 212 192 118 129 131 122 101 100 98 61 57 63 71 56 52 54 43 33 20 39 28 14 25 21 13 15 19 16 18 8 14 14 10 7 6 10 11 5 3 3 3 6 4 2 1 4 2 5 5 4 2 2 0 0 1 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 20559 count: 748171 average: 3866.31 | standard deviation: 2352.95 | 21417 1969 3723 6729 8868 8455 7676 8627 10203 11965 13796 13743 11900 13009 16352 17532 16234 15941 17304 16977 16916 18538 19194 16531 16082 17521 18191 15886 15702 16749 15616 14095 14916 15648 13793 11856 12863 13378 11663 10762 11443 11095 9691 9387 10128 9009 7817 8024 8496 7458 6302 6700 6887 5633 5066 5555 5357 4326 4220 4651 4016 3318 3403 3600 3054 2613 2796 2637 2141 2011 2128 1973 1548 1420 1531 1276 1047 1080 1093 914 741 749 732 584 493 515 525 388 363 345 325 251 268 277 202 190 183 189 147 117 143 119 90 93 91 82 60 58 58 49 51 48 39 28 34 36 30 17 16 21 24 23 12 17 16 9 12 16 12 13 7 4 7 8 7 8 5 7 5 8 4 4 6 5 3 3 2 1 4 1 2 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 128 max: 20559 count: 486192 average: 3864.95 | standard deviation: 2353.73 | 13998 1281 2484 4424 5714 5472 5029 5648 6631 7775 8926 8800 7735 8448 10496 11466 10602 10387 11224 11076 10939 12065 12497 10830 10391 11396 11931 10259 10262 10939 10169 9130 9608 10113 8955 7714 8408 8711 7593 6973 7459 7162 6232 6134 6554 5848 5110 5134 5495 4860 4083 4319 4432 3674 3259 3647 3406 2774 2755 3099 2579 2160 2269 2367 1984 1705 1833 1725 1372 1293 1349 1289 1004 902 970 862 693 720 732 613 484 488 462 374 341 336 349 246 226 213 205 156 178 186 130 122 119 126 100 72 94 79 57 64 63 57 37 38 35 33 35 27 23 19 22 28 17 7 10 14 16 16 10 7 11 6 8 9 3 6 5 4 4 4 4 4 2 6 3 5 4 3 2 5 3 3 1 1 2 1 2 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 128 max: 19863 count: 261979 average: 3868.82 | standard deviation: 2351.5 | 7419 688 1239 2305 3154 2983 2647 2979 3572 4190 4870 4943 4165 4561 5856 6066 5632 5554 6080 5901 5977 6473 6697 5701 5691 6125 6260 5627 5440 5810 5447 4965 5308 5535 4838 4142 4455 4667 4070 3789 3984 3933 3459 3253 3574 3161 2707 2890 3001 2598 2219 2381 2455 1959 1807 1908 1951 1552 1465 1552 1437 1158 1134 1233 1070 908 963 912 769 718 779 684 544 518 561 414 354 360 361 301 257 261 270 210 152 179 176 142 137 132 120 95 90 91 72 68 64 63 47 45 49 40 33 29 28 25 23 20 23 16 16 21 16 9 12 8 13 10 6 7 8 7 2 10 5 3 4 7 9 7 2 0 3 4 3 4 3 1 2 3 0 1 4 0 0 0 1 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle SW Prefetch Requests @@ -510,11 +474,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 28 count: 1495176 average: 0.00219238 | standard deviation: 0.181055 | 1494944 0 4 0 1 0 2 0 2 0 29 0 36 0 53 0 68 0 35 0 0 0 0 0 0 0 0 0 2 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 28 count: 1495176 average: 0.00219238 | standard deviation: 0.181055 | 1494944 0 4 0 1 0 2 0 2 0 29 0 36 0 53 0 68 0 35 0 0 0 0 0 0 0 0 0 2 ] +Total_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 | standard deviation: 0.169351 | 1496294 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 1496498 average: 0.0019285 | standard deviation: 0.169351 | 1496294 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 747528 average: 0 | standard deviation: 0 | 747528 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 28 count: 747648 average: 0.00438442 | standard deviation: 0.256021 | 747416 0 4 0 1 0 2 0 2 0 29 0 36 0 53 0 68 0 35 0 0 0 0 0 0 0 0 0 2 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 748171 average: 0 | standard deviation: 0 | 748171 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 748327 average: 0.0038566 | standard deviation: 0.239469 | 748123 0 2 0 3 0 1 0 1 0 29 0 28 0 42 0 61 0 37 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -522,9 +486,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 28 count: 1495176 average: 0.00219238 Resource Usage -------------- page_size: 4096 -user_time: 2020 -system_time: 0 -page_reclaims: 39806 +user_time: 2550 +system_time: 1 +page_reclaims: 39807 page_faults: 0 swaps: 0 block_inputs: 0 @@ -535,110 +499,110 @@ Network Stats switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0183509 - links_utilized_percent_switch_0_link_0: 0.00733981 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.0293619 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.0183757 + links_utilized_percent_switch_0_link_0: 0.0073498 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0294016 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 93420 747360 [ 0 93420 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 93423 747384 [ 0 0 93423 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 93427 747416 [ 93427 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Data: 87006 696048 [ 87006 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 6427 51416 [ 0 6427 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 93520 748160 [ 0 93520 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 93544 748352 [ 0 0 93544 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 93523 748184 [ 93523 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 86916 695328 [ 86916 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 6640 53120 [ 0 6640 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.018351 - links_utilized_percent_switch_1_link_0: 0.00733985 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0293621 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0183711 + links_utilized_percent_switch_1_link_0: 0.00734831 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0293939 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 93416 747328 [ 0 93416 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 93428 747424 [ 0 0 93428 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 93424 747392 [ 93424 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Data: 86798 694384 [ 86798 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 6639 53112 [ 0 6639 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 93502 748016 [ 0 93502 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 93524 748192 [ 0 0 93524 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 93506 748048 [ 93506 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 86741 693928 [ 86741 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 6783 54264 [ 0 6783 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.018354 - links_utilized_percent_switch_2_link_0: 0.00734114 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.0293669 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0183707 + links_utilized_percent_switch_2_link_0: 0.00734752 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.0293939 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 93431 747448 [ 0 93431 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 93446 747568 [ 0 0 93446 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 93439 747512 [ 93439 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Data: 86779 694232 [ 86779 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 6674 53392 [ 0 6674 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 93497 747976 [ 0 93497 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 93509 748072 [ 0 0 93509 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 93510 748080 [ 93510 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 86829 694632 [ 86829 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 6691 53528 [ 0 6691 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.0183589 - links_utilized_percent_switch_3_link_0: 0.00734326 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.0293746 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.0183818 + links_utilized_percent_switch_3_link_0: 0.00735177 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.0294118 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 93455 747640 [ 0 93455 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 93476 747808 [ 0 0 93476 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 93460 747680 [ 93460 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Data: 86672 693376 [ 86672 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 6809 54472 [ 0 6809 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 93545 748360 [ 0 93545 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 93558 748464 [ 93558 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 86852 694816 [ 86852 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 6734 53872 [ 0 6734 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.0183551 - links_utilized_percent_switch_4_link_0: 0.00734142 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.0293688 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.0183835 + links_utilized_percent_switch_4_link_0: 0.00735287 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.0294141 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 93432 747456 [ 0 93432 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 93452 747616 [ 0 0 93452 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 93443 747544 [ 93443 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Data: 86903 695224 [ 86903 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 6558 52464 [ 0 6558 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 93560 748480 [ 0 93560 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 93582 748656 [ 0 0 93582 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 93567 748536 [ 93567 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Data: 86798 694384 [ 86798 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 6794 54352 [ 0 6794 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.0183621 - links_utilized_percent_switch_5_link_0: 0.0073446 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0293797 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.0183813 + links_utilized_percent_switch_5_link_0: 0.00735204 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.0294105 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 93473 747784 [ 0 93473 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 93492 747936 [ 0 0 93492 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 93479 747832 [ 93479 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Data: 86734 693872 [ 86734 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 6760 54080 [ 0 6760 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 93552 748416 [ 0 93552 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 93561 748488 [ 93561 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Data: 86705 693640 [ 86705 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 6870 54960 [ 0 6870 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.0183551 - links_utilized_percent_switch_6_link_0: 0.00734146 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.0293688 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.0183704 + links_utilized_percent_switch_6_link_0: 0.00734764 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.0293932 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 93437 747496 [ 0 93437 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 93448 747584 [ 0 0 93448 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 93447 747576 [ 93447 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Data: 86886 695088 [ 86886 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 6571 52568 [ 0 6571 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 93494 747952 [ 0 93494 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 93502 748016 [ 93502 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Data: 86898 695184 [ 86898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 6626 53008 [ 0 6626 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.0183603 - links_utilized_percent_switch_7_link_0: 0.00734389 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.0293767 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.0183714 + links_utilized_percent_switch_7_link_0: 0.00734792 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.0293948 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 93464 747712 [ 0 93464 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 93483 747864 [ 0 0 93483 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 93469 747752 [ 93469 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Data: 86818 694544 [ 86818 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 6667 53336 [ 0 6667 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 93501 748008 [ 0 93501 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 93509 748072 [ 93509 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Data: 86787 694296 [ 86787 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 6740 53920 [ 0 6740 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.141626 - links_utilized_percent_switch_8_link_0: 0.0566537 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.226597 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.141705 + links_utilized_percent_switch_8_link_0: 0.0566866 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.226724 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 747588 5980704 [ 747588 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Data: 694596 5556768 [ 694596 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 694424 5555392 [ 0 694424 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 747648 5981184 [ 0 0 747648 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 748236 5985888 [ 748236 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 694526 5556208 [ 694526 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 694293 5554344 [ 0 694293 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 748327 5986616 [ 0 0 748327 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 @@ -649,38 +613,150 @@ links_utilized_percent_switch_9: 0 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.0461557 - links_utilized_percent_switch_10_link_0: 0.0293592 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.0293595 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.0293646 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.0293731 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.0293657 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.0293784 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.0293658 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.0293756 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.226615 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.0461938 + links_utilized_percent_switch_10_link_0: 0.0293992 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.0293932 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.0293901 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.0294071 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.0294115 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.0294082 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.0293906 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.0293917 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.226746 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_9: 0 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 93420 747360 [ 0 93420 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Writeback_Control: 93423 747384 [ 0 0 93423 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 93417 747336 [ 0 93417 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Writeback_Control: 93428 747424 [ 0 0 93428 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 93431 747448 [ 0 93431 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Writeback_Control: 93446 747568 [ 0 0 93446 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 93455 747640 [ 0 93455 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Writeback_Control: 93476 747808 [ 0 0 93476 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 93432 747456 [ 0 93432 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Writeback_Control: 93452 747616 [ 0 0 93452 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 93473 747784 [ 0 93473 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Writeback_Control: 93492 747936 [ 0 0 93492 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 93437 747496 [ 0 93437 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Writeback_Control: 93448 747584 [ 0 0 93448 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 93464 747712 [ 0 93464 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Writeback_Control: 93483 747864 [ 0 0 93483 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 747588 5980704 [ 747588 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Data: 694596 5556768 [ 694596 0 0 0 0 0 ] base_latency: 1 - - --- DMA --- + outgoing_messages_switch_10_link_0_Response_Data: 93520 748160 [ 0 93520 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 93544 748352 [ 0 0 93544 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 93502 748016 [ 0 93502 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 93524 748192 [ 0 0 93524 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 93497 747976 [ 0 93497 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Control: 93509 748072 [ 0 0 93509 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 93545 748360 [ 0 93545 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 93560 748480 [ 0 93560 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Control: 93582 748656 [ 0 0 93582 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 93552 748416 [ 0 93552 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 93569 748552 [ 0 0 93569 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 93494 747952 [ 0 93494 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 93501 748008 [ 0 93501 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Control: 93515 748120 [ 0 0 93515 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 748236 5985888 [ 748236 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Data: 694526 5556208 [ 694526 0 0 0 0 0 ] base_latency: 1 + +l1u_0 cache stats: + l1u_0_total_misses: 93523 + l1u_0_total_demand_misses: 93523 + l1u_0_total_prefetches: 0 + l1u_0_total_sw_prefetches: 0 + l1u_0_total_hw_prefetches: 0 + l1u_0_misses_per_transaction: 93523 + + l1u_0_request_type_LD: 64.8311% + l1u_0_request_type_ST: 35.1689% + + l1u_0_access_mode_type_SupervisorMode: 93523 100% + l1u_0_request_size: [binsize: log2 max: 1 count: 93523 average: 1 | standard deviation: 0 | 0 93523 ] + +l1u_1 cache stats: + l1u_1_total_misses: 93506 + l1u_1_total_demand_misses: 93506 + l1u_1_total_prefetches: 0 + l1u_1_total_sw_prefetches: 0 + l1u_1_total_hw_prefetches: 0 + l1u_1_misses_per_transaction: 93506 + + l1u_1_request_type_LD: 64.8162% + l1u_1_request_type_ST: 35.1838% + + l1u_1_access_mode_type_SupervisorMode: 93506 100% + l1u_1_request_size: [binsize: log2 max: 1 count: 93506 average: 1 | standard deviation: 0 | 0 93506 ] + +l1u_2 cache stats: + l1u_2_total_misses: 93510 + l1u_2_total_demand_misses: 93510 + l1u_2_total_prefetches: 0 + l1u_2_total_sw_prefetches: 0 + l1u_2_total_hw_prefetches: 0 + l1u_2_misses_per_transaction: 93510 + + l1u_2_request_type_LD: 64.931% + l1u_2_request_type_ST: 35.069% + + l1u_2_access_mode_type_SupervisorMode: 93510 100% + l1u_2_request_size: [binsize: log2 max: 1 count: 93510 average: 1 | standard deviation: 0 | 0 93510 ] + +l1u_3 cache stats: + l1u_3_total_misses: 93558 + l1u_3_total_demand_misses: 93558 + l1u_3_total_prefetches: 0 + l1u_3_total_sw_prefetches: 0 + l1u_3_total_hw_prefetches: 0 + l1u_3_misses_per_transaction: 93558 + + l1u_3_request_type_LD: 64.9693% + l1u_3_request_type_ST: 35.0307% + + l1u_3_access_mode_type_SupervisorMode: 93558 100% + l1u_3_request_size: [binsize: log2 max: 1 count: 93558 average: 1 | standard deviation: 0 | 0 93558 ] + +l1u_4 cache stats: + l1u_4_total_misses: 93567 + l1u_4_total_demand_misses: 93567 + l1u_4_total_prefetches: 0 + l1u_4_total_sw_prefetches: 0 + l1u_4_total_hw_prefetches: 0 + l1u_4_misses_per_transaction: 93567 + + l1u_4_request_type_LD: 65.2474% + l1u_4_request_type_ST: 34.7526% + + l1u_4_access_mode_type_SupervisorMode: 93567 100% + l1u_4_request_size: [binsize: log2 max: 1 count: 93567 average: 1 | standard deviation: 0 | 0 93567 ] + +l1u_5 cache stats: + l1u_5_total_misses: 93561 + l1u_5_total_demand_misses: 93561 + l1u_5_total_prefetches: 0 + l1u_5_total_sw_prefetches: 0 + l1u_5_total_hw_prefetches: 0 + l1u_5_misses_per_transaction: 93561 + + l1u_5_request_type_LD: 65.0004% + l1u_5_request_type_ST: 34.9996% + + l1u_5_access_mode_type_SupervisorMode: 93561 100% + l1u_5_request_size: [binsize: log2 max: 1 count: 93561 average: 1 | standard deviation: 0 | 0 93561 ] + +l1u_6 cache stats: + l1u_6_total_misses: 93502 + l1u_6_total_demand_misses: 93502 + l1u_6_total_prefetches: 0 + l1u_6_total_sw_prefetches: 0 + l1u_6_total_hw_prefetches: 0 + l1u_6_misses_per_transaction: 93502 + + l1u_6_request_type_LD: 64.9569% + l1u_6_request_type_ST: 35.0431% + + l1u_6_access_mode_type_SupervisorMode: 93502 100% + l1u_6_request_size: [binsize: log2 max: 1 count: 93502 average: 1 | standard deviation: 0 | 0 93502 ] + +l1u_7 cache stats: + l1u_7_total_misses: 93509 + l1u_7_total_demand_misses: 93509 + l1u_7_total_prefetches: 0 + l1u_7_total_sw_prefetches: 0 + l1u_7_total_hw_prefetches: 0 + l1u_7_misses_per_transaction: 93509 + + l1u_7_request_type_LD: 65.1189% + l1u_7_request_type_ST: 34.8811% + + l1u_7_access_mode_type_SupervisorMode: 93509 100% + l1u_7_request_size: [binsize: log2 max: 1 count: 93509 average: 1 | standard deviation: 0 | 0 93509 ] + + --- DMA 0 --- - Event Counts - ReadRequest 0 WriteRequest 0 @@ -695,26 +771,26 @@ BUSY_RD Data 0 <-- BUSY_WR Ack 0 <-- - --- Directory --- + --- Directory 0 --- - Event Counts - -GETX 7271682 +GETX 7422269 GETS 0 -PUTX 694236 -PUTX_NotOwner 360 +PUTX 694113 +PUTX_NotOwner 412 DMA_READ 0 DMA_WRITE 0 -Memory_Data 694424 -Memory_Ack 694183 +Memory_Data 694293 +Memory_Ack 694037 - Transitions - -I GETX 694479 +I GETX 694355 I PUTX_NotOwner 0 <-- I DMA_READ 0 <-- I DMA_WRITE 0 <-- -M GETX 53105 -M PUTX 694236 -M PUTX_NotOwner 360 +M GETX 53878 +M PUTX 694113 +M PUTX_NotOwner 412 M DMA_READ 0 <-- M DMA_WRITE 0 <-- @@ -726,21 +802,21 @@ M_DWR PUTX 0 <-- M_DWRI Memory_Ack 0 <-- -IM GETX 3129578 +IM GETX 3217688 IM GETS 0 <-- IM PUTX 0 <-- IM PUTX_NotOwner 0 <-- IM DMA_READ 0 <-- IM DMA_WRITE 0 <-- -IM Memory_Data 694424 +IM Memory_Data 694293 -MI GETX 3394520 +MI GETX 3456348 MI GETS 0 <-- MI PUTX 0 <-- MI PUTX_NotOwner 0 <-- MI DMA_READ 0 <-- MI DMA_WRITE 0 <-- -MI Memory_Ack 694183 +MI Memory_Ack 694037 ID GETX 0 <-- ID GETS 0 <-- @@ -758,291 +834,291 @@ ID_W DMA_READ 0 <-- ID_W DMA_WRITE 0 <-- ID_W Memory_Ack 0 <-- - --- L1Cache --- + --- L1Cache 0 --- - Event Counts - -Load 485858 +Load 60632 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32891 +Data 93520 +Fwd_GETX 6640 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93491 +Writeback_Ack 86841 +Writeback_Nack 63 - Transitions - -I Load 485858 +I Load 60632 I Ifetch 0 <-- -I Store 261731 +I Store 32891 I Inv 0 <-- -I Replacement 52736 +I Replacement 6575 -II Writeback_Nack 360 +II Writeback_Nack 63 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6577 M Inv 0 <-- -M Replacement 694597 +M Replacement 86916 -MI Fwd_GETX 360 +MI Fwd_GETX 63 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86841 -IS Data 485823 +IS Data 60630 -IM Data 261705 +IM Data 32890 - --- L1Cache --- + --- L1Cache 1 --- - Event Counts - -Load 485858 +Load 60607 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32899 +Data 93502 +Fwd_GETX 6783 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93474 +Writeback_Ack 86692 +Writeback_Nack 49 - Transitions - -I Load 485858 +I Load 60607 I Ifetch 0 <-- -I Store 261731 +I Store 32899 I Inv 0 <-- -I Replacement 52736 +I Replacement 6733 -II Writeback_Nack 360 +II Writeback_Nack 49 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6734 M Inv 0 <-- -M Replacement 694597 +M Replacement 86741 -MI Fwd_GETX 360 +MI Fwd_GETX 49 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86692 -IS Data 485823 +IS Data 60604 -IM Data 261705 +IM Data 32898 - --- L1Cache --- + --- L1Cache 2 --- - Event Counts - -Load 485858 +Load 60717 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32793 +Data 93497 +Fwd_GETX 6691 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93478 +Writeback_Ack 86777 +Writeback_Nack 41 - Transitions - -I Load 485858 +I Load 60717 I Ifetch 0 <-- -I Store 261731 +I Store 32793 I Inv 0 <-- -I Replacement 52736 +I Replacement 6649 -II Writeback_Nack 360 +II Writeback_Nack 41 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6650 M Inv 0 <-- -M Replacement 694597 +M Replacement 86829 -MI Fwd_GETX 360 +MI Fwd_GETX 41 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86777 -IS Data 485823 +IS Data 60709 -IM Data 261705 +IM Data 32788 - --- L1Cache --- + --- L1Cache 3 --- - Event Counts - -Load 485858 +Load 60784 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32774 +Data 93545 +Fwd_GETX 6734 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93526 +Writeback_Ack 86775 +Writeback_Nack 60 - Transitions - -I Load 485858 +I Load 60784 I Ifetch 0 <-- -I Store 261731 +I Store 32774 I Inv 0 <-- -I Replacement 52736 +I Replacement 6674 -II Writeback_Nack 360 +II Writeback_Nack 60 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6674 M Inv 0 <-- -M Replacement 694597 +M Replacement 86852 -MI Fwd_GETX 360 +MI Fwd_GETX 60 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86775 -IS Data 485823 +IS Data 60776 -IM Data 261705 +IM Data 32769 - --- L1Cache --- + --- L1Cache 4 --- - Event Counts - -Load 485858 +Load 61050 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32517 +Data 93560 +Fwd_GETX 6794 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93535 +Writeback_Ack 86735 +Writeback_Nack 53 - Transitions - -I Load 485858 +I Load 61050 I Ifetch 0 <-- -I Store 261731 +I Store 32517 I Inv 0 <-- -I Replacement 52736 +I Replacement 6737 -II Writeback_Nack 360 +II Writeback_Nack 53 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6741 M Inv 0 <-- -M Replacement 694597 +M Replacement 86798 -MI Fwd_GETX 360 +MI Fwd_GETX 53 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86735 -IS Data 485823 +IS Data 61047 -IM Data 261705 +IM Data 32513 - --- L1Cache --- + --- L1Cache 5 --- - Event Counts - -Load 485858 +Load 60815 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32746 +Data 93552 +Fwd_GETX 6870 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93529 +Writeback_Ack 86654 +Writeback_Nack 45 - Transitions - -I Load 485858 +I Load 60815 I Ifetch 0 <-- -I Store 261731 +I Store 32746 I Inv 0 <-- -I Replacement 52736 +I Replacement 6824 -II Writeback_Nack 360 +II Writeback_Nack 45 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6825 M Inv 0 <-- -M Replacement 694597 +M Replacement 86705 -MI Fwd_GETX 360 +MI Fwd_GETX 45 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86654 -IS Data 485823 +IS Data 60809 -IM Data 261705 +IM Data 32743 - --- L1Cache --- + --- L1Cache 6 --- - Event Counts - -Load 485858 +Load 60736 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32766 +Data 93494 +Fwd_GETX 6626 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93470 +Writeback_Ack 86837 +Writeback_Nack 52 - Transitions - -I Load 485858 +I Load 60736 I Ifetch 0 <-- -I Store 261731 +I Store 32766 I Inv 0 <-- -I Replacement 52736 +I Replacement 6572 -II Writeback_Nack 360 +II Writeback_Nack 52 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6574 M Inv 0 <-- -M Replacement 694597 +M Replacement 86898 -MI Fwd_GETX 360 +MI Fwd_GETX 52 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86837 -IS Data 485823 +IS Data 60730 -IM Data 261705 +IM Data 32764 - --- L1Cache --- + --- L1Cache 7 --- - Event Counts - -Load 485858 +Load 60892 Ifetch 0 -Store 261731 -Data 747528 -Fwd_GETX 53105 +Store 32617 +Data 93501 +Fwd_GETX 6740 Inv 0 -Replacement 747333 -Writeback_Ack 694183 -Writeback_Nack 360 +Replacement 93477 +Writeback_Ack 86726 +Writeback_Nack 49 - Transitions - -I Load 485858 +I Load 60892 I Ifetch 0 <-- -I Store 261731 +I Store 32617 I Inv 0 <-- -I Replacement 52736 +I Replacement 6690 -II Writeback_Nack 360 +II Writeback_Nack 49 M Load 0 <-- M Ifetch 0 <-- M Store 0 <-- -M Fwd_GETX 52745 +M Fwd_GETX 6691 M Inv 0 <-- -M Replacement 694597 +M Replacement 86787 -MI Fwd_GETX 360 +MI Fwd_GETX 49 MI Inv 0 <-- -MI Writeback_Ack 694183 +MI Writeback_Ack 86726 -IS Data 485823 +IS Data 60887 -IM Data 261705 +IM Data 32614 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr index 49e0168cd..bab30a994 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -1,76 +1,76 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"] print config: 1 -system.cpu1: completed 10000 read accesses @3641101 -system.cpu6: completed 10000 read accesses @3657885 -system.cpu0: completed 10000 read accesses @3682054 -system.cpu4: completed 10000 read accesses @3686756 -system.cpu3: completed 10000 read accesses @3686791 -system.cpu2: completed 10000 read accesses @3714721 -system.cpu5: completed 10000 read accesses @3718986 -system.cpu7: completed 10000 read accesses @3739388 -system.cpu1: completed 20000 read accesses @6773990 -system.cpu4: completed 20000 read accesses @6790313 -system.cpu0: completed 20000 read accesses @6796672 -system.cpu3: completed 20000 read accesses @6797278 -system.cpu6: completed 20000 read accesses @6823694 -system.cpu2: completed 20000 read accesses @6833547 -system.cpu5: completed 20000 read accesses @6854676 -system.cpu7: completed 20000 read accesses @6875905 -system.cpu1: completed 30000 read accesses @9853256 -system.cpu3: completed 30000 read accesses @9906665 -system.cpu0: completed 30000 read accesses @9931557 -system.cpu4: completed 30000 read accesses @9952518 -system.cpu5: completed 30000 read accesses @9976242 -system.cpu2: completed 30000 read accesses @9981306 -system.cpu6: completed 30000 read accesses @10008066 -system.cpu7: completed 30000 read accesses @10011960 -system.cpu1: completed 40000 read accesses @13015878 -system.cpu3: completed 40000 read accesses @13040111 -system.cpu5: completed 40000 read accesses @13079687 -system.cpu0: completed 40000 read accesses @13099309 -system.cpu2: completed 40000 read accesses @13115004 -system.cpu4: completed 40000 read accesses @13143910 -system.cpu6: completed 40000 read accesses @13150020 -system.cpu7: completed 40000 read accesses @13161356 -system.cpu3: completed 50000 read accesses @16125452 -system.cpu1: completed 50000 read accesses @16181745 -system.cpu5: completed 50000 read accesses @16184066 -system.cpu0: completed 50000 read accesses @16216286 -system.cpu2: completed 50000 read accesses @16257216 -system.cpu4: completed 50000 read accesses @16263973 -system.cpu6: completed 50000 read accesses @16288792 -system.cpu7: completed 50000 read accesses @16318993 -system.cpu3: completed 60000 read accesses @19283536 -system.cpu0: completed 60000 read accesses @19309937 -system.cpu1: completed 60000 read accesses @19317676 -system.cpu2: completed 60000 read accesses @19325470 -system.cpu5: completed 60000 read accesses @19327514 -system.cpu6: completed 60000 read accesses @19417822 -system.cpu4: completed 60000 read accesses @19447479 -system.cpu7: completed 60000 read accesses @19480386 -system.cpu0: completed 70000 read accesses @22411174 -system.cpu3: completed 70000 read accesses @22411178 -system.cpu2: completed 70000 read accesses @22414508 -system.cpu5: completed 70000 read accesses @22453684 -system.cpu1: completed 70000 read accesses @22473724 -system.cpu4: completed 70000 read accesses @22564254 -system.cpu6: completed 70000 read accesses @22590390 -system.cpu7: completed 70000 read accesses @22646034 -system.cpu3: completed 80000 read accesses @25536114 -system.cpu0: completed 80000 read accesses @25565410 -system.cpu2: completed 80000 read accesses @25581306 -system.cpu1: completed 80000 read accesses @25643150 -system.cpu5: completed 80000 read accesses @25659302 -system.cpu4: completed 80000 read accesses @25672250 -system.cpu6: completed 80000 read accesses @25729734 -system.cpu7: completed 80000 read accesses @25780094 -system.cpu3: completed 90000 read accesses @28701520 -system.cpu2: completed 90000 read accesses @28736898 -system.cpu0: completed 90000 read accesses @28740612 -system.cpu5: completed 90000 read accesses @28751484 -system.cpu1: completed 90000 read accesses @28768980 -system.cpu4: completed 90000 read accesses @28819348 -system.cpu6: completed 90000 read accesses @28888794 -system.cpu7: completed 90000 read accesses @28938947 -system.cpu3: completed 100000 read accesses @31820150 +system.cpu1: completed 10000 read accesses @3663630 +system.cpu2: completed 10000 read accesses @3663638 +system.cpu5: completed 10000 read accesses @3680002 +system.cpu7: completed 10000 read accesses @3691164 +system.cpu3: completed 10000 read accesses @3698130 +system.cpu4: completed 10000 read accesses @3701748 +system.cpu6: completed 10000 read accesses @3704092 +system.cpu0: completed 10000 read accesses @3742302 +system.cpu2: completed 20000 read accesses @6788966 +system.cpu7: completed 20000 read accesses @6816416 +system.cpu5: completed 20000 read accesses @6822351 +system.cpu4: completed 20000 read accesses @6824056 +system.cpu1: completed 20000 read accesses @6825604 +system.cpu3: completed 20000 read accesses @6829578 +system.cpu6: completed 20000 read accesses @6857232 +system.cpu0: completed 20000 read accesses @6872452 +system.cpu5: completed 30000 read accesses @9928492 +system.cpu2: completed 30000 read accesses @9933192 +system.cpu7: completed 30000 read accesses @9950074 +system.cpu4: completed 30000 read accesses @9965775 +system.cpu6: completed 30000 read accesses @9978835 +system.cpu0: completed 30000 read accesses @9993926 +system.cpu1: completed 30000 read accesses @9994767 +system.cpu3: completed 30000 read accesses @9996366 +system.cpu5: completed 40000 read accesses @13012070 +system.cpu2: completed 40000 read accesses @13044972 +system.cpu7: completed 40000 read accesses @13077010 +system.cpu4: completed 40000 read accesses @13081178 +system.cpu1: completed 40000 read accesses @13100740 +system.cpu0: completed 40000 read accesses @13111135 +system.cpu6: completed 40000 read accesses @13147706 +system.cpu3: completed 40000 read accesses @13153176 +system.cpu5: completed 50000 read accesses @16120762 +system.cpu2: completed 50000 read accesses @16176586 +system.cpu7: completed 50000 read accesses @16213417 +system.cpu4: completed 50000 read accesses @16219872 +system.cpu6: completed 50000 read accesses @16231538 +system.cpu1: completed 50000 read accesses @16246976 +system.cpu3: completed 50000 read accesses @16276612 +system.cpu0: completed 50000 read accesses @16293234 +system.cpu5: completed 60000 read accesses @19263804 +system.cpu4: completed 60000 read accesses @19313220 +system.cpu2: completed 60000 read accesses @19330470 +system.cpu7: completed 60000 read accesses @19340197 +system.cpu6: completed 60000 read accesses @19399766 +system.cpu0: completed 60000 read accesses @19424570 +system.cpu1: completed 60000 read accesses @19425712 +system.cpu3: completed 60000 read accesses @19444952 +system.cpu5: completed 70000 read accesses @22408750 +system.cpu4: completed 70000 read accesses @22449746 +system.cpu7: completed 70000 read accesses @22451736 +system.cpu2: completed 70000 read accesses @22461052 +system.cpu0: completed 70000 read accesses @22554296 +system.cpu1: completed 70000 read accesses @22555310 +system.cpu3: completed 70000 read accesses @22588935 +system.cpu6: completed 70000 read accesses @22602456 +system.cpu5: completed 80000 read accesses @25540598 +system.cpu4: completed 80000 read accesses @25577430 +system.cpu7: completed 80000 read accesses @25617532 +system.cpu1: completed 80000 read accesses @25644879 +system.cpu2: completed 80000 read accesses @25660256 +system.cpu0: completed 80000 read accesses @25710799 +system.cpu3: completed 80000 read accesses @25716714 +system.cpu6: completed 80000 read accesses @25776606 +system.cpu5: completed 90000 read accesses @28693458 +system.cpu4: completed 90000 read accesses @28705416 +system.cpu7: completed 90000 read accesses @28729734 +system.cpu1: completed 90000 read accesses @28778532 +system.cpu2: completed 90000 read accesses @28801770 +system.cpu0: completed 90000 read accesses @28857559 +system.cpu6: completed 90000 read accesses @28885159 +system.cpu3: completed 90000 read accesses @28894168 +system.cpu7: completed 100000 read accesses @31814464 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout index 8fd09328a..81934512d 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 13 2009 11:01:42 -M5 revision 57650468aff1+ 6297+ default -M5 started Jul 13 2009 11:01:45 +M5 compiled Jul 19 2009 14:52:18 +M5 revision 544d33334ee1+ 6369+ default tip +M5 started Jul 19 2009 14:52:23 M5 executing on clover-01.cs.wisc.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 31820150 because maximum number of loads reached +Exiting @ tick 31814464 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 060ced5b9..b2eef7422 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 1538632 # Number of bytes of host memory used -host_seconds 2021.99 # Real time elapsed on the host -host_tick_rate 15737 # Simulator tick rate (ticks/s) +host_mem_usage 1538656 # Number of bytes of host memory used +host_seconds 2552.36 # Real time elapsed on the host +host_tick_rate 12465 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31820150 # Number of ticks simulated +sim_ticks 31814464 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99856 # number of read accesses completed -system.cpu0.num_writes 53852 # number of write accesses completed +system.cpu0.num_reads 99342 # number of read accesses completed +system.cpu0.num_writes 53699 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99692 # number of read accesses completed -system.cpu1.num_writes 53561 # number of write accesses completed +system.cpu1.num_reads 99812 # number of read accesses completed +system.cpu1.num_writes 53757 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99805 # number of read accesses completed -system.cpu2.num_writes 53565 # number of write accesses completed +system.cpu2.num_reads 99597 # number of read accesses completed +system.cpu2.num_writes 53671 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 53663 # number of write accesses completed +system.cpu3.num_reads 99365 # number of read accesses completed +system.cpu3.num_writes 53444 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99420 # number of read accesses completed -system.cpu4.num_writes 53889 # number of write accesses completed +system.cpu4.num_reads 99713 # number of read accesses completed +system.cpu4.num_writes 54044 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99788 # number of read accesses completed -system.cpu5.num_writes 53529 # number of write accesses completed +system.cpu5.num_reads 99943 # number of read accesses completed +system.cpu5.num_writes 53789 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99210 # number of read accesses completed -system.cpu6.num_writes 53902 # number of write accesses completed +system.cpu6.num_reads 99307 # number of read accesses completed +system.cpu6.num_writes 53603 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99182 # number of read accesses completed -system.cpu7.num_writes 54075 # number of write accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53881 # number of write accesses completed ---------- End Simulation Statistics ---------- |