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-rw-r--r--base/statistics.cc7
-rw-r--r--base/statistics.hh2
-rw-r--r--base/stats/text.cc2
-rw-r--r--cpu/base_cpu.cc49
-rw-r--r--cpu/base_cpu.hh31
-rw-r--r--cpu/memtest/memtest.cc49
-rw-r--r--cpu/memtest/memtest.hh17
-rw-r--r--cpu/simple_cpu/simple_cpu.cc137
-rw-r--r--cpu/simple_cpu/simple_cpu.hh44
-rw-r--r--cpu/trace/opt_cpu.cc2
-rw-r--r--cpu/trace/opt_cpu.hh11
-rw-r--r--cpu/trace/trace_cpu.cc2
-rw-r--r--cpu/trace/trace_cpu.hh11
-rw-r--r--dev/tsunami.hh35
-rw-r--r--dev/tsunami_io.cc1
-rw-r--r--dev/tsunami_io.hh79
-rw-r--r--objects/MemTest.mpy5
-rw-r--r--sim/main.cc10
-rw-r--r--sim/process.cc23
-rw-r--r--sim/process.hh2
-rw-r--r--sim/pyconfig/m5config.py139
-rwxr-xr-x[-rw-r--r--]test/genini.py8
22 files changed, 281 insertions, 385 deletions
diff --git a/base/statistics.cc b/base/statistics.cc
index 6e3dae1ef..6f5caf1fe 100644
--- a/base/statistics.cc
+++ b/base/statistics.cc
@@ -286,6 +286,13 @@ check()
Database::stats().sort(StatData::less);
+#if defined(STATS_BINNING)
+ if (MainBin::curBin() == NULL) {
+ static MainBin mainBin("main bin");
+ mainBin.activate();
+ }
+#endif
+
if (i == end)
return;
diff --git a/base/statistics.hh b/base/statistics.hh
index 9ec26eb4d..667a0ed48 100644
--- a/base/statistics.hh
+++ b/base/statistics.hh
@@ -2184,7 +2184,7 @@ class SumNode : public Node
* binned. If the typedef is NoBin, nothing is binned. If it is
* MainBin, then all stats are binned under that Bin.
*/
-#if defined(FS_MEASURE) || defined(STATS_BINNING)
+#if defined(STATS_BINNING)
typedef MainBin DefaultBin;
#else
typedef NoBin DefaultBin;
diff --git a/base/stats/text.cc b/base/stats/text.cc
index f7e82a30f..8cc5ff65e 100644
--- a/base/stats/text.cc
+++ b/base/stats/text.cc
@@ -126,7 +126,7 @@ Text::output()
using namespace Database;
ccprintf(*stream, "\n---------- Begin Simulation Statistics ----------\n");
- if (bins().empty()) {
+ if (bins().empty() || bins().size() == 1) {
stat_list_t::const_iterator i, end = stats().end();
for (i = stats().begin(); i != end; ++i)
(*i)->visit(*this);
diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 425ac8877..a17edd371 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -49,25 +49,12 @@ vector<BaseCPU *> BaseCPU::cpuList;
int maxThreadsPerCPU = 1;
#ifdef FULL_SYSTEM
-BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
- Counter max_insts_any_thread,
- Counter max_insts_all_threads,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads,
- System *_system, Tick freq,
- bool _function_trace, Tick _function_trace_start)
- : SimObject(_name), frequency(freq), checkInterrupts(true),
- deferRegistration(_def_reg), number_of_threads(_number_of_threads),
- system(_system)
+BaseCPU::BaseCPU(Params *p)
+ : SimObject(p->name), frequency(p->freq), checkInterrupts(true),
+ params(p), number_of_threads(p->numberOfThreads), system(p->system)
#else
-BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
- Counter max_insts_any_thread,
- Counter max_insts_all_threads,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads,
- bool _function_trace, Tick _function_trace_start)
- : SimObject(_name), deferRegistration(_def_reg),
- number_of_threads(_number_of_threads)
+BaseCPU::BaseCPU(Params *p)
+ : SimObject(p->name), params(p), number_of_threads(p->numberOfThreads)
#endif
{
// add self to global list of CPUs
@@ -84,12 +71,12 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
//
// set up instruction-count-based termination events, if any
//
- if (max_insts_any_thread != 0)
+ if (p->max_insts_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
- new SimExitEvent(comInstEventQueue[i], max_insts_any_thread,
+ new SimExitEvent(comInstEventQueue[i], p->max_insts_any_thread,
"a thread reached the max instruction count");
- if (max_insts_all_threads != 0) {
+ if (p->max_insts_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
// decrement this when triggered; simulation will terminate
// when counter reaches 0
@@ -98,7 +85,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
for (int i = 0; i < number_of_threads; ++i)
new CountedExitEvent(comInstEventQueue[i],
"all threads reached the max instruction count",
- max_insts_all_threads, *counter);
+ p->max_insts_all_threads, *counter);
}
// allocate per-thread load-based event queues
@@ -109,12 +96,12 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
//
// set up instruction-count-based termination events, if any
//
- if (max_loads_any_thread != 0)
+ if (p->max_loads_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
- new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread,
+ new SimExitEvent(comLoadEventQueue[i], p->max_loads_any_thread,
"a thread reached the max load count");
- if (max_loads_all_threads != 0) {
+ if (p->max_loads_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
// decrement this when triggered; simulation will terminate
// when counter reaches 0
@@ -123,7 +110,7 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
for (int i = 0; i < number_of_threads; ++i)
new CountedExitEvent(comLoadEventQueue[i],
"all threads reached the max load count",
- max_loads_all_threads, *counter);
+ p->max_loads_all_threads, *counter);
}
#ifdef FULL_SYSTEM
@@ -132,18 +119,18 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
#endif
functionTracingEnabled = false;
- if (_function_trace) {
+ if (p->functionTrace) {
functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
currentFunctionStart = currentFunctionEnd = 0;
- functionEntryTick = _function_trace_start;
+ functionEntryTick = p->functionTraceStart;
- if (_function_trace_start == 0) {
+ if (p->functionTraceStart == 0) {
functionTracingEnabled = true;
} else {
Event *e =
new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
true);
- e->schedule(_function_trace_start);
+ e->schedule(p->functionTraceStart);
}
}
}
@@ -162,7 +149,7 @@ BaseCPU::~BaseCPU()
void
BaseCPU::init()
{
- if (!deferRegistration)
+ if (!params->deferRegistration)
registerExecContexts();
}
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh
index baa956aa8..dd1c7ac58 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base_cpu.hh
@@ -90,28 +90,31 @@ class BaseCPU : public SimObject
virtual void haltContext(int thread_num) {}
public:
-
+ struct Params
+ {
+ std::string name;
+ int numberOfThreads;
+ bool deferRegistration;
+ Counter max_insts_any_thread;
+ Counter max_insts_all_threads;
+ Counter max_loads_any_thread;
+ Counter max_loads_all_threads;
+ Tick freq;
+ bool functionTrace;
+ Tick functionTraceStart;
#ifdef FULL_SYSTEM
- BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
- Counter max_insts_any_thread, Counter max_insts_all_threads,
- Counter max_loads_any_thread, Counter max_loads_all_threads,
- System *_system, Tick freq,
- bool _function_trace = false, Tick _function_trace_start = 0);
-#else
- BaseCPU(const std::string &_name, int _number_of_threads, bool _def_reg,
- Counter max_insts_any_thread = 0,
- Counter max_insts_all_threads = 0,
- Counter max_loads_any_thread = 0,
- Counter max_loads_all_threads = 0,
- bool _function_trace = false, Tick _function_trace_start = 0);
+ System *system;
#endif
+ };
+
+ const Params *params;
+ BaseCPU(Params *params);
virtual ~BaseCPU();
virtual void init();
virtual void regStats();
- bool deferRegistration;
void registerExecContexts();
/// Prepare for another CPU to take over execution. Called by
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index e967c79da..14b119880 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -36,6 +36,7 @@
#include "base/misc.hh"
#include "base/statistics.hh"
+#include "cpu/exec_context.hh"
#include "cpu/memtest/memtest.hh"
#include "mem/cache/base_cache.hh"
#include "mem/functional_mem/main_memory.hh"
@@ -59,10 +60,8 @@ MemTest::MemTest(const string &name,
unsigned _percentSourceUnaligned,
unsigned _percentDestUnaligned,
Addr _traceAddr,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads)
- : BaseCPU(name, 1, true, 0, 0, max_loads_any_thread,
- max_loads_all_threads),
+ Counter _max_loads)
+ : SimObject(name),
tickEvent(this),
cacheInterface(_cache_interface),
mainMem(main_mem),
@@ -74,12 +73,13 @@ MemTest::MemTest(const string &name,
progressInterval(_progressInterval),
nextProgressMessage(_progressInterval),
percentSourceUnaligned(_percentSourceUnaligned),
- percentDestUnaligned(percentDestUnaligned)
+ percentDestUnaligned(percentDestUnaligned),
+ maxLoads(_max_loads)
{
vector<string> cmd;
cmd.push_back("/bin/ls");
vector<string> null_vec;
- xc = new ExecContext(this ,0,mainMem,0);
+ xc = new ExecContext(NULL, 0, mainMem, 0);
blockSize = cacheInterface->getBlockSize();
blockAddrMask = blockSize - 1;
@@ -160,7 +160,8 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
nextProgressMessage += progressInterval;
}
- comLoadEventQueue[0]->serviceEvents(numReads);
+ if (numReads >= maxLoads)
+ SimExit(curTick, "Maximum number of loads reached!");
break;
case Write:
@@ -402,8 +403,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
Param<unsigned> percent_source_unaligned;
Param<unsigned> percent_dest_unaligned;
Param<Addr> trace_addr;
- Param<Counter> max_loads_any_thread;
- Param<Counter> max_loads_all_threads;
+ Param<Counter> max_loads;
END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
@@ -413,23 +413,17 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
INIT_PARAM(cache, "L1 cache"),
INIT_PARAM(main_mem, "hierarchical memory"),
INIT_PARAM(check_mem, "check memory"),
- INIT_PARAM_DFLT(memory_size, "memory size", 65536),
- INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
- INIT_PARAM_DFLT(percent_copies, "target copy percentage", 0),
- INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
- INIT_PARAM_DFLT(progress_interval,
- "progress report interval (in accesses)", 1000000),
- INIT_PARAM_DFLT(percent_source_unaligned, "percent of copy source address "
- "that are unaligned", 50),
- INIT_PARAM_DFLT(percent_dest_unaligned, "percent of copy dest address "
- "that are unaligned", 50),
- INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "terminate when all threads have reached this load count",
- 0)
+ INIT_PARAM(memory_size, "memory size"),
+ INIT_PARAM(percent_reads, "target read percentage"),
+ INIT_PARAM(percent_copies, "target copy percentage"),
+ INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
+ INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
+ INIT_PARAM(percent_source_unaligned,
+ "percent of copy source address that are unaligned"),
+ INIT_PARAM(percent_dest_unaligned,
+ "percent of copy dest address that are unaligned"),
+ INIT_PARAM(trace_addr, "address to trace"),
+ INIT_PARAM(max_loads, "terminate when we have reached this load count")
END_INIT_SIM_OBJECT_PARAMS(MemTest)
@@ -440,8 +434,7 @@ CREATE_SIM_OBJECT(MemTest)
check_mem, memory_size, percent_reads, percent_copies,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
- trace_addr, max_loads_any_thread,
- max_loads_all_threads);
+ trace_addr, max_loads);
}
REGISTER_SIM_OBJECT("MemTest", MemTest)
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 43b17a713..45b2d24e8 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -26,20 +26,21 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __MEMTEST_HH__
-#define __MEMTEST_HH__
+#ifndef __CPU_MEMTEST_MEMTEST_HH__
+#define __CPU_MEMTEST_MEMTEST_HH__
#include <set>
#include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/exec_context.hh"
#include "mem/functional_mem/functional_memory.hh"
#include "mem/mem_interface.hh"
+#include "sim/eventq.hh"
+#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-class MemTest : public BaseCPU
+class ExecContext;
+class MemTest : public SimObject
{
public:
@@ -55,8 +56,7 @@ class MemTest : public BaseCPU
unsigned _percentSourceUnaligned,
unsigned _percentDestUnaligned,
Addr _traceAddr,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads);
+ Counter _max_loads);
// register statistics
virtual void regStats();
@@ -116,6 +116,7 @@ class MemTest : public BaseCPU
Tick noResponseCycles;
uint64_t numReads;
+ uint64_t maxLoads;
Stats::Scalar<> numReadsStat;
Stats::Scalar<> numWritesStat;
Stats::Scalar<> numCopiesStat;
@@ -146,7 +147,7 @@ class MemCompleteEvent : public Event
virtual const char *description();
};
-#endif // __MEMTEST_HH__
+#endif // __CPU_MEMTEST_MEMTEST_HH__
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index f292b25a5..044ee9b9d 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -75,15 +75,15 @@
using namespace std;
-SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
- : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
+SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
+ : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
{
}
void
SimpleCPU::TickEvent::process()
{
- int count = multiplier;
+ int count = width;
do {
cpu->tick();
} while (--count > 0 && cpu->status() == Running);
@@ -97,8 +97,7 @@ SimpleCPU::TickEvent::description()
SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
- : Event(&mainEventQueue),
- cpu(_cpu)
+ : Event(&mainEventQueue), cpu(_cpu)
{
}
@@ -113,52 +112,22 @@ SimpleCPU::CacheCompletionEvent::description()
return "SimpleCPU cache completion event";
}
-#ifdef FULL_SYSTEM
-SimpleCPU::SimpleCPU(const string &_name,
- System *_system,
- Counter max_insts_any_thread,
- Counter max_insts_all_threads,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads,
- AlphaITB *itb, AlphaDTB *dtb,
- FunctionalMemory *mem,
- MemInterface *icache_interface,
- MemInterface *dcache_interface,
- bool _def_reg, Tick freq,
- bool _function_trace, Tick _function_trace_start)
- : BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
- max_insts_any_thread, max_insts_all_threads,
- max_loads_any_thread, max_loads_all_threads,
- _system, freq, _function_trace, _function_trace_start),
-#else
-SimpleCPU::SimpleCPU(const string &_name, Process *_process,
- Counter max_insts_any_thread,
- Counter max_insts_all_threads,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads,
- MemInterface *icache_interface,
- MemInterface *dcache_interface,
- bool _def_reg,
- bool _function_trace, Tick _function_trace_start)
- : BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
- max_insts_any_thread, max_insts_all_threads,
- max_loads_any_thread, max_loads_all_threads,
- _function_trace, _function_trace_start),
-#endif
- tickEvent(this), xc(NULL), cacheCompletionEvent(this)
+SimpleCPU::SimpleCPU(Params *p)
+ : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
+ cacheCompletionEvent(this)
{
_status = Idle;
#ifdef FULL_SYSTEM
- xc = new ExecContext(this, 0, system, itb, dtb, mem);
+ xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
// initialize CPU, including PC
TheISA::initCPU(&xc->regs);
#else
- xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
+ xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
#endif // !FULL_SYSTEM
- icacheInterface = icache_interface;
- dcacheInterface = dcache_interface;
+ icacheInterface = p->icache_interface;
+ dcacheInterface = p->dcache_interface;
memReq = new MemReq();
memReq->xc = xc;
@@ -841,7 +810,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
SimObjectParam<BaseMem *> dcache;
Param<bool> defer_registration;
- Param<int> multiplier;
+ Param<int> width;
Param<bool> function_trace;
Param<Tick> function_trace_start;
@@ -849,71 +818,67 @@ END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
- INIT_PARAM_DFLT(max_insts_any_thread,
- "terminate when any thread reaches this inst count",
- 0),
- INIT_PARAM_DFLT(max_insts_all_threads,
- "terminate when all threads have reached this inst count",
- 0),
- INIT_PARAM_DFLT(max_loads_any_thread,
- "terminate when any thread reaches this load count",
- 0),
- INIT_PARAM_DFLT(max_loads_all_threads,
- "terminate when all threads have reached this load count",
- 0),
+ INIT_PARAM(max_insts_any_thread,
+ "terminate when any thread reaches this inst count"),
+ INIT_PARAM(max_insts_all_threads,
+ "terminate when all threads have reached this inst count"),
+ INIT_PARAM(max_loads_any_thread,
+ "terminate when any thread reaches this load count"),
+ INIT_PARAM(max_loads_all_threads,
+ "terminate when all threads have reached this load count"),
#ifdef FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
- INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
+ INIT_PARAM(mult, "system clock multiplier"),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
- INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
- INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
- INIT_PARAM_DFLT(defer_registration, "defer registration with system "
- "(for sampling)", false),
-
- INIT_PARAM_DFLT(multiplier, "clock multiplier", 1),
- INIT_PARAM_DFLT(function_trace, "Enable function trace", false),
- INIT_PARAM_DFLT(function_trace_start, "Cycle to start function trace", 0)
+ INIT_PARAM(icache, "L1 instruction cache object"),
+ INIT_PARAM(dcache, "L1 data cache object"),
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+ INIT_PARAM(width, "cpu width"),
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
CREATE_SIM_OBJECT(SimpleCPU)
{
- SimpleCPU *cpu;
#ifdef FULL_SYSTEM
if (mult != 1)
panic("processor clock multiplier must be 1\n");
+#endif
- cpu = new SimpleCPU(getInstanceName(), system,
- max_insts_any_thread, max_insts_all_threads,
- max_loads_any_thread, max_loads_all_threads,
- itb, dtb, mem,
- (icache) ? icache->getInterface() : NULL,
- (dcache) ? dcache->getInterface() : NULL,
- defer_registration,
- ticksPerSecond * mult,
- function_trace, function_trace_start);
-#else
-
- cpu = new SimpleCPU(getInstanceName(), workload,
- max_insts_any_thread, max_insts_all_threads,
- max_loads_any_thread, max_loads_all_threads,
- (icache) ? icache->getInterface() : NULL,
- (dcache) ? dcache->getInterface() : NULL,
- defer_registration,
- function_trace, function_trace_start);
-
-#endif // FULL_SYSTEM
+ SimpleCPU::Params *params = new SimpleCPU::Params();
+ params->name = getInstanceName();
+ params->numberOfThreads = 1;
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
+ params->deferRegistration = defer_registration;
+ params->freq = ticksPerSecond;
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+ params->icache_interface = (icache) ? icache->getInterface() : NULL;
+ params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
+ params->width = width;
- cpu->setTickMultiplier(multiplier);
+#ifdef FULL_SYSTEM
+ params->itb = itb;
+ params->dtb = dtb;
+ params->mem = mem;
+ params->system = system;
+#else
+ params->process = workload;
+#endif
+ SimpleCPU *cpu = new SimpleCPU(params);
return cpu;
}
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index a81d6365b..0283545f4 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -69,9 +69,9 @@ class SimpleCPU : public BaseCPU
struct TickEvent : public Event
{
SimpleCPU *cpu;
- int multiplier;
+ int width;
- TickEvent(SimpleCPU *c);
+ TickEvent(SimpleCPU *c, int w);
void process();
const char *description();
};
@@ -94,12 +94,6 @@ class SimpleCPU : public BaseCPU
tickEvent.squash();
}
- public:
- void setTickMultiplier(int multiplier)
- {
- tickEvent.multiplier = multiplier;
- }
-
private:
Trace::InstRecord *traceData;
@@ -128,32 +122,24 @@ class SimpleCPU : public BaseCPU
}
};
+ public:
+ struct Params : public BaseCPU::Params
+ {
+ MemInterface *icache_interface;
+ MemInterface *dcache_interface;
+ int width;
#ifdef FULL_SYSTEM
-
- SimpleCPU(const std::string &_name,
- System *_system,
- Counter max_insts_any_thread, Counter max_insts_all_threads,
- Counter max_loads_any_thread, Counter max_loads_all_threads,
- AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
- MemInterface *icache_interface, MemInterface *dcache_interface,
- bool _def_reg, Tick freq,
- bool _function_trace, Tick _function_trace_start);
-
+ AlphaITB *itb;
+ AlphaDTB *dtb;
+ FunctionalMemory *mem;
#else
-
- SimpleCPU(const std::string &_name, Process *_process,
- Counter max_insts_any_thread,
- Counter max_insts_all_threads,
- Counter max_loads_any_thread,
- Counter max_loads_all_threads,
- MemInterface *icache_interface, MemInterface *dcache_interface,
- bool _def_reg,
- bool _function_trace, Tick _function_trace_start);
-
+ Process *process;
#endif
-
+ };
+ SimpleCPU(Params *params);
virtual ~SimpleCPU();
+ public:
// execution context
ExecContext *xc;
diff --git a/cpu/trace/opt_cpu.cc b/cpu/trace/opt_cpu.cc
index 77211e382..15b53d46e 100644
--- a/cpu/trace/opt_cpu.cc
+++ b/cpu/trace/opt_cpu.cc
@@ -48,7 +48,7 @@ OptCPU::OptCPU(const string &name,
int block_size,
int cache_size,
int _assoc)
- : BaseCPU(name, 1, true), tickEvent(this), trace(_trace),
+ : SimObject(name), tickEvent(this), trace(_trace),
numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc),
setMask(numSets - 1)
{
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index 847147b3c..7f6aa3e18 100644
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -32,14 +32,14 @@
* trace to access a fully associative cache with optimal replacement.
*/
-#ifndef __OPT_CPU_HH__
-#define __OPT_CPU_HH__
+#ifndef __CPU_TRACE_OPT_CPU_HH__
+#define __CPU_TRACE_OPT_CPU_HH__
#include <vector>
-#include "cpu/base_cpu.hh"
#include "mem/mem_req.hh" // for MemReqPtr
#include "sim/eventq.hh" // for Event
+#include "sim/sim_object.hh"
// Forward Declaration
class MemTraceReader;
@@ -47,8 +47,9 @@ class MemTraceReader;
/**
* A CPU object to simulate a fully-associative cache with optimal replacement.
*/
-class OptCPU : public BaseCPU
+class OptCPU : public SimObject
{
+ private:
typedef int RefIndex;
typedef std::vector<RefIndex> L3Table;
@@ -219,4 +220,4 @@ class OptCPU : public BaseCPU
void tick();
};
-#endif
+#endif // __CPU_TRACE_OPT_CPU_HH__
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index f1160337a..1902d0be4 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -47,7 +47,7 @@ TraceCPU::TraceCPU(const string &name,
MemInterface *icache_interface,
MemInterface *dcache_interface,
MemTraceReader *data_trace)
- : BaseCPU(name, 4, true), icacheInterface(icache_interface),
+ : SimObject(name), icacheInterface(icache_interface),
dcacheInterface(dcache_interface),
dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
{
diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
index 1711646a8..cdac4bb4f 100644
--- a/cpu/trace/trace_cpu.hh
+++ b/cpu/trace/trace_cpu.hh
@@ -32,14 +32,14 @@
* provided memory hierarchy.
*/
-#ifndef __TRACE_CPU_HH__
-#define __TRACE_CPU_HH__
+#ifndef __CPU_TRACE_TRACE_CPU_HH__
+#define __CPU_TRACE_TRACE_CPU_HH__
#include <string>
-#include "cpu/base_cpu.hh"
#include "mem/mem_req.hh" // for MemReqPtr
#include "sim/eventq.hh" // for Event
+#include "sim/sim_object.hh"
// Forward declaration.
class MemInterface;
@@ -48,8 +48,9 @@ class MemTraceReader;
/**
* A cpu object for running memory traces through a memory hierarchy.
*/
-class TraceCPU : public BaseCPU
+class TraceCPU : public SimObject
{
+ private:
/** Interface for instruction trace requests, if any. */
MemInterface *icacheInterface;
/** Interface for data trace requests, if any. */
@@ -133,5 +134,5 @@ class TraceCompleteEvent : public Event
virtual const char *description();
};
-#endif //__TRACE_CPU_HH__
+#endif // __CPU_TRACE_TRACE_CPU_HH__
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index d7c549e90..7722c8417 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -32,8 +32,8 @@
* retains pointers to all its children so the children can communicate.
*/
-#ifndef __TSUNAMI_HH__
-#define __TSUNAMI_HH__
+#ifndef __DEV_TSUNAMI_HH__
+#define __DEV_TSUNAMI_HH__
#include "dev/platform.hh"
@@ -56,7 +56,6 @@ class System;
class Tsunami : public Platform
{
public:
-
/** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 64;
@@ -67,15 +66,15 @@ class Tsunami : public Platform
TsunamiIO *io;
/** Pointer to the Tsunami CChip.
- * The chip contains some configuration information and
- * all the interrupt mask and status registers
- */
+ * The chip contains some configuration information and
+ * all the interrupt mask and status registers
+ */
TsunamiCChip *cchip;
/** Pointer to the Tsunami PChip.
- * The pchip is the interface to the PCI bus, in our case
- * it does not have to do much.
- */
+ * The pchip is the interface to the PCI bus, in our case
+ * it does not have to do much.
+ */
TsunamiPChip *pchip;
int intr_sum_type[Tsunami::Max_CPUs];
@@ -83,12 +82,12 @@ class Tsunami : public Platform
public:
/**
- * Constructor for the Tsunami Class.
- * @param name name of the object
- * @param con pointer to the console
- * @param intrcontrol pointer to the interrupt controller
- * @param intrFreq frequency that interrupts happen
- */
+ * Constructor for the Tsunami Class.
+ * @param name name of the object
+ * @param con pointer to the console
+ * @param intrcontrol pointer to the interrupt controller
+ * @param intrFreq frequency that interrupts happen
+ */
Tsunami(const std::string &name, System *s, IntrControl *intctrl,
PciConfigAll *pci, int intrFreq);
@@ -96,7 +95,7 @@ class Tsunami : public Platform
* Return the interrupting frequency to AlphaAccess
* @return frequency of RTC interrupts
*/
- virtual Tick intrFrequency();
+ virtual Tick intrFrequency();
/**
* Cause the cpu to post a serial interrupt to the CPU.
@@ -120,7 +119,7 @@ class Tsunami : public Platform
virtual Addr pciToDma(Addr pciAddr) const;
- /**
+ /**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
@@ -134,4 +133,4 @@ class Tsunami : public Platform
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
-#endif // __TSUNAMI_HH__
+#endif // __DEV_TSUNAMI_HH__
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 94a951d2c..6c9195bff 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -67,7 +67,6 @@ TsunamiIO::RTCEvent::process()
schedule(curTick + ticksPerSecond/RTC_RATE);
//Actually interrupt the processor here
tsunami->cchip->postRTC();
-
}
const char *
diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh
index d507355c3..a9f044ec9 100644
--- a/dev/tsunami_io.hh
+++ b/dev/tsunami_io.hh
@@ -30,8 +30,8 @@
* Tsunami Fake I/O Space mapping including RTC/timer interrupts
*/
-#ifndef __TSUNAMI_DMA_HH__
-#define __TSUNAMI_DMA_HH__
+#ifndef __DEV_TSUNAMI_IO_HH__
+#define __DEV_TSUNAMI_IO_HH__
#include "dev/io_device.hh"
#include "base/range.hh"
@@ -56,9 +56,11 @@ class TsunamiIO : public PioDevice
struct tm tm;
- /** In Tsunami RTC only has two i/o ports one for data and one for address,
- * so you write the address and then read/write the data. This store the
- * address you are going to be reading from on a read.
+ /**
+ * In Tsunami RTC only has two i/o ports one for data and one for
+ * address, so you write the address and then read/write the
+ * data. This store the address you are going to be reading from
+ * on a read.
*/
uint8_t RTCAddress;
@@ -132,38 +134,37 @@ class TsunamiIO : public PioDevice
class RTCEvent : public Event
{
protected:
- /** A pointer back to tsunami to create interrupt the processor. */
- Tsunami* tsunami;
+ /** A pointer back to tsunami to create interrupt the processor. */
+ Tsunami* tsunami;
public:
- /** RTC Event initializes the RTC event by scheduling an event
- * RTC_RATE times pre second. */
- RTCEvent(Tsunami* t);
-
- /**
- * Interrupth the processor and reschedule the event.
- * */
- virtual void process();
-
- /**
- * Return a description of this event.
- * @return a description
- */
- virtual const char *description();
-
- /**
- * Serialize this object to the given output stream.
- * @param os The stream to serialize to.
- */
- virtual void serialize(std::ostream &os);
-
-
- /**
- * Reconstruct the state of this object from a checkpoint.
- * @param cp The checkpoint use.
- * @param section The section name of this object
- */
- virtual void unserialize(Checkpoint *cp, const std::string &section);
- };
+ /** RTC Event initializes the RTC event by scheduling an event
+ * RTC_RATE times pre second. */
+ RTCEvent(Tsunami* t);
+
+ /**
+ * Interrupth the processor and reschedule the event.
+ */
+ virtual void process();
+
+ /**
+ * Return a description of this event.
+ * @return a description
+ */
+ virtual const char *description();
+
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
+ virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+ };
/** uip UpdateInProgess says that the rtc is updating, but we just fake it
* by alternating it on every read of the bit since we are going to
@@ -219,7 +220,6 @@ class TsunamiIO : public PioDevice
*/
uint32_t timerData;
-
public:
/**
* Return the freqency of the RTC
@@ -227,7 +227,6 @@ class TsunamiIO : public PioDevice
*/
Tick frequency() const { return RTC_RATE; }
-
/**
* Initialize all the data for devices supported by Tsunami I/O.
* @param name name of this device.
@@ -279,7 +278,6 @@ class TsunamiIO : public PioDevice
*/
virtual void serialize(std::ostream &os);
-
/**
* Reconstruct the state of this object from a checkpoint.
* @param cp The checkpoint use.
@@ -287,8 +285,7 @@ class TsunamiIO : public PioDevice
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
-
Tick cacheAccess(MemReqPtr &req);
};
-#endif // __TSUNAMI_IO_HH__
+#endif // __DEV_TSUNAMI_IO_HH__
diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy
index 1ec33a30c..af14ed9c3 100644
--- a/objects/MemTest.mpy
+++ b/objects/MemTest.mpy
@@ -3,10 +3,7 @@ simobj MemTest(SimObject):
cache = Param.BaseCache("L1 cache")
check_mem = Param.FunctionalMemory("check memory")
main_mem = Param.FunctionalMemory("hierarchical memory")
- max_loads_all_threads = Param.Counter(0,
- "terminate when all threads have reached this load count")
- max_loads_any_thread = Param.Counter(0,
- "terminate when any thread reaches this load count")
+ max_loads = Param.Counter("number of loads to execute")
memory_size = Param.Int(65536, "memory size")
percent_copies = Param.Percent(0, "target copy percentage")
percent_dest_unaligned = Param.Percent(50,
diff --git a/sim/main.cc b/sim/main.cc
index 1748294af..c15d24453 100644
--- a/sim/main.cc
+++ b/sim/main.cc
@@ -31,6 +31,8 @@
///
#include <sys/types.h>
#include <sys/stat.h>
+#include <errno.h>
+#include <libgen.h>
#include <stdlib.h>
#include <signal.h>
@@ -107,7 +109,7 @@ abortHandler(int sigtype)
}
/// Simulator executable name
-const char *myProgName = "";
+char *myProgName = "";
/// Show brief help message.
void
@@ -400,12 +402,6 @@ main(int argc, char **argv)
// Reset to put the stats in a consistent state.
Stats::reset();
- // Nothing to simulate if we don't have at least one CPU somewhere.
- if (BaseCPU::numSimulatedCPUs() == 0) {
- cerr << "Fatal: no CPUs to simulate." << endl;
- exit(1);
- }
-
warn("Entering event queue. Starting simulation...\n");
SimStartup();
while (!mainEventQueue.empty()) {
diff --git a/sim/process.cc b/sim/process.cc
index f09452c42..acc6762f8 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -88,8 +88,6 @@ Process::Process(const string &name,
fd_map[i] = -1;
}
- num_syscalls = 0;
-
// other parameters will be initialized when the program is loaded
}
@@ -145,21 +143,28 @@ Process::registerExecContext(ExecContext *xc)
execContexts.push_back(xc);
if (myIndex == 0) {
- // first exec context for this process... initialize & enable
-
// copy process's initial regs struct
xc->regs = *init_regs;
-
- // mark this context as active.
- // activate with zero delay so that we start ticking right
- // away on cycle 0
- xc->activate(0);
}
// return CPU number to caller and increment available CPU count
return myIndex;
}
+void
+Process::startup()
+{
+ if (execContexts.empty())
+ return;
+
+ // first exec context for this process... initialize & enable
+ ExecContext *xc = execContexts[0];
+
+ // mark this context as active.
+ // activate with zero delay so that we start ticking right
+ // away on cycle 0
+ xc->activate(0);
+}
void
Process::replaceExecContext(ExecContext *xc, int xcIndex)
diff --git a/sim/process.hh b/sim/process.hh
index 6c7bc4222..3bcc65da6 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -109,6 +109,8 @@ class Process : public SimObject
int stdout_fd,
int stderr_fd);
+ // post initialization startup
+ virtual void startup();
protected:
FunctionalMemory *memory;
diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py
index 9a48e2fa4..6393fb0b8 100644
--- a/sim/pyconfig/m5config.py
+++ b/sim/pyconfig/m5config.py
@@ -39,16 +39,6 @@ def panic(*args, **kwargs):
print >>sys.stderr, 'panic:', string
sys.exit(1)
-def AddToPath(path):
- path = os.path.realpath(path)
- if os.path.isdir(path) and path not in sys.path:
- sys.path.append(path)
-
-def Import(path):
- AddToPath(os.path.dirname(path))
- exec('from m5config import *')
- mpy_exec(file(path, 'r'))
-
def issequence(value):
return isinstance(value, tuple) or isinstance(value, list)
@@ -287,8 +277,7 @@ class MetaConfigNode(type):
# deal with them as params.
return super(MetaConfigNode, mcls).__new__(mcls, name, bases, priv)
- # initialization: start out with an empty _params dict (makes life
- # simpler if we can assume _params is always valid).
+ # initialization
def __init__(cls, name, bases, dict):
super(MetaConfigNode, cls).__init__(cls, name, bases, {})
@@ -396,8 +385,11 @@ class MetaConfigNode(type):
if cls._isvalue(attr):
return Value(cls, attr)
+ if attr == '_cppname' and hasattr(cls, 'type'):
+ return cls.type + '*'
+
raise AttributeError, \
- "object '%s' has no attribute '%s'" % (cls.__name__, cls)
+ "object '%s' has no attribute '%s'" % (cls.__name__, attr)
# Set attribute (called on foo.attr = value when foo is an
# instance of class cls).
@@ -577,11 +569,6 @@ class SimObject(ConfigNode):
for pname in param_names]
code += "\n".join(decls) + "\n"
code += "END_DECLARE_SIM_OBJECT_PARAMS(%s)\n\n" % name
- code += "BEGIN_INIT_SIM_OBJECT_PARAMS(%s)\n" % name
- inits = [" " + cls._params[pname].sim_init(pname) \
- for pname in param_names]
- code += ",\n".join(inits) + "\n"
- code += "END_INIT_SIM_OBJECT_PARAMS(%s)\n\n" % name
return code
_sim_code = classmethod(_sim_code)
@@ -620,14 +607,13 @@ class Node(object):
self.path = '.'.join(path)
def find(self, realtype, path):
- rtype = eval(realtype)
if not path:
- if issubclass(self.realtype, rtype):
+ if issubclass(self.realtype, realtype):
return self, True
obj = None
for child in self.children:
- if issubclass(child.realtype, rtype):
+ if issubclass(child.realtype, realtype):
if obj is not None:
raise AttributeError, \
'Super matched more than one: %s %s' % \
@@ -643,11 +629,11 @@ class Node(object):
last = path[-1]
if obj.child_names.has_key(last):
value = obj.child_names[last]
- if issubclass(value.realtype, rtype):
+ if issubclass(value.realtype, realtype):
return value, True
elif obj.param_names.has_key(last):
value = obj.param_names[last]
- rtype._convert(value.value)
+ realtype._convert(value.value)
return value.value, True
except KeyError:
pass
@@ -754,8 +740,7 @@ class Node(object):
except:
print 'exception in %s:%s' % (self.name, param.name)
raise
- ptype = eval(param.ptype)
- if isConfigNode(ptype) and string != "Null":
+ if isConfigNode(param.ptype) and string != "Null":
simobjs.append(string)
else:
label += '%s = %s\\n' % (param.name, string)
@@ -830,8 +815,10 @@ class Value(object):
# Regular parameter.
class _Param(object):
- def __init__(self, ptype, *args, **kwargs):
- self.ptype = ptype
+ def __init__(self, ptype_string, *args, **kwargs):
+ self.ptype_string = ptype_string
+ # can't eval ptype_string here to get ptype, since the type might
+ # not have been defined yet. Do it lazily in __getattr__.
if args:
if len(args) == 1:
@@ -858,44 +845,32 @@ class _Param(object):
if not hasattr(self, 'desc'):
raise TypeError, 'desc attribute missing'
+ def __getattr__(self, attr):
+ if attr == 'ptype':
+ try:
+ self.ptype = eval(self.ptype_string)
+ return self.ptype
+ except:
+ raise TypeError, 'Param.%s: undefined type' % self.ptype_string
+ else:
+ raise AttributeError, "'%s' object has no attribute '%s'" % \
+ (type(self).__name__, attr)
+
def valid(self, value):
if not isinstance(value, Proxy):
- ptype = eval(self.ptype)
- ptype._convert(value)
+ self.ptype._convert(value)
def convert(self, value):
- ptype = eval(self.ptype)
- return ptype._convert(value)
+ return self.ptype._convert(value)
def string(self, value):
- ptype = eval(self.ptype)
- return ptype._string(value)
-
- def get(self, name, instance, owner):
- # nothing to do if None or already correct type. Also allow NULL
- # pointer to be assigned where a SimObject is expected.
- try:
- if value == None or isinstance(value, self.ptype) or \
- isConfigNode(self.ptype) and \
- (isNullPointer(value) or issubclass(value, self.ptype)):
- return value
-
- except TypeError:
- # this type conversion will raise an exception if it's illegal
- return self.ptype(value)
+ return self.ptype._string(value)
def set(self, name, instance, value):
instance.__dict__[name] = value
def sim_decl(self, name):
- return 'Param<%s> %s;' % (self.ptype.__name__, name)
-
- def sim_init(self, name):
- if self.default == None:
- return 'INIT_PARAM(%s, "%s")' % (name, self.desc)
- else:
- return 'INIT_PARAM_DFLT(%s, "%s", %s)' % \
- (name, self.desc, str(self.default))
+ return '%s %s;' % (self.ptype._cppname, name)
class _ParamProxy(object):
def __init__(self, type):
@@ -931,13 +906,12 @@ class _VectorParam(_Param):
if value == None:
return True
- ptype = eval(self.ptype)
if issequence(value):
for val in value:
if not isinstance(val, Proxy):
- ptype._convert(val)
+ self.ptype._convert(val)
elif not isinstance(value, Proxy):
- ptype._convert(value)
+ self.ptype._convert(value)
# Convert assigned value to appropriate type. If the RHS is not a
# list or tuple, it generates a single-element list.
@@ -945,23 +919,21 @@ class _VectorParam(_Param):
if value == None:
return []
- ptype = eval(self.ptype)
if issequence(value):
# list: coerce each element into new list
- return [ ptype._convert(v) for v in value ]
+ return [ self.ptype._convert(v) for v in value ]
else:
# singleton: coerce & wrap in a list
- return ptype._convert(value)
+ return self.ptype._convert(value)
def string(self, value):
- ptype = eval(self.ptype)
if issequence(value):
- return ' '.join([ ptype._string(v) for v in value])
+ return ' '.join([ self.ptype._string(v) for v in value])
else:
- return ptype._string(value)
+ return self.ptype._string(value)
def sim_decl(self, name):
- return 'VectorParam<%s> %s;' % (self.ptype.__name__, name)
+ return 'std::vector<%s> %s;' % (self.ptype._cppname, name)
class _VectorParamProxy(_ParamProxy):
# E.g., VectorParam.Int(5, "number of widgets")
@@ -1008,14 +980,14 @@ class _CheckedInt(object):
_string = classmethod(_string)
class CheckedInt(type):
- def __new__(cls, name, min, max):
+ def __new__(cls, cppname, min, max):
# New class derives from _CheckedInt base with proper bounding
# parameters
- dict = { '_name' : name, '_min' : min, '_max' : max }
- return type.__new__(cls, name, (_CheckedInt, ), dict)
+ dict = { '_cppname' : cppname, '_min' : min, '_max' : max }
+ return type.__new__(cls, cppname, (_CheckedInt, ), dict)
class CheckedIntType(CheckedInt):
- def __new__(cls, name, size, unsigned):
+ def __new__(cls, cppname, size, unsigned):
dict = {}
if unsigned:
min = 0
@@ -1024,7 +996,7 @@ class CheckedIntType(CheckedInt):
min = -(2 ** (size - 1))
max = (2 ** (size - 1)) - 1
- return super(cls, CheckedIntType).__new__(cls, name, min, max)
+ return super(cls, CheckedIntType).__new__(cls, cppname, min, max)
Int = CheckedIntType('int', 32, False)
Unsigned = CheckedIntType('unsigned', 32, True)
@@ -1067,15 +1039,15 @@ def RangeSize(start, size):
class Range(type):
def __new__(cls, type):
- dict = { '_name' : 'Range<%s>' + type._name, '_type' : type }
- cname = 'Range_' + type.__name__
- return super(cls, Range).__new__(cls, cname, (_Range, ), dict)
+ dict = { '_cppname' : 'Range<%s>' % type._cppname, '_type' : type }
+ clsname = 'Range_' + type.__name__
+ return super(cls, Range).__new__(cls, clsname, (_Range, ), dict)
AddrRange = Range(Addr)
# Boolean parameter type.
class Bool(object):
- _name = 'bool'
+ _cppname = 'bool'
def _convert(value):
t = type(value)
if t == bool:
@@ -1103,7 +1075,7 @@ class Bool(object):
# String-valued parameter.
class String(object):
- _name = 'string'
+ _cppname = 'string'
# Constructor. Value must be Python string.
def _convert(cls,value):
@@ -1143,7 +1115,7 @@ class NextEthernetAddr(object):
self.addr = IncEthernetAddr(self.addr, inc)
class EthernetAddr(object):
- _name = 'EthAddr'
+ _cppname = 'EthAddr'
def _convert(cls, value):
if value == NextEthernetAddr:
@@ -1175,7 +1147,7 @@ class EthernetAddr(object):
# only one copy of a particular node
class NullSimObject(object):
__metaclass__ = Singleton
- _name = 'NULL'
+ _cppname = 'NULL'
def __call__(cls):
return cls
@@ -1278,21 +1250,6 @@ G = K*M
#####################################################################
-# Munge an arbitrary Python code string to get it to execute (mostly
-# dealing with indentation). Stolen from isa_parser.py... see
-# comments there for a more detailed description.
-#def fixPythonIndentation(s):
-# # get rid of blank lines first
-# s = re.sub(r'(?m)^\s*\n', '', s);
-# if (s != '' and re.match(r'[ \t]', s[0])):
-# s = 'if 1:\n' + s
-# return s
-
-# Hook to generate C++ parameter code.
-def gen_sim_code(file):
- for objname in sim_object_list:
- print >> file, eval("%s._sim_code()" % objname)
-
# The final hook to generate .ini files. Called from configuration
# script once config is built.
def instantiate(root):
diff --git a/test/genini.py b/test/genini.py
index 73e7012f6..9c28ef361 100644..100755
--- a/test/genini.py
+++ b/test/genini.py
@@ -30,13 +30,14 @@ from os.path import join as joinpath, realpath
mypath = sys.path[0]
sys.path.append(joinpath(mypath, '..'))
-sys.path.append(joinpath(mypath, '../configs/kernel'))
sys.path.append(joinpath(mypath, '../util/pbs'))
sys.path.append(joinpath(mypath, '../sim/pyconfig'))
-from importer import mpy_exec, mpy_execfile, AddToPath
+from importer import AddToPath, LoadMpyFile
from m5config import *
+AddToPath('.')
+
try:
opts, args = getopt.getopt(sys.argv[1:], '-E:I:')
for opt,arg in opts:
@@ -55,8 +56,7 @@ except getopt.GetoptError:
sys.exit('Improper Usage')
for arg in args:
- AddToPath(os.path.dirname(arg))
- mpy_execfile(arg)
+ LoadMpyFile(arg)
if globals().has_key('root') and isinstance(root, type) \
and issubclass(root, Root):
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-27 05:48:36 +0000