diff options
51 files changed, 4084 insertions, 445 deletions
diff --git a/SConstruct b/SConstruct index b18fe66d3..259b6c583 100644 --- a/SConstruct +++ b/SConstruct @@ -494,10 +494,10 @@ for build_path in build_paths: exports = 'env') # Set up the regression tests for each build. -# for e in envList: -# SConscript('m5-test/SConscript', -# build_dir = os.path.join(build_dir, 'test', e.Label), -# exports = { 'env' : e }, duplicate = False) + for e in envList: + SConscript('tests/SConscript', + build_dir = os.path.join(build_path, 'test', e.Label), + exports = { 'env' : e }, duplicate = False) Help(help_text) diff --git a/configs/test/fs.py b/configs/test/fs.py index 41c3f8cc0..7e89b7dd4 100644 --- a/configs/test/fs.py +++ b/configs/test/fs.py @@ -3,10 +3,16 @@ import optparse, os, sys import m5 from m5.objects import * from SysPaths import * +from FullO3Config import * parser = optparse.OptionParser() +parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-t", "--timing", action="store_true") +parser.add_option("-m", "--maxtick", type="int") +parser.add_option("--maxtime", type="float") +parser.add_option("--dual", help="Run full system using dual systems", + action="store_true") (options, args) = parser.parse_args() @@ -21,180 +27,53 @@ script.dir = '/z/saidi/work/m5.newmem/configs/boot' linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img')) -class IdeControllerPciData(PciConfigData): - VendorID = 0x8086 - DeviceID = 0x7111 - Command = 0x0 - Status = 0x280 - Revision = 0x0 - ClassCode = 0x01 - SubClassCode = 0x01 - ProgIF = 0x85 - BAR0 = 0x00000001 - BAR1 = 0x00000001 - BAR2 = 0x00000001 - BAR3 = 0x00000001 - BAR4 = 0x00000001 - BAR5 = 0x00000001 - InterruptLine = 0x1f - InterruptPin = 0x01 - BAR0Size = '8B' - BAR1Size = '4B' - BAR2Size = '8B' - BAR3Size = '4B' - BAR4Size = '16B' - -class SinicPciData(PciConfigData): - VendorID = 0x1291 - DeviceID = 0x1293 - Status = 0x0290 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000000 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x34 - MinimumGrant = 0xb0 - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '64kB' - -class NSGigEPciData(PciConfigData): - VendorID = 0x100B - DeviceID = 0x0022 - Status = 0x0290 - SubClassCode = 0x00 - ClassCode = 0x02 - ProgIF = 0x00 - BAR0 = 0x00000001 - BAR1 = 0x00000000 - BAR2 = 0x00000000 - BAR3 = 0x00000000 - BAR4 = 0x00000000 - BAR5 = 0x00000000 - MaximumLatency = 0x34 - MinimumGrant = 0xb0 - InterruptLine = 0x1e - InterruptPin = 0x01 - BAR0Size = '256B' - BAR1Size = '4kB' - -class LinuxRootDisk(IdeDisk): - raw_image = RawDiskImage(image_file=linux_image, read_only=True) - image = CowDiskImage(child=Parent.raw_image, read_only=False) - -class LinuxSwapDisk(IdeDisk): - raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'), - read_only=True) - image = CowDiskImage(child = Parent.raw_image, read_only=False) - -class SpecwebFilesetDisk(IdeDisk): - raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'), - read_only=True) - image = CowDiskImage(child = Parent.raw_image, read_only=False) +class CowIdeDisk(IdeDisk): + image = CowDiskImage(child=RawDiskImage(read_only=True), + read_only=False) + + def childImage(self, ci): + self.image.child.image_file = ci class BaseTsunami(Tsunami): - cchip = TsunamiCChip(pio_addr=0x801a0000000) - pchip = TsunamiPChip(pio_addr=0x80180000000) - pciconfig = PciConfigAll() - fake_sm_chip = IsaFake(pio_addr=0x801fc000370) - - fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) - fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) - fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) - fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) - - fake_ppc = IsaFake(pio_addr=0x801fc0003bc) - - fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) - - fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) - fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) - fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) - fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) - fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) - fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) - fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) - fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) - fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) - fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) - - fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) - fake_ata1 = IsaFake(pio_addr=0x801fc000170) - - fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') - io = TsunamiIO(pio_addr=0x801fc000000) - uart = Uart8250(pio_addr=0x801fc0003f8) ethernet = NSGigE(configdata=NSGigEPciData(), pci_bus=0, pci_dev=1, pci_func=0) etherint = NSGigEInt(device=Parent.ethernet) - console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk) - -class LinuxTsunami(BaseTsunami): - disk0 = LinuxRootDisk(driveID='master') - disk1 = SpecwebFilesetDisk(driveID='slave') - disk2 = LinuxSwapDisk(driveID='master') - ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2], - configdata=IdeControllerPciData(), + ide = IdeController(disks=[Parent.disk0, Parent.disk2], pci_func=0, pci_dev=0, pci_bus=0) class MyLinuxAlphaSystem(LinuxAlphaSystem): - magicbus = Bus(bus_id=0) - magicbus2 = Bus(bus_id=1) + iobus = Bus(bus_id=0) + membus = Bus(bus_id=1) bridge = Bridge() physmem = PhysicalMemory(range = AddrRange('128MB')) - bridge.side_a = magicbus.port - bridge.side_b = magicbus2.port - physmem.port = magicbus2.port - tsunami = LinuxTsunami() - tsunami.cchip.pio = magicbus.port - tsunami.pchip.pio = magicbus.port - tsunami.pciconfig.pio = magicbus.default - tsunami.fake_sm_chip.pio = magicbus.port - tsunami.ethernet.pio = magicbus.port - tsunami.ethernet.dma = magicbus.port - tsunami.ethernet.config = magicbus.port - tsunami.fake_uart1.pio = magicbus.port - tsunami.fake_uart2.pio = magicbus.port - tsunami.fake_uart3.pio = magicbus.port - tsunami.fake_uart4.pio = magicbus.port - tsunami.ide.pio = magicbus.port - tsunami.ide.dma = magicbus.port - tsunami.ide.config = magicbus.port - tsunami.fake_ppc.pio = magicbus.port - tsunami.fake_OROM.pio = magicbus.port - tsunami.fake_pnp_addr.pio = magicbus.port - tsunami.fake_pnp_write.pio = magicbus.port - tsunami.fake_pnp_read0.pio = magicbus.port - tsunami.fake_pnp_read1.pio = magicbus.port - tsunami.fake_pnp_read2.pio = magicbus.port - tsunami.fake_pnp_read3.pio = magicbus.port - tsunami.fake_pnp_read4.pio = magicbus.port - tsunami.fake_pnp_read5.pio = magicbus.port - tsunami.fake_pnp_read6.pio = magicbus.port - tsunami.fake_pnp_read7.pio = magicbus.port - tsunami.fake_ata0.pio = magicbus.port - tsunami.fake_ata1.pio = magicbus.port - tsunami.fb.pio = magicbus.port - tsunami.io.pio = magicbus.port - tsunami.uart.pio = magicbus.port - tsunami.console.pio = magicbus.port - raw_image = RawDiskImage(image_file=disk('linux-latest.img'), - read_only=True) - simple_disk = SimpleDisk(disk=Parent.raw_image) + bridge.side_a = iobus.port + bridge.side_b = membus.port + physmem.port = membus.port + disk0 = CowIdeDisk(driveID='master') + disk2 = CowIdeDisk(driveID='master') + disk0.childImage(linux_image) + disk2.childImage(disk('linux-bigswap2.img')) + tsunami = BaseTsunami() + tsunami.attachIO(iobus) + tsunami.ide.pio = iobus.port + tsunami.ide.dma = iobus.port + tsunami.ide.config = iobus.port + tsunami.ethernet.pio = iobus.port + tsunami.ethernet.dma = iobus.port + tsunami.ethernet.config = iobus.port + simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image, + read_only = True)) intrctrl = IntrControl() - if options.timing: + if options.detailed: + cpu = DetailedO3CPU() + elif options.timing: cpu = TimingSimpleCPU() mem_mode = 'timing' else: cpu = AtomicSimpleCPU() - cpu.mem = magicbus2 - cpu.icache_port = magicbus2.port - cpu.dcache_port = magicbus2.port + cpu.mem = membus + cpu.icache_port = membus.port + cpu.dcache_port = membus.port cpu.itb = AlphaITB() cpu.dtb = AlphaDTB() cpu.clock = '2GHz' @@ -203,14 +82,10 @@ class MyLinuxAlphaSystem(LinuxAlphaSystem): pal = binary('ts_osfpal') console = binary('console') boot_osflags = 'root=/dev/hda1 console=ttyS0' -# readfile = os.path.join(test_base, 'halt.sh') - - -class TsunamiRoot(System): +class TsunamiRoot(Root): pass - def DualRoot(clientSystem, serverSystem): self = Root() self.client = clientSystem @@ -223,9 +98,12 @@ def DualRoot(clientSystem, serverSystem): self.clock = '1THz' return self -root = DualRoot( - MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), - MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) +if options.dual: + root = DualRoot( + MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), + MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) +else: + root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem()) m5.instantiate(root) @@ -237,6 +115,13 @@ m5.instantiate(root) # m5.checkpoint(root, 'cptA') -exit_event = m5.simulate() +if options.maxtick: + exit_event = m5.simulate(options.maxtick) +elif options.maxtime: + simtime = int(options.maxtime * root.clock.value) + print "simulating for: ", simtime + exit_event = m5.simulate(simtime) +else: + exit_event = m5.simulate() print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause() diff --git a/configs/test/test.py b/configs/test/test.py index feb44e2d1..3b637f70f 100644 --- a/configs/test/test.py +++ b/configs/test/test.py @@ -1,38 +1,14 @@ # Simple test script # # Alpha: "m5 test.py" -# MIPS: "m5 test.py -a Mips -c hello_mips" - -import os, optparse, sys +# MIPS: "m5 test.py -c hello_mips" import m5 +import os, optparse, sys +m5.AddToPath('../common') +from SEConfig import * from m5.objects import * -from FullO3Config import * - -# parse command-line arguments -parser = optparse.OptionParser() - -parser.add_option("-c", "--cmd", default="hello", - help="The binary to run in syscall emulation mode.") -parser.add_option("-o", "--options", default="", - help="The options to pass to the binary, use \" \" around the entire\ - string.") -parser.add_option("-i", "--input", default="", - help="A file of input to give to the binary.") -parser.add_option("-t", "--timing", action="store_true", - help="Use simple timing CPU.") -parser.add_option("-d", "--detailed", action="store_true", - help="Use detailed CPU.") -parser.add_option("-m", "--maxtick", type="int", - help="Set the maximum number of ticks to run for") - -(options, args) = parser.parse_args() - -if args: - print "Error: script doesn't take any positional arguments" - sys.exit(1) -# build configuration this_dir = os.path.dirname(__file__) process = LiveProcess() @@ -41,16 +17,7 @@ process.cmd = options.cmd + " " + options.options if options.input != "": process.input = options.input -magicbus = Bus() -mem = PhysicalMemory() - -if options.timing and options.detailed: - print "Error: you may only specify one cpu model"; - sys.exit(1) - -if options.timing: - cpu = TimingSimpleCPU() -elif options.detailed: +if options.detailed: #check for SMT workload workloads = options.cmd.split(';') if len(workloads) > 1: @@ -70,22 +37,10 @@ elif options.detailed: process += [smt_process, ] smt_idx += 1 - cpu = DetailedO3CPU() -else: - cpu = AtomicSimpleCPU() -cpu.workload = process -cpu.mem = magicbus -cpu.icache_port=magicbus.port -cpu.dcache_port=magicbus.port - -system = System(physmem = mem, cpu = cpu) +root = MySESystem(process) if options.timing or options.detailed: - system.mem_mode = 'timing' - - -mem.port = magicbus.port -root = Root(system = system) + root.system.mem_mode = 'timing' # instantiate configuration m5.instantiate(root) diff --git a/src/SConscript b/src/SConscript index 9825cafe7..812089a00 100644 --- a/src/SConscript +++ b/src/SConscript @@ -98,6 +98,7 @@ base_sources = Split(''' mem/packet.cc mem/physical.cc mem/port.cc + mem/tport.cc mem/cache/base_cache.cc mem/cache/cache.cc @@ -298,7 +299,7 @@ alpha_eio_sources = Split(''' encumbered/eio/eio.cc ''') -if env['TARGET_ISA'] == 'ALPHA_ISA': +if env['TARGET_ISA'] == 'alpha': syscall_emulation_sources += alpha_eio_sources memtest_sources = Split(''' diff --git a/src/arch/SConscript b/src/arch/SConscript index bc517341a..0a5962889 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -140,8 +140,15 @@ def isa_desc_emitter(target, source, env): # Pieces are in place, so create the builder. python = sys.executable # use same Python binary used to run scons -isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', - emitter = isa_desc_emitter) + +# Also include the CheckerCPU as one of the models if it is being +# enabled via command line. +if env['USE_CHECKER']: + isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU', + emitter = isa_desc_emitter) +else: + isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', + emitter = isa_desc_emitter) env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) diff --git a/src/cpu/SConscript b/src/cpu/SConscript index bc4ec7923..7d45c7870 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -71,7 +71,8 @@ virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) c # Generate a temporary CPU list, including the CheckerCPU if # it's enabled. This isn't used for anything else other than StaticInst # headers. -temp_cpu_list = env['CPU_MODELS'] +temp_cpu_list = env['CPU_MODELS'][:] + if env['USE_CHECKER']: temp_cpu_list.append('CheckerCPU') @@ -113,6 +114,9 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] # ################################################################# +# Keep a list of CPU models that support SMT +env['SMT_CPU_MODELS'] = [] + sources = [] need_simple_base = False @@ -156,6 +160,7 @@ if 'O3CPU' in env['CPU_MODELS']: ''') if env['USE_CHECKER']: sources += Split('o3/checker_builder.cc') + env['SMT_CPU_MODELS'].append('O3CPU') if 'OzoneCPU' in env['CPU_MODELS']: need_bp_unit = True diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index a508c56ba..6d6ae1e0a 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -170,7 +170,7 @@ class CheckerCPU : public BaseCPU virtual Counter totalInstructions() const { - return numInst - startNumInst; + return 0; } // number of simulated loads diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 904af1071..c667d633a 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -996,6 +996,12 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) // Check if the instruction caused a fault. If so, trap. Fault inst_fault = head_inst->getFault(); + // DTB will sometimes need the machine instruction for when + // faults happen. So we will set it here, prior to the DTB + // possibly needing it for its fault. + thread[tid]->setInst( + static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); + if (inst_fault != NoFault) { head_inst->setCompleted(); DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", @@ -1018,12 +1024,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) // execution doesn't generate extra squashes. thread[tid]->inSyscall = true; - // DTB will sometimes need the machine instruction for when - // faults happen. So we will set it here, prior to the DTB - // possibly needing it for its fault. - thread[tid]->setInst( - static_cast<TheISA::MachInst>(head_inst->staticInst->machInst)); - // Execute the trap. Although it's slightly unrealistic in // terms of timing (as it doesn't wait for the full timing of // the trap event to complete before updating state), it's diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index b407f4fcc..c43cc2cf8 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -745,7 +745,8 @@ template <class Impl> void FullO3CPU<Impl>::serialize(std::ostream &os) { - SERIALIZE_ENUM(_status); + SimObject::State so_state = SimObject::getState(); + SERIALIZE_ENUM(so_state); BaseCPU::serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); @@ -766,7 +767,8 @@ template <class Impl> void FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ENUM(_status); + SimObject::State so_state; + UNSERIALIZE_ENUM(so_state); BaseCPU::unserialize(cp, section); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); @@ -1045,7 +1047,8 @@ template <class Impl> void FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) { - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); + int idx = reg_idx + TheISA::FP_Base_DepTag; + PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); regFile.setFloatReg(phys_reg, val); } @@ -1054,7 +1057,8 @@ template <class Impl> void FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) { - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); + int idx = reg_idx + TheISA::FP_Base_DepTag; + PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); regFile.setFloatReg(phys_reg, val, 64); } @@ -1063,7 +1067,8 @@ template <class Impl> void FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) { - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); + int idx = reg_idx + TheISA::FP_Base_DepTag; + PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); regFile.setFloatRegBits(phys_reg, val); } diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index fb9afde54..6c6be4787 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -31,11 +31,12 @@ #ifndef __CPU_O3_IEW_HH__ #define __CPU_O3_IEW_HH__ +#include "config/full_system.hh" + #include <queue> #include "base/statistics.hh" #include "base/timebuf.hh" -#include "config/full_system.hh" #include "cpu/o3/comm.hh" #include "cpu/o3/scoreboard.hh" #include "cpu/o3/lsq.hh" @@ -215,7 +216,7 @@ class DefaultIEW if (++wbOutstanding == wbMax) ableToIssue = false; DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); -#if DEBUG +#ifdef DEBUG wbList.insert(sn); #endif } @@ -225,13 +226,13 @@ class DefaultIEW if (wbOutstanding-- == wbMax) ableToIssue = true; DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); -#if DEBUG +#ifdef DEBUG assert(wbList.find(sn) != wbList.end()); wbList.erase(sn); #endif } -#if DEBUG +#ifdef DEBUG std::set<InstSeqNum> wbList; void dumpWb() diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index a76a73f0c..512b5a63c 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -601,6 +601,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) // Tell IQ/mem dep unit that this instruction will need to be // rescheduled eventually iewStage->rescheduleMemInst(load_inst); + iewStage->decrWb(load_inst->seqNum); ++lsqRescheduledLoads; // Do not generate a writeback event as this instruction is not diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 85b150cd9..4f5dbbf1c 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -790,6 +790,7 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) // Squashed instructions do not need to complete their access. if (inst->isSquashed()) { + iewStage->decrWb(inst->seqNum); assert(!inst->isStore()); ++lsqIgnoredResponses; return; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 1752b2b5b..c396f5033 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -159,18 +159,20 @@ AtomicSimpleCPU::~AtomicSimpleCPU() void AtomicSimpleCPU::serialize(ostream &os) { - SERIALIZE_ENUM(_status); - BaseSimpleCPU::serialize(os); + SimObject::State so_state = SimObject::getState(); + SERIALIZE_ENUM(so_state); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); + BaseSimpleCPU::serialize(os); } void AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) { - UNSERIALIZE_ENUM(_status); - BaseSimpleCPU::unserialize(cp, section); + SimObject::State so_state; + UNSERIALIZE_ENUM(so_state); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); + BaseSimpleCPU::unserialize(cp, section); } void @@ -178,6 +180,10 @@ AtomicSimpleCPU::resume() { assert(system->getMemoryMode() == System::Atomic); changeState(SimObject::Running); + if (thread->status() == ThreadContext::Active) { + if (!tickEvent.scheduled()) + tickEvent.schedule(curTick); + } } void diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index d59ca01aa..b602af558 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -126,8 +126,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); - virtual void resume(); + void switchOut(); void takeOverFrom(BaseCPU *oldCPU); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index af10e64d7..240696c2b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -178,8 +178,8 @@ void BaseSimpleCPU::serialize(ostream &os) { BaseCPU::serialize(os); - SERIALIZE_SCALAR(inst); - nameOut(os, csprintf("%s.xc", name())); +// SERIALIZE_SCALAR(inst); + nameOut(os, csprintf("%s.xc.0", name())); thread->serialize(os); } @@ -187,8 +187,8 @@ void BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) { BaseCPU::unserialize(cp, section); - UNSERIALIZE_SCALAR(inst); - thread->unserialize(cp, csprintf("%s.xc", section)); +// UNSERIALIZE_SCALAR(inst); + thread->unserialize(cp, csprintf("%s.xc.0", section)); } void diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index d2c2c7c47..5c1654f7e 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -85,8 +85,16 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status) panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); } + +void +TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) +{ + pkt = _pkt; + Event::schedule(t); +} + TimingSimpleCPU::TimingSimpleCPU(Params *p) - : BaseSimpleCPU(p), icachePort(this), dcachePort(this) + : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) { _status = Idle; ifetch_pkt = dcache_pkt = NULL; @@ -103,14 +111,16 @@ TimingSimpleCPU::~TimingSimpleCPU() void TimingSimpleCPU::serialize(ostream &os) { - SERIALIZE_ENUM(_status); + SimObject::State so_state = SimObject::getState(); + SERIALIZE_ENUM(so_state); BaseSimpleCPU::serialize(os); } void TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) { - UNSERIALIZE_ENUM(_status); + SimObject::State so_state; + UNSERIALIZE_ENUM(so_state); BaseSimpleCPU::unserialize(cp, section); } @@ -135,7 +145,9 @@ TimingSimpleCPU::resume() if (_status != SwitchedOut && _status != Idle) { // Delete the old event if it existed. if (fetchEvent) { - assert(!fetchEvent->scheduled()); + if (fetchEvent->scheduled()) + fetchEvent->deschedule(); + delete fetchEvent; } @@ -458,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt) } } +void +TimingSimpleCPU::IcachePort::ITickEvent::process() +{ + cpu->completeIfetch(pkt); +} bool TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) { - cpu->completeIfetch(pkt); + // These next few lines could be replaced with something faster + // who knows what though + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeIfetch(pkt); + else + tickEvent.schedule(pkt, time); + return true; } @@ -519,11 +546,25 @@ TimingSimpleCPU::completeDrain() bool TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) { - cpu->completeDataAccess(pkt); + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeDataAccess(pkt); + else + tickEvent.schedule(pkt, time); + return true; } void +TimingSimpleCPU::DcachePort::DTickEvent::process() +{ + cpu->completeDataAccess(pkt); +} + +void TimingSimpleCPU::DcachePort::recvRetry() { // we shouldn't get a retry unless we have a packet that we're diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index ac36e5c99..d03fa4bc0 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -74,11 +74,12 @@ class TimingSimpleCPU : public BaseSimpleCPU { protected: TimingSimpleCPU *cpu; + Tick lat; public: - CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) - : Port(_name), cpu(_cpu) + CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) + : Port(_name), cpu(_cpu), lat(_lat) { } protected: @@ -92,14 +93,26 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { resp.clear(); snoop.clear(); } + + struct TickEvent : public Event + { + Packet *pkt; + TimingSimpleCPU *cpu; + + TickEvent(TimingSimpleCPU *_cpu) + :Event(&mainEventQueue), cpu(_cpu) {} + const char *description() { return "Timing CPU clock event"; } + void schedule(Packet *_pkt, Tick t); + }; + }; class IcachePort : public CpuPort { public: - IcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu->name() + "-iport", _cpu) + IcachePort(TimingSimpleCPU *_cpu, Tick _lat) + : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) { } protected: @@ -107,14 +120,26 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); virtual void recvRetry(); + + struct ITickEvent : public TickEvent + { + + ITickEvent(TimingSimpleCPU *_cpu) + : TickEvent(_cpu) {} + void process(); + const char *description() { return "Timing CPU clock event"; } + }; + + ITickEvent tickEvent; + }; class DcachePort : public CpuPort { public: - DcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu->name() + "-dport", _cpu) + DcachePort(TimingSimpleCPU *_cpu, Tick _lat) + : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) { } protected: @@ -122,6 +147,17 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); virtual void recvRetry(); + + struct DTickEvent : public TickEvent + { + DTickEvent(TimingSimpleCPU *_cpu) + : TickEvent(_cpu) {} + void process(); + const char *description() { return "Timing CPU clock event"; } + }; + + DTickEvent tickEvent; + }; IcachePort icachePort; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index af1db2ff2..5f86cf2b7 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -196,6 +196,7 @@ SimpleThread::copyState(ThreadContext *oldContext) #if !FULL_SYSTEM funcExeInst = oldContext->readFuncExeInst(); #endif + inst = oldContext->getInst(); } void diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 660efabfd..b51a93190 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -36,8 +36,7 @@ PioPort::PioPort(PioDevice *dev, System *s, std::string pname) - : Port(dev->name() + pname), device(dev), sys(s), - outTiming(0), drainEvent(NULL) + : SimpleTimingPort(dev->name() + pname), device(dev), sys(s) { } @@ -61,48 +60,6 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) } -void -PioPort::recvRetry() -{ - bool result = true; - while (result && transmitList.size()) { - result = Port::sendTiming(transmitList.front()); - if (result) - transmitList.pop_front(); - } - if (transmitList.size() == 0 && drainEvent) { - drainEvent->process(); - drainEvent = NULL; - } -} - -void -PioPort::SendEvent::process() -{ - port->outTiming--; - assert(port->outTiming >= 0); - if (port->Port::sendTiming(packet)) - if (port->transmitList.size() == 0 && port->drainEvent) { - port->drainEvent->process(); - port->drainEvent = NULL; - } - return; - - port->transmitList.push_back(packet); -} - -void -PioPort::resendNacked(Packet *pkt) { - pkt->reinitNacked(); - if (transmitList.size()) { - transmitList.push_front(pkt); - } else { - if (!Port::sendTiming(pkt)) - transmitList.push_front(pkt); - } -}; - - bool PioPort::recvTiming(Packet *pkt) { @@ -117,15 +74,6 @@ PioPort::recvTiming(Packet *pkt) return true; } -unsigned int -PioPort::drain(Event *de) -{ - if (outTiming == 0 && transmitList.size() == 0) - return 0; - drainEvent = de; - return 1; -} - PioDevice::~PioDevice() { if (pioPort) diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index fa3f98247..22a32e73a 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -37,6 +37,7 @@ #include "mem/packet_impl.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" +#include "mem/tport.hh" class Platform; class PioDevice; @@ -48,13 +49,9 @@ class System; * sensitive to an address range use. The port takes all the memory * access types and roles them into one read() and write() call that the device * must respond to. The device must also provide the addressRanges() function - * with which it returns the address ranges it is interested in. An extra - * sendTiming() function is implemented which takes an delay. In this way the - * device can immediatly call sendTiming(pkt, time) after processing a request - * and the request will be handled by the port even if the port bus the device - * connects to is blocked. - */ -class PioPort : public Port + * with which it returns the address ranges it is interested in. */ + +class PioPort : public SimpleTimingPort { protected: /** The device that this port serves. */ @@ -64,10 +61,6 @@ class PioPort : public Port * we are currently operating in. */ System *sys; - /** A list of outgoing timing response packets that haven't been serviced - * yet. */ - std::list<Packet*> transmitList; - /** The current status of the peer(bus) that we are connected to. */ Status peerStatus; @@ -82,53 +75,9 @@ class PioPort : public Port virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); - void resendNacked(Packet *pkt); - - /** - * This class is used to implemented sendTiming() with a delay. When a delay - * is requested a new event is created. When the event time expires it - * attempts to send the packet. If it cannot, the packet is pushed onto the - * transmit list to be sent when recvRetry() is called. */ - class SendEvent : public Event - { - PioPort *port; - Packet *packet; - - SendEvent(PioPort *p, Packet *pkt, Tick t) - : Event(&mainEventQueue), port(p), packet(pkt) - { schedule(curTick + t); } - - virtual void process(); - - virtual const char *description() - { return "Future scheduled sendTiming event"; } - - friend class PioPort; - }; - - /** Number of timing requests that are emulating the device timing before - * attempting to end up on the bus. - */ - int outTiming; - - /** If we need to drain, keep the drain event around until we're done - * here.*/ - Event *drainEvent; - - /** Schedule a sendTiming() event to be called in the future. */ - void sendTiming(Packet *pkt, Tick time) - { outTiming++; new PioPort::SendEvent(this, pkt, time); } - - /** This function is notification that the device should attempt to send a - * packet again. */ - virtual void recvRetry(); - public: PioPort(PioDevice *dev, System *s, std::string pname = "-pioport"); - unsigned int drain(Event *de); - - friend class PioPort::SendEvent; }; diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 2d66602ab..291c70d8c 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Ron Dreslinski + * Ali Saidi */ #include <sys/types.h> @@ -52,24 +53,6 @@ using namespace std; using namespace TheISA; -PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet *pkt, MemoryPort* _m) - : Event(&mainEventQueue, CPU_Tick_Pri), pkt(pkt), memoryPort(_m) -{ - - this->setFlags(AutoDelete); -} - -void -PhysicalMemory::MemResponseEvent::process() -{ - memoryPort->sendTiming(pkt); -} - -const char * -PhysicalMemory::MemResponseEvent::description() -{ - return "Physical Memory Timing Access respnse event"; -} PhysicalMemory::PhysicalMemory(const string &n, Tick latency) : MemObject(n),base_addr(0), pmem_addr(NULL), port(NULL), lat(latency) @@ -124,27 +107,8 @@ PhysicalMemory::deviceBlockSize() return 0; } -bool -PhysicalMemory::doTimingAccess (Packet *pkt, MemoryPort* memoryPort) -{ - doFunctionalAccess(pkt); - - // turn packet around to go back to requester - pkt->makeTimingResponse(); - MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort); - response->schedule(curTick + lat); - - return true; -} Tick -PhysicalMemory::doAtomicAccess(Packet *pkt) -{ - doFunctionalAccess(pkt); - return lat; -} - -void PhysicalMemory::doFunctionalAccess(Packet *pkt) { assert(pkt->getAddr() + pkt->getSize() < pmem_size); @@ -170,6 +134,7 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt) } pkt->result = Packet::Success; + return lat; } Port * @@ -195,7 +160,7 @@ PhysicalMemory::recvStatusChange(Port::Status status) PhysicalMemory::MemoryPort::MemoryPort(const std::string &_name, PhysicalMemory *_memory) - : Port(_name), memory(_memory) + : SimpleTimingPort(_name), memory(_memory) { } void @@ -228,13 +193,20 @@ PhysicalMemory::MemoryPort::deviceBlockSize() bool PhysicalMemory::MemoryPort::recvTiming(Packet *pkt) { - return memory->doTimingAccess(pkt, this); + assert(pkt->result != Packet::Nacked); + + Tick latency = memory->doFunctionalAccess(pkt); + + pkt->makeTimingResponse(); + sendTiming(pkt, latency); + + return true; } Tick PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt) { - return memory->doAtomicAccess(pkt); + return memory->doFunctionalAccess(pkt); } void @@ -243,7 +215,16 @@ PhysicalMemory::MemoryPort::recvFunctional(Packet *pkt) memory->doFunctionalAccess(pkt); } - +unsigned int +PhysicalMemory::drain(Event *de) +{ + int count = port->drain(de); + if (count) + changeState(Draining); + else + changeState(Drained); + return count; +} void PhysicalMemory::serialize(ostream &os) diff --git a/src/mem/physical.hh b/src/mem/physical.hh index 50fa75ed3..b549c1f8b 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -37,7 +37,7 @@ #include "base/range.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" -#include "mem/port.hh" +#include "mem/tport.hh" #include "sim/eventq.hh" #include <map> #include <string> @@ -47,7 +47,7 @@ // class PhysicalMemory : public MemObject { - class MemoryPort : public Port + class MemoryPort : public SimpleTimingPort { PhysicalMemory *memory; @@ -74,16 +74,6 @@ class PhysicalMemory : public MemObject int numPorts; - struct MemResponseEvent : public Event - { - Packet *pkt; - MemoryPort *memoryPort; - - MemResponseEvent(Packet *pkt, MemoryPort *memoryPort); - void process(); - const char *description(); - }; - private: // prevent copying of a MainMemory object PhysicalMemory(const PhysicalMemory &specmem); @@ -110,13 +100,10 @@ class PhysicalMemory : public MemObject void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); virtual Port *getPort(const std::string &if_name, int idx = -1); void virtual init(); + unsigned int drain(Event *de); - // fast back-door memory access for vtophys(), remote gdb, etc. - // uint64_t phys_read_qword(Addr addr) const; private: - bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort); - Tick doAtomicAccess(Packet *pkt); - void doFunctionalAccess(Packet *pkt); + Tick doFunctionalAccess(Packet *pkt); void recvStatusChange(Port::Status status); diff --git a/src/mem/tport.cc b/src/mem/tport.cc new file mode 100644 index 000000000..90cf68f02 --- /dev/null +++ b/src/mem/tport.cc @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include "mem/tport.hh" + +void +SimpleTimingPort::recvRetry() +{ + bool result = true; + while (result && transmitList.size()) { + result = Port::sendTiming(transmitList.front()); + if (result) + transmitList.pop_front(); + } + if (transmitList.size() == 0 && drainEvent) { + drainEvent->process(); + drainEvent = NULL; + } +} + +void +SimpleTimingPort::SendEvent::process() +{ + port->outTiming--; + assert(port->outTiming >= 0); + if (port->Port::sendTiming(packet)) + if (port->transmitList.size() == 0 && port->drainEvent) { + port->drainEvent->process(); + port->drainEvent = NULL; + } + return; + + port->transmitList.push_back(packet); +} + +void +SimpleTimingPort::resendNacked(Packet *pkt) { + pkt->reinitNacked(); + if (transmitList.size()) { + transmitList.push_front(pkt); + } else { + if (!Port::sendTiming(pkt)) + transmitList.push_front(pkt); + } +}; + + +unsigned int +SimpleTimingPort::drain(Event *de) +{ + if (outTiming == 0 && transmitList.size() == 0) + return 0; + drainEvent = de; + return 1; +} diff --git a/src/mem/tport.hh b/src/mem/tport.hh new file mode 100644 index 000000000..5473e945e --- /dev/null +++ b/src/mem/tport.hh @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +/** + * @file + * Implement a port which adds simple support of a sendTiming() function that + * takes a delay. In this way the * device can immediatly call + * sendTiming(pkt, time) after processing a request and the request will be + * handled by the port even if the port bus the device connects to is blocked. + */ + +/** recvTiming and drain should be implemented something like this when this + * class is used. + +bool +PioPort::recvTiming(Packet *pkt) +{ + if (pkt->result == Packet::Nacked) { + resendNacked(pkt); + } else { + Tick latency = device->recvAtomic(pkt); + // turn packet around to go back to requester + pkt->makeTimingResponse(); + sendTiming(pkt, latency); + } + return true; +} + +PioDevice::drain(Event *de) +{ + unsigned int count; + count = SimpleTimingPort->drain(de); + if (count) + changeState(Draining); + else + changeState(Drained); + return count; +} +*/ + +#ifndef __MEM_TPORT_HH__ +#define __MEM_TPORT_HH__ + +#include "mem/port.hh" +#include "sim/eventq.hh" +#include <list> +#include <string> + +class SimpleTimingPort : public Port +{ + protected: + /** A list of outgoing timing response packets that haven't been serviced + * yet. */ + std::list<Packet*> transmitList; + /** + * This class is used to implemented sendTiming() with a delay. When a delay + * is requested a new event is created. When the event time expires it + * attempts to send the packet. If it cannot, the packet is pushed onto the + * transmit list to be sent when recvRetry() is called. */ + class SendEvent : public Event + { + SimpleTimingPort *port; + Packet *packet; + + SendEvent(SimpleTimingPort *p, Packet *pkt, Tick t) + : Event(&mainEventQueue), port(p), packet(pkt) + { setFlags(AutoDelete); schedule(curTick + t); } + + virtual void process(); + + virtual const char *description() + { return "Future scheduled sendTiming event"; } + + friend class SimpleTimingPort; + }; + + + /** Number of timing requests that are emulating the device timing before + * attempting to end up on the bus. + */ + int outTiming; + + /** If we need to drain, keep the drain event around until we're done + * here.*/ + Event *drainEvent; + + /** Schedule a sendTiming() event to be called in the future. */ + void sendTiming(Packet *pkt, Tick time) + { outTiming++; new SimpleTimingPort::SendEvent(this, pkt, time); } + + /** This function is notification that the device should attempt to send a + * packet again. */ + virtual void recvRetry(); + + void resendNacked(Packet *pkt); + public: + + SimpleTimingPort(std::string pname) + : Port(pname), outTiming(0), drainEvent(NULL) + {} + + unsigned int drain(Event *de); + + friend class SimpleTimingPort::SendEvent; +}; + +#endif // __MEM_TPORT_HH__ diff --git a/src/python/m5/config.py b/src/python/m5/config.py index 8eed28dcc..df4b74cbd 100644 --- a/src/python/m5/config.py +++ b/src/python/m5/config.py @@ -665,7 +665,8 @@ class BaseProxy(object): result, done = self.find(obj) if not done: - raise AttributeError, "Can't resolve proxy '%s' from '%s'" % \ + raise AttributeError, \ + "Can't resolve proxy '%s' from '%s'" % \ (self.path(), base.path()) if isinstance(result, BaseProxy): diff --git a/src/python/m5/main.py b/src/python/m5/main.py index afe73d94c..a757aaf1a 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -249,6 +249,8 @@ def main(): # check to make sure we can find the listed script if not arguments or not os.path.isfile(arguments[0]): + if arguments and not os.path.isfile(arguments[0]): + print "Script %s not found" % arguments[0] usage(2) # tell C++ about output directory diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index 222f750da..f72c8e73f 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -12,7 +12,7 @@ class BasicPioDevice(PioDevice): type = 'BasicPioDevice' abstract = True pio_addr = Param.Addr("Device Address") - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") class DmaDevice(PioDevice): type = 'DmaDevice' diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py index 70d8b2e45..a98b35a4f 100644 --- a/src/python/m5/objects/DiskImage.py +++ b/src/python/m5/objects/DiskImage.py @@ -10,6 +10,6 @@ class RawDiskImage(DiskImage): class CowDiskImage(DiskImage): type = 'CowDiskImage' - child = Param.DiskImage("child image") + child = Param.DiskImage(RawDiskImage(read_only=True), + "child image") table_size = Param.Int(65536, "initial table size") - image_file = '' diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py index 418670592..db7efe004 100644 --- a/src/python/m5/objects/Ethernet.py +++ b/src/python/m5/objects/Ethernet.py @@ -1,7 +1,7 @@ from m5 import build_env from m5.config import * from Device import DmaDevice -from Pci import PciDevice +from Pci import PciDevice, PciConfigData class EtherInt(SimObject): type = 'EtherInt' @@ -84,6 +84,26 @@ class EtherDevBase(PciDevice): tx_thread = Param.Bool(False, "dedicated kernel threads for receive") rss = Param.Bool(False, "Receive Side Scaling") +class NSGigEPciData(PciConfigData): + VendorID = 0x100B + DeviceID = 0x0022 + Status = 0x0290 + SubClassCode = 0x00 + ClassCode = 0x02 + ProgIF = 0x00 + BAR0 = 0x00000001 + BAR1 = 0x00000000 + BAR2 = 0x00000000 + BAR3 = 0x00000000 + BAR4 = 0x00000000 + BAR5 = 0x00000000 + MaximumLatency = 0x34 + MinimumGrant = 0xb0 + InterruptLine = 0x1e + InterruptPin = 0x01 + BAR0Size = '256B' + BAR1Size = '4kB' + class NSGigE(EtherDevBase): type = 'NSGigE' @@ -91,11 +111,32 @@ class NSGigE(EtherDevBase): dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") + configdata = NSGigEPciData() + class NSGigEInt(EtherInt): type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") +class SinicPciData(PciConfigData): + VendorID = 0x1291 + DeviceID = 0x1293 + Status = 0x0290 + SubClassCode = 0x00 + ClassCode = 0x02 + ProgIF = 0x00 + BAR0 = 0x00000000 + BAR1 = 0x00000000 + BAR2 = 0x00000000 + BAR3 = 0x00000000 + BAR4 = 0x00000000 + BAR5 = 0x00000000 + MaximumLatency = 0x34 + MinimumGrant = 0xb0 + InterruptLine = 0x1e + InterruptPin = 0x01 + BAR0Size = '64kB' + class Sinic(EtherDevBase): type = 'Sinic' @@ -111,6 +152,8 @@ class Sinic(EtherDevBase): delay_copy = Param.Bool(False, "Delayed copy transmit") virtual_addr = Param.Bool(False, "Virtual addressing") + configdata = SinicPciData() + class SinicInt(EtherInt): type = 'SinicInt' device = Param.Sinic("Ethernet device of this interface") diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py index 9ee578177..a5fe1b595 100644 --- a/src/python/m5/objects/Ide.py +++ b/src/python/m5/objects/Ide.py @@ -1,8 +1,31 @@ from m5.config import * -from Pci import PciDevice +from Pci import PciDevice, PciConfigData class IdeID(Enum): vals = ['master', 'slave'] +class IdeControllerPciData(PciConfigData): + VendorID = 0x8086 + DeviceID = 0x7111 + Command = 0x0 + Status = 0x280 + Revision = 0x0 + ClassCode = 0x01 + SubClassCode = 0x01 + ProgIF = 0x85 + BAR0 = 0x00000001 + BAR1 = 0x00000001 + BAR2 = 0x00000001 + BAR3 = 0x00000001 + BAR4 = 0x00000001 + BAR5 = 0x00000001 + InterruptLine = 0x1f + InterruptPin = 0x01 + BAR0Size = '8B' + BAR1Size = '4B' + BAR2Size = '8B' + BAR3Size = '4B' + BAR4Size = '16B' + class IdeDisk(SimObject): type = 'IdeDisk' delay = Param.Latency('1us', "Fixed disk delay in microseconds") @@ -12,3 +35,5 @@ class IdeDisk(SimObject): class IdeController(PciDevice): type = 'IdeController' disks = VectorParam.IdeDisk("IDE disks attached to this controller") + + configdata =IdeControllerPciData() diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py index 29014bb37..cc0d1cf4a 100644 --- a/src/python/m5/objects/Pci.py +++ b/src/python/m5/objects/Pci.py @@ -52,7 +52,7 @@ class PciDevice(DmaDevice): pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") pci_func = Param.Int("PCI function code") - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") configdata = Param.PciConfigData(Parent.any, "PCI Config data") class PciFake(PciDevice): diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index 373475a7a..33dd22620 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -7,7 +7,7 @@ from Debug import Debug class Root(SimObject): type = 'Root' - clock = Param.RootClock('200MHz', "tick frequency") + clock = Param.RootClock('1THz', "tick frequency") max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)") progress_interval = Param.Tick('0', "print a progress message every n ticks (0 = never)") diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 4613571d8..0b5ff9e7d 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -1,11 +1,10 @@ from m5.config import * from Device import BasicPioDevice from Platform import Platform - -class Tsunami(Platform): - type = 'Tsunami' -# pciconfig = Param.PciConfigAll("PCI configuration") - system = Param.System(Parent.any, "system") +from AlphaConsole import AlphaConsole +from Uart import Uart8250 +from Pci import PciConfigAll +from BadDevice import BadDevice class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' @@ -25,3 +24,71 @@ class TsunamiIO(BasicPioDevice): class TsunamiPChip(BasicPioDevice): type = 'TsunamiPChip' tsunami = Param.Tsunami(Parent.any, "Tsunami") + +class Tsunami(Platform): + type = 'Tsunami' + system = Param.System(Parent.any, "system") + + cchip = TsunamiCChip(pio_addr=0x801a0000000) + pchip = TsunamiPChip(pio_addr=0x80180000000) + pciconfig = PciConfigAll() + fake_sm_chip = IsaFake(pio_addr=0x801fc000370) + + fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) + fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) + fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) + fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) + + fake_ppc = IsaFake(pio_addr=0x801fc0003bc) + + fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) + + fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) + fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) + fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) + fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) + fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) + fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) + fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) + fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) + fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) + fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) + + fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) + fake_ata1 = IsaFake(pio_addr=0x801fc000170) + + fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') + io = TsunamiIO(pio_addr=0x801fc000000) + uart = Uart8250(pio_addr=0x801fc0003f8) + console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk) + + # Attach I/O devices to specified bus object. Can't do this + # earlier, since the bus object itself is typically defined at the + # System level. + def attachIO(self, bus): + self.cchip.pio = bus.port + self.pchip.pio = bus.port + self.pciconfig.pio = bus.default + self.fake_sm_chip.pio = bus.port + self.fake_uart1.pio = bus.port + self.fake_uart2.pio = bus.port + self.fake_uart3.pio = bus.port + self.fake_uart4.pio = bus.port + self.fake_ppc.pio = bus.port + self.fake_OROM.pio = bus.port + self.fake_pnp_addr.pio = bus.port + self.fake_pnp_write.pio = bus.port + self.fake_pnp_read0.pio = bus.port + self.fake_pnp_read1.pio = bus.port + self.fake_pnp_read2.pio = bus.port + self.fake_pnp_read3.pio = bus.port + self.fake_pnp_read4.pio = bus.port + self.fake_pnp_read5.pio = bus.port + self.fake_pnp_read6.pio = bus.port + self.fake_pnp_read7.pio = bus.port + self.fake_ata0.pio = bus.port + self.fake_ata1.pio = bus.port + self.fb.pio = bus.port + self.io.pio = bus.port + self.uart.pio = bus.port + self.console.pio = bus.port diff --git a/src/sim/main.cc b/src/sim/main.cc index d0725ab37..4ea8c4138 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -215,7 +215,7 @@ loadIniFile(PyObject *_resolveFunc) configStream = simout.find("config.out"); // The configuration database is now complete; start processing it. - inifile.load("config.ini"); + inifile.load(simout.resolve("config.ini")); // Initialize statistics database Stats::InitSimStats(); diff --git a/tests/SConscript b/tests/SConscript new file mode 100644 index 000000000..5eadce6d4 --- /dev/null +++ b/tests/SConscript @@ -0,0 +1,244 @@ +# -*- mode:python -*- + +# Copyright (c) 2004-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import os +import sys +import glob +from SCons.Script.SConscript import SConsEnvironment + +Import('env') + +env['DIFFOUT'] = File('diff-out') + +# Dict that accumulates lists of tests by category (quick, medium, long) +env.Tests = {} + +def contents(node): + return file(str(node)).read() + +def check_test(target, source, env): + """Check output from running test. + + Targets are as follows: + target[0] : outdiff + target[1] : statsdiff + target[2] : status + + """ + # make sure target files are all gone + for t in target: + if os.path.exists(t.abspath): + Execute(Delete(t.abspath)) + # Run diff on output & ref directories to find differences. + # Exclude m5stats.txt since we will use diff-out on that. + Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + + '-I "^command line:" ' + # for stdout file + '-I "^M5 compiled on" ' + # for stderr file + '-I "^M5 simulation started" ' + # for stderr file + '-I "^Simulation complete at" ' + # for stderr file + '-I "^Listening for" ' + # for stderr file + '--exclude=m5stats.txt --exclude=SCCS ' + + '--exclude=${TARGETS[0].file} ' + + '> ${TARGETS[0]}', target=target, source=source), None) + print "===== Output differences =====" + print contents(target[0]) + # Run diff-out on m5stats.txt file + status = Execute(env.subst('$DIFFOUT $SOURCES > ${TARGETS[1]}', + target=target, source=source), + strfunction=None) + print "===== Statistics differences =====" + print contents(target[1]) + # Generate status file contents based on exit status of diff-out + if status == 0: + status_str = "passed." + else: + status_str = "FAILED!" + f = file(str(target[2]), 'w') + print >>f, env.subst('${TARGETS[2].dir}', target=target, source=source), \ + status_str + f.close() + # done + return 0 + +def check_test_string(target, source, env): + return env.subst("Comparing outputs in ${TARGETS[0].dir}.", + target=target, source=source) + +testAction = env.Action(check_test, check_test_string) + +def print_test(target, source, env): + print '***** ' + contents(source[0]) + return 0 + +printAction = env.Action(print_test, strfunction = None) + +def update_test(target, source, env): + """Update reference test outputs. + + Target is phony. First two sources are the ref & new m5stats.txt + files, respectively. We actually copy everything in the + respective directories except the status & diff output files. + + """ + dest_dir = str(source[0].get_dir()) + src_dir = str(source[1].get_dir()) + dest_files = os.listdir(dest_dir) + src_files = os.listdir(src_dir) + # Exclude status & diff outputs + for f in ('outdiff', 'statsdiff', 'status'): + if f in src_files: + src_files.remove(f) + for f in src_files: + if f in dest_files: + print " Replacing file", f + dest_files.remove(f) + else: + print " Creating new file", f + copyAction = Copy(os.path.join(dest_dir, f), os.path.join(src_dir, f)) + copyAction.strfunction = None + Execute(copyAction) + # warn about any files in dest not overwritten (other than SCCS dir) + if 'SCCS' in dest_files: + dest_files.remove('SCCS') + if dest_files: + print "Warning: file(s) in", dest_dir, "not updated:", + print ', '.join(dest_files) + return 0 + +def update_test_string(target, source, env): + return env.subst("Updating ${SOURCES[0].dir} from ${SOURCES[1].dir}", + target=target, source=source) + +updateAction = env.Action(update_test, update_test_string) + +def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=15): + """Define a test. + + Args: + category -- string describing test category (e.g., 'quick') + cpu_list -- list of CPUs to runs this test on (blank means all compiled CPUs) + os_list -- list of OSs to run this test on + refdir -- subdirectory containing reference output (default 'ref') + timeout -- test timeout in minutes (only enforced on pool) + + """ + + default_refdir = False + if refdir == 'ref': + default_refdir = True + if len(cpu_list) == 0: + cpu_list = env['CPU_MODELS'] +# if len(os_list) == 0: +# raise RuntimeError, "No OS specified" +# else: +# for test_os in os_list: +# build_cpu_test(env, category, test_os, cpu_list, refdir, timeout) + # Loop through CPU models and generate proper options, ref directories for each + for cpu in cpu_list: + test_os = '' + if cpu == "AtomicSimpleCPU": + cpu_option = ('','atomic/') + elif cpu == "TimingSimpleCPU": + cpu_option = ('--timing','timing/') + elif cpu == "O3CPU": + cpu_option = ('--detailed','detailed/') + else: + raise TypeError, "Unknown CPU model specified" + + if default_refdir: + # Reference stats located in ref/arch/os/cpu or ref/arch/cpu if no OS specified + test_refdir = os.path.join(refdir, env['TARGET_ISA']) + if test_os != '': + test_refdir = os.path.join(test_refdir, test_os) + cpu_refdir = os.path.join(test_refdir, cpu_option[1]) + + ref_stats = os.path.join(cpu_refdir, 'm5stats.txt') + + # base command for running test + base_cmd = '${SOURCES[0]} -d $TARGET.dir ${SOURCES[1]}' + base_cmd = base_cmd + ' ' + cpu_option[0] + # stdout and stderr files + cmd_stdout = '${TARGETS[0]}' + cmd_stderr = '${TARGETS[1]}' + + stdout_string = cpu_option[1] + 'stdout' + stderr_string = cpu_option[1] + 'stderr' + m5stats_string = cpu_option[1] + 'm5stats.txt' + outdiff_string = cpu_option[1] + 'outdiff' + statsdiff_string = cpu_option[1] + 'statsdiff' + status_string = cpu_option[1] + 'status' + + # Prefix test run with batch job submission command if appropriate. + # Output redirection is also different for batch runs. + # Batch command also supports timeout arg (in seconds, not minutes). + if env['BATCH']: + cmd = [env['BATCH_CMD'], '-t', str(timeout * 60), + '-o', cmd_stdout, '-e', cmd_stderr, base_cmd] + else: + cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr] + + env.Command([stdout_string, stderr_string, m5stats_string], [env.M5Binary, 'run.py'], + ' '.join(cmd)) + + # order of targets is important... see check_test + env.Command([outdiff_string, statsdiff_string, status_string], + [ref_stats, m5stats_string], + testAction) + + # phony target to echo status + if env['update_ref']: + p = env.Command(cpu_option[1] + '_update', [ref_stats, m5stats_string, status_string], + updateAction) + else: + p = env.Command(cpu_option[1] + '_print', [status_string], printAction) + env.AlwaysBuild(p) + + env.Tests.setdefault(category, []) + env.Tests[category] += p + +# Make test_builder a "wrapper" function. See SCons wiki page at +# http://www.scons.org/cgi-bin/wiki/WrapperFunctions. +SConsEnvironment.Test = test_builder + +cwd = os.getcwd() +os.chdir(str(Dir('.').srcdir)) +scripts = glob.glob('*/SConscript') +os.chdir(cwd) + +for s in scripts: + SConscript(s, exports = 'env', duplicate = False) + +# Set up phony commands for various test categories +allTests = [] +for (key, val) in env.Tests.iteritems(): + env.Command(key, val, env.NoAction) + allTests += val + +# The 'all' target is redundant since just specifying the test +# directory name (e.g., ALPHA_SE/test/opt) has the same effect. +env.Command('all', allTests, env.NoAction) diff --git a/tests/diff-out b/tests/diff-out new file mode 100755 index 000000000..5ebe97dd7 --- /dev/null +++ b/tests/diff-out @@ -0,0 +1,409 @@ +#!/usr/bin/perl +# Copyright (c) 2001-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +# +# This script diffs two SimpleScalar statistics output files. +# + +use Getopt::Std; + +# +# -t thresh sets threshold for ignoring differences (in %) +# -p sorts differences by % chg (default is alphabetic) +# -f ignores fetch-loss statistics +# -d ignores all distributions +# + +getopts('dfn:pt:h'); + +if ($#ARGV < 1) +{ + print "\nError: need two file arguments (<reference> <new>).\n"; + print " Options: -d = Ignore distributions\n"; + print " -f = Ignore fetch-loss stats\n"; + print " -p = Sort errors by percentage\n"; + print " -h = Diff header info separately from stats\n"; + print " -n <num> = Print top <num> errors (default 20)\n"; + print " -t <num> = Error threshold in percent (default 1)\n\n"; + die -1; +} + +open(REF, "<$ARGV[0]") or die "Error: can't open $ARGV[0].\n"; +open(NEW, "<$ARGV[1]") or die "Error: can't open $ARGV[1].\n"; + + +# +# Things that really should be adjustable via the command line +# + +# Ignorable error (in percent) +$err_thresh = ($opt_t) ? $opt_t : 0; + +# Number of stats to print before omitting +$omit_count = ($opt_n) ? $opt_n : 20; + + +# +# First copy everything up to the simulation statistics to a pair of +# temporary files, stripping out date-related items, and do a plain +# diff. Any differences in the arguments are not necessarily an issue; +# any differences in the program output should be caught by the EIO +# mechanism if an EIO file is used. +# + +# copy_header takes input filehandle and output filename + +sub copy_header +{ + my ($inhandle, $outname) = @_; + + open(OUTPUT, ">$outname") or die "Error: can't open $outname.\n"; + + while (<$inhandle>) + { + # strip out lines that can vary + next if /^(command line:|M5 compiled on |M5 simulation started |M5 executing on )/; + last if /Begin Simulation Statistics/; + print OUTPUT; + } + close OUTPUT; +} + +if ($opt_h) { + + # Diff header separately from stats + + $refheader = "/tmp/smt-test.refheader.$$"; + $newheader = "/tmp/smt-test.newheader.$$"; + + copy_header(\*REF, $refheader); + copy_header(\*NEW, $newheader); + + print "\n===== Header and program output differences =====\n\n"; + + print `diff $refheader $newheader`; + + print "\n===== Statistics differences =====\n\n"; +} + +# +# Now parse statistics +# + +# +# This function takes an open filehandle and returns a reference to +# a hash containing all the statistics variables and their values. +# +sub parse_file +{ + $stathandle = shift; + + $in_dist = undef; + $hashref = { }; # initialize hash for values + + while (<$stathandle>) + { + next if /^\s*$/; # skip blank lines + next if /^\*\*Ignore/; # temporary, to make totaling scripts easy for ISCA 03 + last if /End Simulation Statistics/; + + s/ *#.*//; # strip comments + + if (/^Memory usage: (\d+) KBytes/) { + $stat = 'memory usage'; + $value = $1; + } + elsif ($in_dist) { + if ($in_dist =~ /^fetch_loss_counters/) { + if (/^fetch_loss_counters_\d+\.end/) { + # end line of distribution: clear $in_dist flag + $in_dist = undef; + next; + } + else { + next if $opt_f; + + ($stat, $value) = /^(\S+)\s+(.*)/; + } + } + else { + if (/(.*)\.end_dist/) { + # end line of distribution: clear $in_dist flag + $in_dist = undef; + next; + } + if ($opt_d) { + next; # bail out if we are ignoring dists... + } + elsif (/(.*)\.(min|max)_value/) { + # treat these like normal stats + ($stat, $value) = /^(\S+)\s+(.*)/; + } + else { + # this is ugly because labels in the distribution + # buckets don't start in column 0 and may include + # embedded spaces + ($stat, $value) = + /^\s*(\S+(?:.*\S)?)\s+(\d+)\s+\d+\.\d+%/; + $stat = $in_dist . '::' . $stat; + } + } + } + else { + if (/(.*)\.start_dist/) { + # start line of distribution: set $in_dist flag + # and save distribution name for future reference + $in_dist = $1; + $stat = $1; + $value = 0; + } + elsif (/^(fetch_loss_counters_\d+)\.start/) { + # treat fetch loss counters like distribution, sort of + $in_dist = $1; + $stat = $1; + $value = 0; + } + else { + ($stat, $value) = /^(\S+)\s+(.*)/; + } + } + + $$hashref{$stat} = $value; + } + + close($stathandle); + return $hashref; +} + + +# +# pct_diff($old, $new) returns percent difference from $old to $new. +# +sub pct_diff +{ + my ($old, $new) = @_; + return ($old == 0) ? (($new == 0) ? 0 : 9999) : 100 * ($new - $old) / $old; +} + + +# +# Statistics to ignore: these relate to simulator performance, not +# correctness, so don't fail on changes here. +# +%ignore = ( + 'host_seconds' => 1, + 'host_tick_rate' => 1, + 'host_inst_rate' => 1, + 'host_mem_usage' => 1 +); + +# +# List of key statistics (always displayed) +# ==> list stats here WITHOUT trailing thread ID +# +@key_stat_list = ( + 'COM:IPC', + 'ISSUE:MSIPC', + 'COM:count', + 'host_inst_rate', + 'sim_insts', + 'sim_ticks', + 'host_mem_usage' +); + +$key_stat_pattern = join('|', @key_stat_list); + +# initialize first statistics from each file + +$max_err_mag = 0; + +$refhash = parse_file(\*REF); +$newhash = parse_file(\*NEW); + +# The string sim-smt prints on a divide by zero +$divbyzero = '<err: divide by zero>'; + +foreach $stat (sort keys %$refhash) +{ + $refvalue = $$refhash{$stat}; + $newvalue = $$newhash{$stat}; + + if (!defined($newvalue)) { + # stat missing from new file + push @missing_stats, $stat; + next; + } + + if ($stat =~ /($key_stat_pattern)/o) { + # key statistics: always record & display changes in these + push @key_stats, [$stat, $refvalue, $newvalue]; + } + + if ($ignore{$stat} or $refvalue eq $newvalue) { + # stat is in "ignore" list, or hasn't changed + } + else { + if ($refvalue eq $divbyzero || $newvalue eq $divbyzero) { + # one or the other was a divide by zero: + # no point in trying to quantify error + print "$stat: $refvalue --> $newvalue\n"; + } + else { + $reldiff = pct_diff($refvalue, $newvalue); + $diffmag = abs($reldiff); + + if ($diffmag > $err_thresh) { + push @errs, + [$stat, $refvalue, $newvalue, $reldiff]; + } + + if ($diffmag > $max_err_mag) { + $max_err_mag = $diffmag; + } + } + } + + # remove from new hash so we can detect added stats + delete $$newhash{$stat}; +} + + +# +# All done. Print comparison summary. +# + +printf("Maximum error magnitude: %+f%%\n\n", $max_err_mag); + +printf(" %-30s %10s %10s %10s %7s\n", ' ', 'Reference', 'New Value', 'Abs Diff', 'Pct Chg'); + +printf("Key statistics:\n\n"); + +foreach $key_stat (@key_stats) +{ + ($statname, $refvalue, $newvalue, $reldiff) = @$key_stat; + + # deduce format from reference value + $pointpos = rindex($refvalue, '.'); + $digits = ($pointpos < 0) ? 0 :(length($refvalue) - $pointpos - 1); + $fmt = "%10.${digits}f"; + + # print differing values with absolute and relative error + printf(" %-30s $fmt $fmt $fmt %+7.2f%%\n", + $statname, $refvalue, $newvalue, + $newvalue - $refvalue, pct_diff($refvalue, $newvalue)); +} + +printf("\nLargest $omit_count relative errors (> %d%%):\n\n", $err_thresh); + +$num_errs = 0; + +if ($opt_p) +{ + # sort differences by percent change + @errs = sort { abs($$b[3]) <=> abs($$a[3]) } @errs; +} + +foreach $err (@errs) +{ + ($statname, $refvalue, $newvalue, $reldiff) = @$err; + + # deduce format from reference value + $pointpos1 = rindex($refvalue, '.'); + $digits1 = ($pointpos1 < 0) ? 0 :(length($refvalue) - $pointpos1 - 1); + $pointpos2 = rindex($newvalue, '.'); + $digits2 = ($pointpos2 < 0) ? 0 :(length($newvalue) - $pointpos2 - 1); + $digits = ($digits1 > $digits2) ? $digits1 : $digits2; + $fmt = "%10.${digits}f"; + + # print differing values with absolute and relative error + printf(" %-30s $fmt $fmt $fmt %+7.2f%%\n", + $statname, $refvalue, $newvalue, $newvalue - $refvalue, $reldiff); + + # only print top N errors + if (++$num_errs >= $omit_count) + { + print "[... additional errors omitted ...]\n"; + last; + } +} + +# +# Report missing stats, but first filter out distribution buckets: +# these are mostly noise + +@missing_stats = grep { !/::(\d+|overflows)?$/ } @missing_stats; + +# get count +$missing_stats = scalar(@missing_stats); + +if ($missing_stats) +{ + print "\nMissing $missing_stats reference statistics:\n\n"; + foreach $stat (@missing_stats) + { +# print "\t$stat\n"; + printf " %-50s ", $stat; + print "$$refhash{$stat}\n"; + } +} + +# +# Any stats left in newhash are added since the reference file +# + +@added_stats = keys %$newhash; + +# first filter out distribution buckets: mostly noise + +@added_stats = grep { !/::(\d+|overflows)?$/ } @added_stats; + +# get count +$added_stats = scalar(@added_stats); + +if ($added_stats) +{ + print "\nFound $added_stats new statistics:\n\n"; + foreach $stat (sort @added_stats) + { +# print "\t$stat\n"; + printf " %-50s ", $stat; + print "$$newhash{$stat}\n"; + } +} + +cleanup(); +# Exit code is 0 if no stats error, 1 otherwise +$status = ($max_err_mag == 0.0) ? 0 : 1; +exit $status; + +sub cleanup +{ + unlink($refheader) if ($refheader); + unlink($newheader) if ($newheader); +} diff --git a/tests/test1/ref/alpha/atomic/config.ini b/tests/test1/ref/alpha/atomic/config.ini new file mode 100644 index 000000000..9961fe389 --- /dev/null +++ b/tests/test1/ref/alpha/atomic/config.ini @@ -0,0 +1,95 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu0 physmem workload +mem_mode=atomic +physmem=system.physmem + +[system.cpu0] +type=AtomicSimpleCPU +children=mem +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu0.mem +simulate_stalls=false +system=system +width=1 +workload=system.workload + +[system.cpu0.mem] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[system.workload] +type=EioProcess +chkpt= +file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +output=cout +system=system + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/test1/ref/alpha/atomic/config.out b/tests/test1/ref/alpha/atomic/config.out new file mode 100644 index 000000000..a9c04ceff --- /dev/null +++ b/tests/test1/ref/alpha/atomic/config.out @@ -0,0 +1,90 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.workload] +type=EioProcess +file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +chkpt= +output=cout +system=system + +[system.cpu0.mem] +type=Bus +bus_id=0 + +[system.cpu0] +type=AtomicSimpleCPU +max_insts_any_thread=500000 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.cpu0.mem +system=system +workload=system.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/test1/ref/alpha/atomic/m5stats.txt b/tests/test1/ref/alpha/atomic/m5stats.txt new file mode 100644 index 000000000..09e94d639 --- /dev/null +++ b/tests/test1/ref/alpha/atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1301768 # Simulator instruction rate (inst/s) +host_mem_usage 147756 # Number of bytes of host memory used +host_seconds 0.38 # Real time elapsed on the host +host_tick_rate 1300060 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 499999 # Number of ticks simulated +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 500000 # number of cpu cycles simulated +system.cpu0.num_insts 500000 # Number of instructions executed +system.cpu0.num_refs 182204 # Number of memory references +system.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/test1/ref/alpha/atomic/stderr b/tests/test1/ref/alpha/atomic/stderr new file mode 100644 index 000000000..4e444fa6b --- /dev/null +++ b/tests/test1/ref/alpha/atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... + +gzip: stdout: Broken pipe diff --git a/tests/test1/ref/alpha/atomic/stdout b/tests/test1/ref/alpha/atomic/stdout new file mode 100644 index 000000000..78ab05bdd --- /dev/null +++ b/tests/test1/ref/alpha/atomic/stdout @@ -0,0 +1,14 @@ +main dictionary has 1245 entries +49508 bytes wasted +>M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 19 2006 15:49:01 +M5 started Wed Jul 19 15:49:10 2006 +M5 executing on zamp.eecs.umich.edu +Creating SE system +Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/test1/ref/alpha/detailed/config.ini b/tests/test1/ref/alpha/detailed/config.ini new file mode 100644 index 000000000..192833c8b --- /dev/null +++ b/tests/test1/ref/alpha/detailed/config.ini @@ -0,0 +1,298 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu0 physmem workload +mem_mode=atomic +physmem=system.physmem + +[system.cpu0] +type=DerivO3CPU +children=checker fuPool mem +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +checker=system.cpu0.checker +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu0.mem +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +wbDepth=1 +wbWidth=8 +workload=system.workload + +[system.cpu0.checker] +type=O3Checker +clock=1 +defer_registration=false +exitOnError=true +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +system=system +warnOnlyOnLoadError=false +workload=system.workload + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu0.fuPool.FUList0.opList0 + +[system.cpu0.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 + +[system.cpu0.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu0.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu0.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 + +[system.cpu0.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu0.fuPool.FUList4.opList0 + +[system.cpu0.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu0.fuPool.FUList5.opList0 + +[system.cpu0.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 + +[system.cpu0.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu0.fuPool.FUList7.opList0 + +[system.cpu0.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu0.mem] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[system.workload] +type=EioProcess +chkpt= +file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +output=cout +system=system + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/test1/ref/alpha/detailed/config.out b/tests/test1/ref/alpha/detailed/config.out new file mode 100644 index 000000000..07c092a2b --- /dev/null +++ b/tests/test1/ref/alpha/detailed/config.out @@ -0,0 +1,293 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.workload] +type=EioProcess +file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +chkpt= +output=cout +system=system + +[system.cpu0.mem] +type=Bus +bus_id=0 + +[system.cpu0.checker] +type=O3Checker +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +workload=system.workload +clock=1 +defer_registration=false +exitOnError=true +warnOnlyOnLoadError=false +function_trace=false +function_trace_start=0 + +[system.cpu0.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +opList=system.cpu0.fuPool.FUList0.opList0 +count=6 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 +count=2 + +[system.cpu0.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu0.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu0.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 +count=4 + +[system.cpu0.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu0.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 +count=2 + +[system.cpu0.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +opList=system.cpu0.fuPool.FUList4.opList0 +count=0 + +[system.cpu0.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu0.fuPool.FUList5] +type=FUDesc +opList=system.cpu0.fuPool.FUList5.opList0 +count=0 + +[system.cpu0.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu0.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu0.fuPool.FUList6] +type=FUDesc +opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 +count=4 + +[system.cpu0.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu0.fuPool.FUList7] +type=FUDesc +opList=system.cpu0.fuPool.FUList7.opList0 +count=1 + +[system.cpu0.fuPool] +type=FUPool +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 + +[system.cpu0] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.workload +mem=system.cpu0.mem +checker=system.cpu0.checker +max_insts_any_thread=500000 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu0.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=6 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/test1/ref/alpha/detailed/m5stats.txt b/tests/test1/ref/alpha/detailed/m5stats.txt new file mode 100644 index 000000000..8ff727085 --- /dev/null +++ b/tests/test1/ref/alpha/detailed/m5stats.txt @@ -0,0 +1,1775 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 45390 # Number of BTB hits +global.BPredUnit.BTBLookups 59902 # Number of BTB lookups +global.BPredUnit.RASInCorrect 85 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 3098 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 46029 # Number of conditional branches predicted +global.BPredUnit.lookups 70231 # Number of BP lookups +global.BPredUnit.usedRAS 7755 # Number of times the RAS was used to get a target. +host_inst_rate 69741 # Simulator instruction rate (inst/s) +host_mem_usage 148316 # Number of bytes of host memory used +host_seconds 7.17 # Real time elapsed on the host +host_tick_rate 36160 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15235 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 2693 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 145639 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 60928 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500002 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 259259 # Number of ticks simulated +system.cpu0.checker.numCycles 518940 # number of cpu cycles simulated +system.cpu0.commit.COM:branches 61160 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 17172 # number cycles where commit BW limit reached +system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle.samples 251997 +system.cpu0.commit.COM:committed_per_cycle.min_value 0 + 0 70509 2798.01% + 1 75489 2995.63% + 2 28876 1145.89% + 3 23224 921.60% + 4 21222 842.15% + 5 3198 126.91% + 6 8368 332.07% + 7 3939 156.31% + 8 17172 681.44% +system.cpu0.commit.COM:committed_per_cycle.max_value 8 +system.cpu0.commit.COM:committed_per_cycle.end_dist + +system.cpu0.commit.COM:count 518948 # Number of instructions committed +system.cpu0.commit.COM:loads 131376 # Number of loads committed +system.cpu0.commit.COM:membars 0 # Number of memory barriers committed +system.cpu0.commit.COM:refs 189772 # Number of memory references committed +system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.branchMispredicts 2836 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 518948 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 44297 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 500002 # Number of Instructions Simulated +system.cpu0.committedInsts_total 500002 # Number of Instructions Simulated +system.cpu0.cpi 0.518516 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.518516 # CPI: Total CPI of All Threads +system.cpu0.decode.DECODE:BlockedCycles 743 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 281 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 16033 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 586219 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 143055 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 108199 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 7263 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 989 # Number of squashed instructions handled by decode +system.cpu0.fetch.Branches 70231 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 71036 # Number of cache lines fetched +system.cpu0.fetch.Cycles 180480 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 962 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 594968 # Number of instructions fetch has processed +system.cpu0.fetch.SquashCycles 3140 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.270890 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 71036 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 53145 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 2.294870 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist.samples 259260 +system.cpu0.fetch.rateDist.min_value 0 + 0 149817 5778.64% + 1 3603 138.97% + 2 9058 349.38% + 3 10685 412.13% + 4 8455 326.12% + 5 18775 724.18% + 6 25664 989.89% + 7 6109 235.63% + 8 27094 1045.05% +system.cpu0.fetch.rateDist.max_value 8 +system.cpu0.fetch.rateDist.end_dist + +system.cpu0.iew.EXEC:branches 64672 # Number of branches executed +system.cpu0.iew.EXEC:insts 526242 # Number of executed instructions +system.cpu0.iew.EXEC:loads 140576 # Number of load instructions executed +system.cpu0.iew.EXEC:nop 19405 # number of nop insts executed +system.cpu0.iew.EXEC:rate 2.029785 # Inst execution rate +system.cpu0.iew.EXEC:refs 200121 # number of memory reference insts executed +system.cpu0.iew.EXEC:squashedInsts 5760 # Number of squashed instructions skipped in execute +system.cpu0.iew.EXEC:stores 59545 # Number of stores executed +system.cpu0.iew.EXEC:swp 0 # number of swp insts executed +system.cpu0.iew.WB:consumers 394903 # num instructions consuming a value +system.cpu0.iew.WB:count 523588 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.746115 # average fanout of values written-back +system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.iew.WB:producers 294643 # num instructions producing a value +system.cpu0.iew.WB:rate 2.019548 # insts written-back per cycle +system.cpu0.iew.WB:sent 524223 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 2948 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 145639 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 1523 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 60928 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 563297 # Number of instructions dispatched to IQ +system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 7263 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu0.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 18223 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 14246 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 2528 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 1750 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 1198 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 1.928581 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.928581 # IPC: Total IPC of All Threads +system.cpu0.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:(null).samples 0 +system.cpu0.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:(null).max_value 0 +system.cpu0.iq.IQ:residence:(null).end_dist + +system.cpu0.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:IntAlu.samples 0 +system.cpu0.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:IntAlu.max_value 0 +system.cpu0.iq.IQ:residence:IntAlu.end_dist + +system.cpu0.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:IntMult.samples 0 +system.cpu0.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:IntMult.max_value 0 +system.cpu0.iq.IQ:residence:IntMult.end_dist + +system.cpu0.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:IntDiv.samples 0 +system.cpu0.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:IntDiv.max_value 0 +system.cpu0.iq.IQ:residence:IntDiv.end_dist + +system.cpu0.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:FloatAdd.samples 0 +system.cpu0.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu0.iq.IQ:residence:FloatAdd.end_dist + +system.cpu0.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:FloatCmp.samples 0 +system.cpu0.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu0.iq.IQ:residence:FloatCmp.end_dist + +system.cpu0.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:FloatCvt.samples 0 +system.cpu0.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu0.iq.IQ:residence:FloatCvt.end_dist + +system.cpu0.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:FloatMult.samples 0 +system.cpu0.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:FloatMult.max_value 0 +system.cpu0.iq.IQ:residence:FloatMult.end_dist + +system.cpu0.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:FloatDiv.samples 0 +system.cpu0.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu0.iq.IQ:residence:FloatDiv.end_dist + +system.cpu0.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu0.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu0.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu0.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:MemRead.samples 0 +system.cpu0.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:MemRead.max_value 0 +system.cpu0.iq.IQ:residence:MemRead.end_dist + +system.cpu0.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:MemWrite.samples 0 +system.cpu0.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:MemWrite.max_value 0 +system.cpu0.iq.IQ:residence:MemWrite.end_dist + +system.cpu0.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:IprAccess.samples 0 +system.cpu0.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:IprAccess.max_value 0 +system.cpu0.iq.IQ:residence:IprAccess.end_dist + +system.cpu0.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu0.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu0.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu0.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu0.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:(null)_delay.samples 0 +system.cpu0.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:(null)_delay.max_value 0 +system.cpu0.iq.ISSUE:(null)_delay.end_dist + +system.cpu0.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu0.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu0.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu0.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:IntMult_delay.samples 0 +system.cpu0.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu0.iq.ISSUE:IntMult_delay.end_dist + +system.cpu0.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu0.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu0.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu0.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu0.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu0.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu0.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu0.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu0.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu0.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu0.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu0.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu0.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu0.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu0.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu0.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu0.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu0.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu0.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu0.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu0.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu0.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:MemRead_delay.samples 0 +system.cpu0.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu0.iq.ISSUE:MemRead_delay.end_dist + +system.cpu0.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu0.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu0.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu0.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu0.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu0.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu0.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu0.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu0.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu0.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu0.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu0.iq.ISSUE:FU_type_0 532005 # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.start_dist + (null) 0 0.00% # Type of FU issued + IntAlu 329259 61.89% # Type of FU issued + IntMult 10 0.00% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 13 0.00% # Type of FU issued + FloatCmp 3 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 2 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 142868 26.85% # Type of FU issued + MemWrite 59850 11.25% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0.end_dist +system.cpu0.iq.ISSUE:fu_busy_cnt 5510 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.010357 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1663 30.18% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 2693 48.87% # attempts to use FU when none available + MemWrite 1154 20.94% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full.end_dist +system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle.samples 259260 +system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 + 0 59185 2282.84% + 1 72964 2814.32% + 2 38364 1479.75% + 3 33144 1278.41% + 4 19818 764.41% + 5 14624 564.07% + 6 18233 703.27% + 7 2333 89.99% + 8 595 22.95% +system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu0.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu0.iq.ISSUE:rate 2.052013 # Inst issue rate +system.cpu0.iq.iqInstsAdded 543865 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 532005 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 42716 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 611 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 21818 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.numCycles 259260 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 191 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IdleCycles 144885 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 336 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:RenameLookups 753146 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 577319 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 432146 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 106374 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 7263 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 302 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 46034 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 245 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 34 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 421 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 32 # count of temporary serializing insts renamed +system.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/test1/ref/alpha/detailed/stderr b/tests/test1/ref/alpha/detailed/stderr new file mode 100644 index 000000000..2b973e482 --- /dev/null +++ b/tests/test1/ref/alpha/detailed/stderr @@ -0,0 +1,4 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (1) detected @ PC 0x000000 + +gzip: stdout: Broken pipe diff --git a/tests/test1/ref/alpha/detailed/stdout b/tests/test1/ref/alpha/detailed/stdout new file mode 100644 index 000000000..2c46aa4f2 --- /dev/null +++ b/tests/test1/ref/alpha/detailed/stdout @@ -0,0 +1,14 @@ +main dictionary has 1245 entries +49508 bytes wasted +>M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 19 2006 15:49:01 +M5 started Wed Jul 19 15:49:12 2006 +M5 executing on zamp.eecs.umich.edu +Creating SE system +Exiting @ tick 259259 because a thread reached the max instruction count diff --git a/tests/test1/ref/alpha/timing/config.ini b/tests/test1/ref/alpha/timing/config.ini new file mode 100644 index 000000000..58dc6741b --- /dev/null +++ b/tests/test1/ref/alpha/timing/config.ini @@ -0,0 +1,93 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu0 physmem workload +mem_mode=atomic +physmem=system.physmem + +[system.cpu0] +type=TimingSimpleCPU +children=mem +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=500000 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu0.mem +system=system +workload=system.workload + +[system.cpu0.mem] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[system.workload] +type=EioProcess +chkpt= +file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +output=cout +system=system + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/test1/ref/alpha/timing/config.out b/tests/test1/ref/alpha/timing/config.out new file mode 100644 index 000000000..b28de6f74 --- /dev/null +++ b/tests/test1/ref/alpha/timing/config.out @@ -0,0 +1,90 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.workload] +type=EioProcess +file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +chkpt= +output=cout +system=system + +[system.cpu0.mem] +type=Bus +bus_id=0 + +[system.cpu0] +type=TimingSimpleCPU +max_insts_any_thread=500000 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.cpu0.mem +system=system +workload=system.workload +clock=1 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/test1/ref/alpha/timing/m5stats.txt b/tests/test1/ref/alpha/timing/m5stats.txt new file mode 100644 index 000000000..64d05099f --- /dev/null +++ b/tests/test1/ref/alpha/timing/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 739858 # Simulator instruction rate (inst/s) +host_mem_usage 147760 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 1006609 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 500000 # Number of instructions simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 680774 # Number of ticks simulated +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.numCycles 0 # number of cpu cycles simulated +system.cpu0.num_insts 500000 # Number of instructions executed +system.cpu0.num_refs 182203 # Number of memory references +system.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/test1/ref/alpha/timing/stderr b/tests/test1/ref/alpha/timing/stderr new file mode 100644 index 000000000..4e444fa6b --- /dev/null +++ b/tests/test1/ref/alpha/timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... + +gzip: stdout: Broken pipe diff --git a/tests/test1/ref/alpha/timing/stdout b/tests/test1/ref/alpha/timing/stdout new file mode 100644 index 000000000..980af1477 --- /dev/null +++ b/tests/test1/ref/alpha/timing/stdout @@ -0,0 +1,14 @@ +main dictionary has 1245 entries +49508 bytes wasted +>M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 19 2006 15:49:01 +M5 started Wed Jul 19 15:49:19 2006 +M5 executing on zamp.eecs.umich.edu +Creating SE system +Exiting @ tick 680774 because a thread reached the max instruction count |