diff options
| -rw-r--r-- | RELEASE_NOTES | 16 | ||||
| -rw-r--r-- | SConstruct | 2 | ||||
| -rw-r--r-- | configs/common/Simulation.py | 3 | ||||
| -rw-r--r-- | src/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 6 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 8 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 2 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 6 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 10 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 10 | ||||
| -rw-r--r-- | src/cpu/thread_context.hh | 4 | ||||
| -rw-r--r-- | src/cpu/thread_state.cc | 16 | ||||
| -rw-r--r-- | src/cpu/thread_state.hh | 6 | ||||
| -rw-r--r-- | src/mem/bus.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 19 | ||||
| -rw-r--r-- | src/mem/cache/coherence/simple_coherence.hh | 4 | ||||
| -rw-r--r-- | src/mem/cache/coherence/uni_coherence.cc | 33 | ||||
| -rw-r--r-- | src/mem/cache/coherence/uni_coherence.hh | 2 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt | 37 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt | 35 | ||||
| -rw-r--r-- | tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt | 60 | ||||
| -rw-r--r-- | util/m5/m5op.S | 4 |
22 files changed, 186 insertions, 100 deletions
diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 39086de89..03eec3aab 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,3 +1,19 @@ +Nov. 28, 2006: m5_2.0_beta2 +-------------------- +Bug fixes since beta 1: +1. Many cache issues resolved +2. Uni-coherence fixes in full-system +3. LL/SC Support +4. Draining/Switchover +5. Functional Accesses +6. Bus now has real timing +7. Single config file fro all SpecCPU2000 benchmarks +8. Several other minor bug fixes and enhancements + +Outstading issues for 2.0 release: +1. Simulator performance fixes for memory system/caches +2. Multiprocessor linux boot using the detailed O3 CPU model + Aug. 25, 2006: m5_2.0_beta patch 1 -------------------- Handful of minor bug fixes for m5_2.0_beta, diff --git a/SConstruct b/SConstruct index d8851f091..50ca2d6e4 100644 --- a/SConstruct +++ b/SConstruct @@ -344,7 +344,7 @@ sticky_opts.AddOptions( # values (more than one value) not to be able to be restored from # a saved option file. If this causes trouble then upgrade to # scons 0.96.90 or later. - ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU', + ListOption('CPU_MODELS', 'CPU models', 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU', env['ALL_CPU_LIST']), BoolOption('ALPHA_TLASER', 'Model Alpha TurboLaser platform (vs. Tsunami)', False), diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 374ff3fc2..e037d0343 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -39,6 +39,9 @@ def setCPUClass(options): if options.timing: TmpClass = TimingSimpleCPU elif options.detailed: + if not options.caches: + print "O3 CPU must be used with caches" + sys.exit(1) TmpClass = DerivO3CPU else: TmpClass = AtomicSimpleCPU diff --git a/src/SConscript b/src/SConscript index 9d54174ab..429e1bee1 100644 --- a/src/SConscript +++ b/src/SConscript @@ -333,6 +333,7 @@ makeEnv('fast', '.fo', strip = True, # Profiled binary makeEnv('prof', '.po', CCFLAGS = Split('-O3 -g -pg'), + CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'], LINKFLAGS = '-pg') Return('envList') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 7014d4c22..6df47ef7a 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -795,6 +795,12 @@ decode OPCODE default Unknown::unknown() { 0x04: quiesceTime({{ R0 = AlphaPseudo::quiesceTime(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); + 0x10: ivlb({{ + warn_once("Obsolete M5 instruction ivlb encountered.\n"); + }}); + 0x11: ivle({{ + warn_once("Obsolete M5 instruction ivlb encountered.\n"); + }}); 0x20: m5exit_old({{ AlphaPseudo::m5exit_old(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 3dc353a9f..a5a00015f 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -497,8 +497,6 @@ FullO3CPU<Impl>::init() } #if FULL_SYSTEM - src_tc->init(); - TheISA::initCPU(src_tc, src_tc->readCpuId()); #endif } @@ -554,6 +552,12 @@ template <class Impl> void FullO3CPU<Impl>::activateContext(int tid, int delay) { +#if FULL_SYSTEM + // Connect the ThreadContext's memory ports (Functional/Virtual + // Ports) + threadContexts[tid]->connectMemPorts(); +#endif + // Needs to set each stage to running as well. if (delay){ DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 031f36480..390569c3d 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -92,7 +92,7 @@ class O3ThreadContext : public ThreadContext void delVirtPort(VirtualPort *vp); - virtual void init() { thread->init(); } + virtual void connectMemPorts() { thread->connectMemPorts(); } #else virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 0180756e3..afebf294f 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -101,8 +101,10 @@ template <class Impl> void O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp) { - delete vp->getPeer(); - delete vp; + if (vp != thread->getVirtPort()) { + delete vp->getPeer(); + delete vp; + } } #endif diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index b7699c405..67611e815 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -78,9 +78,6 @@ AtomicSimpleCPU::init() for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; - // initialize the mem pointers - tc->init(); - // initialize CPU, including PC TheISA::initCPU(tc, tc->readCpuId()); } @@ -241,6 +238,13 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) assert(!tickEvent.scheduled()); notIdleFraction++; + +#if FULL_SYSTEM + // Connect the ThreadContext's memory ports (Functional/Virtual + // Ports) + tc->connectMemPorts(); +#endif + //Make sure ticks are still on multiples of cycles tickEvent.schedule(nextCycle(curTick + cycles(delay))); _status = Running; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index aa23a00e8..dfffb0b1f 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -59,9 +59,6 @@ TimingSimpleCPU::init() for (int i = 0; i < threadContexts.size(); ++i) { ThreadContext *tc = threadContexts[i]; - // initialize the mem pointers - tc->init(); - // initialize CPU, including PC TheISA::initCPU(tc, tc->readCpuId()); } @@ -241,6 +238,13 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) notIdleFraction++; _status = Running; + +#if FULL_SYSTEM + // Connect the ThreadContext's memory ports (Functional/Virtual + // Ports) + tc->connectMemPorts(); +#endif + // kick things off by initiating the fetch of the next instruction fetchEvent = new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index baeb7a8be..bb9cc9e16 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -134,7 +134,7 @@ class ThreadContext virtual void delVirtPort(VirtualPort *vp) = 0; - virtual void init() = 0; + virtual void connectMemPorts() = 0; #else virtual TranslatingPort *getMemPort() = 0; @@ -308,7 +308,7 @@ class ProxyThreadContext : public ThreadContext void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } - void init() {actualTC->init(); } + void connectMemPorts() { actualTC->connectMemPorts(); } #else TranslatingPort *getMemPort() { return actualTC->getMemPort(); } diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index 9cac4fd26..93dd1e2eb 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -113,23 +113,29 @@ ThreadState::unserialize(Checkpoint *cp, const std::string §ion) #if FULL_SYSTEM void -ThreadState::init() +ThreadState::connectMemPorts() { - initPhysPort(); - initVirtPort(); + connectPhysPort(); + connectVirtPort(); } void -ThreadState::initPhysPort() +ThreadState::connectPhysPort() { + // @todo: For now this disregards any older port that may have + // already existed. Fix this memory leak once the bus port IDs + // for functional ports is resolved. physPort = new FunctionalPort(csprintf("%s-%d-funcport", baseCpu->name(), tid)); connectToMemFunc(physPort); } void -ThreadState::initVirtPort() +ThreadState::connectVirtPort() { + // @todo: For now this disregards any older port that may have + // already existed. Fix this memory leak once the bus port IDs + // for functional ports is resolved. virtPort = new VirtualPort(csprintf("%s-%d-vport", baseCpu->name(), tid)); connectToMemFunc(virtPort); diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 1844be8b7..4f878db1f 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -91,11 +91,11 @@ struct ThreadState { Tick readLastSuspend() { return lastSuspend; } #if FULL_SYSTEM - void init(); + void connectMemPorts(); - void initPhysPort(); + void connectPhysPort(); - void initVirtPort(); + void connectVirtPort(); void dumpFuncProfile(); diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 6b5b63f50..e9a870b80 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -296,7 +296,7 @@ Bus::findPort(Addr addr, int id) // we shouldn't be sending this back to where it came from - // only on a functional access and then we should terminate + // do the snoop access and then we should terminate // the cyclical call. if (dest_id == id) return 0; diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index df59b0a4f..3a681bc52 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -391,7 +391,13 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt) } //Send a timing (true) invalidate up if the protocol calls for it - coherence->propogateInvalidate(pkt, true); + if (coherence->propogateInvalidate(pkt, true)) { + //Temp hack, we had a functional read hit in the L1, mark as success + pkt->flags |= SATISFIED; + pkt->result = Packet::Success; + respondToSnoop(pkt, curTick + hitLatency); + return; + } Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); @@ -562,6 +568,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update, PacketList writebacks; int lat; + BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update); DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), @@ -615,7 +622,8 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update, // Can't handle it, return request unsatisfied. panic("Atomic access ran into outstanding MSHR's or WB's!"); } - if (!pkt->req->isUncacheable()) { + if (!pkt->req->isUncacheable() /*Uncacheables just go through*/ + && (pkt->cmd != Packet::Writeback)/*Writebacks on miss fall through*/) { // Fetch the cache block to fill BlkType *blk = tags->findBlock(pkt); Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd, @@ -691,7 +699,12 @@ Tick Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt) { //Send a atomic (false) invalidate up if the protocol calls for it - coherence->propogateInvalidate(pkt, false); + if (coherence->propogateInvalidate(pkt, false)) { + //Temp hack, we had a functional read hit in the L1, mark as success + pkt->flags |= SATISFIED; + pkt->result = Packet::Success; + return hitLatency; + } Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh index 5316e64b9..a1fd33080 100644 --- a/src/mem/cache/coherence/simple_coherence.hh +++ b/src/mem/cache/coherence/simple_coherence.hh @@ -161,10 +161,10 @@ class SimpleCoherence bool hasProtocol() { return true; } - void propogateInvalidate(PacketPtr pkt, bool isTiming) + bool propogateInvalidate(PacketPtr pkt, bool isTiming) { //For now we do nothing, asssumes simple coherence is top level of cache - return; + return false; } }; diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index 19230e35b..ea615d70a 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -54,6 +54,7 @@ UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success) { bool unblock = cshrs.isFull(); // cshrs.markInService(cshr); + delete pkt->req; cshrs.deallocate(cshr); if (!cshrs.havePending()) { cache->clearSlaveRequest(Request_Coherence); @@ -81,17 +82,24 @@ UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, } else if (blk) { new_state = blk->status; + if (pkt->isRead()) { + DPRINTF(Cache, "Uni-coherence snoops a read that hit in itself" + ". Should satisfy the packet\n"); + return true; //Satisfy Reads if we can + } } return false; } -void +bool UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) { if (pkt->isInvalidate()) { +/* Temp Fix for now, forward all invalidates up as functional accesses */ if (isTiming) { // Forward to other caches - PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); + Request* req = new Request(pkt->req->getPaddr(), pkt->getSize(), 0); + PacketPtr tmp = new Packet(req, Packet::InvalidateReq, -1); cshrs.allocate(tmp); cache->setSlaveRequest(Request_Coherence, curTick); if (cshrs.isFull()) @@ -102,5 +110,26 @@ UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) cache->cpuSidePort->sendAtomic(tmp); delete tmp; } +/**/ +/* PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); + cache->cpuSidePort->sendFunctional(tmp); + delete tmp; +*/ + } + if (pkt->isRead()) { + /*For now we will see if someone above us has the data by + doing a functional access on reads. Fix this later */ + PacketPtr tmp = new Packet(pkt->req, Packet::ReadReq, -1); + tmp->allocate(); + cache->cpuSidePort->sendFunctional(tmp); + bool hit = (tmp->result == Packet::Success); + if (hit) { + memcpy(pkt->getPtr<uint8_t>(), tmp->getPtr<uint8_t>(), + pkt->getSize()); + DPRINTF(Cache, "Uni-coherence snoops a read that hit in L1\n"); + } + delete tmp; + return hit; } + return false; } diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh index 44c752088..9a4aacdec 100644 --- a/src/mem/cache/coherence/uni_coherence.hh +++ b/src/mem/cache/coherence/uni_coherence.hh @@ -140,7 +140,7 @@ class UniCoherence bool hasProtocol() { return false; } - void propogateInvalidate(PacketPtr pkt, bool isTiming); + bool propogateInvalidate(PacketPtr pkt, bool isTiming); }; #endif //__UNI_COHERENCE_HH__ diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index d34c19255..8b8a25405 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 437 # Nu global.BPredUnit.condPredicted 1563 # Number of conditional branches predicted global.BPredUnit.lookups 5229 # Number of BP lookups global.BPredUnit.usedRAS 2821 # Number of times the RAS was used to get a target. -host_inst_rate 15039 # Simulator instruction rate (inst/s) -host_mem_usage 180156 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 3741816 # Simulator tick rate (ticks/s) +host_inst_rate 15743 # Simulator instruction rate (inst/s) +host_mem_usage 180184 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host +host_tick_rate 3916768 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. memdepunit.memDep.insertedLoads 3775 # Number of loads inserted to the mem dependence unit. @@ -73,7 +73,7 @@ system.cpu.dcache.WriteReq_mshr_hits 181 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 375299 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 3366.651163 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.587209 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked @@ -325,49 +325,48 @@ system.cpu.iq.iqSquashedInstsExamined 13381 # Nu system.cpu.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 9575 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 482 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 480 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 4520.691667 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2303.372917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 2169932 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 480 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 1105619 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 480 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004167 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 4520.691667 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 2303.372917 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 2169932 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995851 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 1105619 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995851 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 482 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 4520.691667 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 2303.372917 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 2169932 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995851 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 1105619 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -384,7 +383,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 480 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 248.469634 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 53773 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 27822f334..68f6bcca4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 179790 # Simulator instruction rate (inst/s) -host_mem_usage 179436 # Number of bytes of host memory used +host_inst_rate 167195 # Simulator instruction rate (inst/s) +host_mem_usage 179768 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 55533187 # Simulator tick rate (ticks/s) +host_tick_rate 51710933 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated @@ -143,49 +143,48 @@ system.cpu.icache.total_refs 5366 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002268 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -202,7 +201,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index aa4877339..365f828db 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1201 # Nu global.BPredUnit.condPredicted 4031 # Number of conditional branches predicted global.BPredUnit.lookups 12370 # Number of BP lookups global.BPredUnit.usedRAS 6337 # Number of times the RAS was used to get a target. -host_inst_rate 9282 # Simulator instruction rate (inst/s) -host_mem_usage 181628 # Number of bytes of host memory used -host_seconds 1.21 # Real time elapsed on the host -host_tick_rate 1845830 # Simulator tick rate (ticks/s) +host_inst_rate 9475 # Simulator instruction rate (inst/s) +host_mem_usage 181200 # Number of bytes of host memory used +host_seconds 1.19 # Real time elapsed on the host +host_tick_rate 1884343 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 20 # Number of conflicting loads. memdepunit.memDep.conflictingStores 97 # Number of conflicting stores. @@ -571,36 +571,34 @@ system.cpu.iq.iqSquashedInstsExamined 27426 # Nu system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 20011 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 975 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 975 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 973 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 973 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 6750.932169 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency_0 6750.932169 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3603.773895 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3603.773895 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 6568657 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency_0 6568657 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997949 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.997949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 973 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses_0 973 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 3506472 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3506472 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997949 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 973 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses_0 973 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002055 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 975 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 975 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 973 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 6750.932169 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_0 6750.932169 # average overall miss latency @@ -608,14 +606,14 @@ system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> system.cpu.l2cache.demand_avg_mshr_miss_latency 3603.773895 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3603.773895 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 0 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 6568657 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_0 6568657 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997949 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997949 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses system.cpu.l2cache.demand_misses 973 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_0 973 # number of demand (read+write) misses @@ -626,8 +624,8 @@ system.cpu.l2cache.demand_mshr_hits_1 0 # nu system.cpu.l2cache.demand_mshr_miss_latency 3506472 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_0 3506472 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997949 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 973 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_0 973 # number of demand (read+write) MSHR misses @@ -637,8 +635,8 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 975 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 975 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 973 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 6750.932169 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_0 6750.932169 # average overall miss latency @@ -649,15 +647,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_hits_0 0 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 6568657 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_0 6568657 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_1 no value # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses system.cpu.l2cache.overall_misses 973 # number of overall misses system.cpu.l2cache.overall_misses_0 973 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses @@ -667,8 +665,8 @@ system.cpu.l2cache.overall_mshr_hits_1 0 # nu system.cpu.l2cache.overall_mshr_miss_latency 3506472 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_0 3506472 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997949 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 973 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_0 973 # number of overall MSHR misses @@ -696,7 +694,7 @@ system.cpu.l2cache.soft_prefetch_mshr_full 0 # system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 489.113488 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks diff --git a/util/m5/m5op.S b/util/m5/m5op.S index c47bd15b0..61e79d5d3 100644 --- a/util/m5/m5op.S +++ b/util/m5/m5op.S @@ -36,7 +36,9 @@ #define quiescens_func 0x02 #define quiescecycle_func 0x03 #define quiescetime_func 0x04 -#define exit_old_func 0x20 // deprectated! +#define ivlb 0x10 // obsolete +#define ivle 0x11 // obsolete +#define exit_old_func 0x20 // deprecated! #define exit_func 0x21 #define initparam_func 0x30 #define loadsymbol_func 0x31 |