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-rw-r--r--arch/mips/faults.hh3
-rw-r--r--arch/mips/isa/base.isa2
-rw-r--r--arch/mips/isa/bitfields.isa10
-rw-r--r--arch/mips/isa/decoder.isa43
-rw-r--r--arch/mips/isa/formats.isa3
-rw-r--r--arch/mips/isa/formats/branch.isa4
-rw-r--r--arch/mips/isa/formats/fp.isa63
-rw-r--r--arch/mips/isa/formats/mem.isa2
-rw-r--r--arch/mips/isa/formats/noop.isa6
-rw-r--r--arch/mips/isa/formats/util.isa2
-rw-r--r--arch/mips/isa/includes.isa1
-rw-r--r--arch/mips/isa_traits.hh2
-rw-r--r--cpu/static_inst.hh2
13 files changed, 57 insertions, 86 deletions
diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh
index 4e1cb5ed6..60c9e735c 100644
--- a/arch/mips/faults.hh
+++ b/arch/mips/faults.hh
@@ -32,9 +32,6 @@
#include "sim/faults.hh"
#include "arch/isa_traits.hh" //For the Addr type
-class Garbage;
-class Fault;
-
class AlphaFault : public Fault
{
public:
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
index 49de59e55..7600632d3 100644
--- a/arch/mips/isa/base.isa
+++ b/arch/mips/isa/base.isa
@@ -7,6 +7,8 @@
//Outputs to decoder.hh
output header {{
+#define R31 31
+
/**
* Base class for all MIPS static instructions.
*/
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 532b3793a..3a01b64ee 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -5,9 +5,15 @@
// Bitfield definitions.
//
+def bitfield OPCODE <31:26>;
def bitfield OPCODE_HI <31:29>;
def bitfield OPCODE_LO <28:26>;
+def bitfield REGIMM <20:16>;
+def bitfield REGIMM_HI <20:19>;
+def bitfield REGIMM_LO <18:16>;
+
+def bitfield FUNCTION < 5: 0>;
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
@@ -31,6 +37,8 @@ def bitfield FT <20:16>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
+def bitfield ND <17:17>;
+def bitfield TF <16:16>;
def bitfield MOVCI <16:16>;
def bitfield MOVCF <16:16>;
def bitfield SRL <21:21>;
@@ -45,7 +53,7 @@ def bitfield OFFSET <15: 0>; // displacement
// Jmp format
def bitfield JMPTARG <25: 0>;
-def bitfield JMPHINT <10: 6>;
+def bitfield HINT <10: 6>;
def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 7dd08ac49..f16da7f87 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -96,13 +96,13 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode FUNCTION_LO {
format IntOp {
0x0: mult({{
- INT64 temp1 = Rs.sw * Rt.sw;
+ int64_t temp1 = Rs.sw * Rt.sw;
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>;
}});
0x1: multu({{
- INT64 temp1 = Rs.uw * Rt.uw;
+ int64_t temp1 = Rs.uw * Rt.uw;
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
Rd.sw = Rs.uw * Rt.uw;
@@ -141,7 +141,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode FUNCTION_LO {
- format Trap {
+ format BasicOp {
0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
@@ -167,7 +167,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x1: decode REGIMM_LO {
- format Trap {
+ format BasicOp {
0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
@@ -179,14 +179,14 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: decode REGIMM_LO {
format Branch {
- 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink);
- 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink);
+ 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn);
+ 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn);
}
format BranchLikely {
//Will be removed in future MIPS releases
- 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink);
- 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink);
+ 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn);
+ 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn);
}
}
@@ -336,7 +336,7 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
- format Trap {
+ format BasicOp {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
@@ -433,8 +433,8 @@ decode OPCODE_HI default Unknown::unknown() {
}
format Float64Op {
- 0x2: recips({{ Fd = 1 / Fs; }});
- 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
+ 0x5: recips({{ Fd = 1 / Fs; }});
+ 0x6: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
}
}
@@ -502,8 +502,8 @@ decode OPCODE_HI default Unknown::unknown() {
}
format BasicOp {
- 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }});
- 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
+ 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }});
+ 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }});
}
format Float64Op {
@@ -538,12 +538,12 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
0x4: decode FUNCTION {
format FloatOp {
- 0x10: cvt_s({{
+ 0x20: cvt_s({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
- 0x10: cvt_d({{
+ 0x21: cvt_d({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
@@ -613,6 +613,11 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
+ format BasicOp {
+ 0x2: movzps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
+ 0x3: movnps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }});
+ }
+
}
0x4: decode RS_LO {
@@ -763,14 +768,14 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
format IntOp {
0x0: madd({{
- INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
}});
0x1: maddu({{
- INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
@@ -779,14 +784,14 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
- INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
+ int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
}});
0x5: msubu({{
- INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
+ int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
index c244013df..a6aec9437 100644
--- a/arch/mips/isa/formats.isa
+++ b/arch/mips/isa/formats.isa
@@ -10,7 +10,7 @@
//Include utility formats/functions
##include "m5/arch/mips/isa/formats/util.isa"
-//Include the integerOp and integerOpCc format
+//Include the integer formats
##include "m5/arch/mips/isa/formats/int.isa"
//Include the floatOp format
@@ -30,4 +30,3 @@
//Include the noop format
##include "m5/arch/mips/isa/formats/unknown.isa"
-
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index fc207fd3f..c896e9b2d 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -70,7 +70,7 @@ output header {{
int32_t disp;
/// Constructor.
- Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+ BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
disp(OFFSET << 2)
{
@@ -243,7 +243,7 @@ output decoder {{
ss << ",";
}
- ccprintf(ss, "(r%d)", RB);
+ ccprintf(ss, "(r%d)", RT);
return ss.str();
}
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index 23fcbaa67..7dd1e8442 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
@@ -5,7 +7,7 @@
output header {{
/**
- * Base class for integer operations.
+ * Base class for FP operations.
*/
class FPOp : public MipsStaticInst
{
@@ -70,62 +72,19 @@ def template FloatingPointExecute {{
}};
// Primary format for integer operate instructions:
-def format FloatOp(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- checkPriv = (code.find('checkPriv') != -1)
- code.replace('checkPriv', '')
- if checkPriv:
- code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
- else:
- code.replace('checkPriv;', '')
- for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
- ('xvValue', '0'), ('xcValue', '0')):
- code.replace(marker, value)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format FloatOp(code, *flags) {{
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = FloatingPointExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
// Primary format for integer operate instructions:
-def format Float64Op(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- checkPriv = (code.find('checkPriv') != -1)
- code.replace('checkPriv', '')
- if checkPriv:
- code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
- else:
- code.replace('checkPriv;', '')
- for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
- ('xvValue', '0'), ('xcValue', '0')):
- code.replace(marker, value)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = FloatingPointExecute.subst(iop)
-}};
-
-// Primary format for integer operate instructions:
-def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
- orig_code = code
-
- cblk = CodeBlock(code)
- checkPriv = (code.find('checkPriv') != -1)
- code.replace('checkPriv', '')
- if checkPriv:
- code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
- else:
- code.replace('checkPriv;', '')
- for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
- ('xvValue', xvValue), ('xcValue', xcValue)):
- code.replace(marker, value)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
+def format Float64Op(code, *flags) {{
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = IntegerExecute.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 134548746..fcdb577c6 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -70,7 +70,7 @@ output decoder {{
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
- flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
+ flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT);
}
}};
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index d366461e2..05c5ac10f 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -63,12 +63,12 @@ output exec {{
}
}};
-// integer & FP operate instructions use Rc as dest, so check for
-// Rc == 31 to detect nops
+// integer & FP operate instructions use RT as dest, so check for
+// RT == 0 to detect nops
def template OperateNopCheckDecode {{
{
MipsStaticInst *i = new %(class_name)s(machInst);
- if (RC == 31) {
+ if (RD == 0) {
i = makeNop(i);
}
return i;
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
index f0671726c..c06877b35 100644
--- a/arch/mips/isa/formats/util.isa
+++ b/arch/mips/isa/formats/util.isa
@@ -122,4 +122,4 @@ output exec {{
{
//CODE HERE
}
-}
+}};
diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa
index ff7cb7d1d..da919be00 100644
--- a/arch/mips/isa/includes.isa
+++ b/arch/mips/isa/includes.isa
@@ -9,7 +9,6 @@ output header {{
#include <iomanip>
#include "cpu/static_inst.hh"
-#include "traps.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags
}};
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index c636cd241..71da82ffa 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -56,7 +56,7 @@ namespace MipsISA
{
typedef uint32_t MachInst;
-// typedef uint64_t Addr;
+// typedef uint64_t Addr;
typedef uint8_t RegIndex;
enum {
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 5106dcf06..db9e73714 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted
IsCall, ///< Subroutine call.
IsReturn, ///< Subroutine return.
+ IsCondDelaySlot,///< Conditional Delay-Slot Instruction
+
IsThreadSync, ///< Thread synchronization operation.
IsSerializing, ///< Serializes pipeline: won't execute until all
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 12:19:27 +0000