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-rw-r--r--configs/common/FSConfig.py12
-rw-r--r--src/dev/Device.py2
-rw-r--r--src/dev/Pci.py2
-rw-r--r--src/dev/arm/RealView.py11
-rw-r--r--src/dev/pcidev.cc4
-rw-r--r--src/dev/x86/SouthBridge.py2
-rw-r--r--src/python/m5/SimObject.py2
-rw-r--r--src/python/m5/params.py5
8 files changed, 30 insertions, 10 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 8407db869..6154f9877 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -84,7 +84,11 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.port
+ self.tsunami.ide.config = self.iobus.port
+ self.tsunami.ide.dma = self.iobus.port
self.tsunami.ethernet.pio = self.iobus.port
+ self.tsunami.ethernet.config = self.iobus.port
+ self.tsunami.ethernet.dma = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -129,7 +133,11 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.piobus)
self.tsunami.ide.pio = self.piobus.port
+ self.tsunami.ide.config = self.piobus.port
+ self.tsunami.ide.dma = self.piobus.port
self.tsunami.ethernet.pio = self.piobus.port
+ self.tsunami.ethernet.config = self.piobus.port
+ self.tsunami.ethernet.dma = self.piobus.port
#
# Store the dma devices for later connection to dma ruby ports.
@@ -324,7 +332,11 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.port
+ self.malta.ide.config = self.iobus.port
+ self.malta.ide.dma = self.iobus.port
self.malta.ethernet.pio = self.iobus.port
+ self.malta.ethernet.config = self.iobus.port
+ self.malta.ethernet.dma = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
diff --git a/src/dev/Device.py b/src/dev/Device.py
index bf43449b5..aa622aa05 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -46,7 +46,7 @@ class BasicPioDevice(PioDevice):
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
- dma = Port(Self.pio.peerObj.port, "DMA port")
+ dma = Port("DMA port")
min_backoff_delay = Param.Latency('4ns',
"min time between a nack packet being received and the next request made by the device")
max_backoff_delay = Param.Latency('10us',
diff --git a/src/dev/Pci.py b/src/dev/Pci.py
index bd67d82fb..9c2f27142 100644
--- a/src/dev/Pci.py
+++ b/src/dev/Pci.py
@@ -41,7 +41,7 @@ class PciConfigAll(PioDevice):
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
- config = Port(Self.pio.peerObj.port, "PCI configuration space port")
+ config = Port("PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index cd7744362..1dec9a40d 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -199,9 +199,12 @@ class RealViewPBX(RealView):
self.timer0.pio = bus.port
self.timer1.pio = bus.port
self.clcd.pio = bus.port
+ self.clcd.dma = bus.port
self.kmi0.pio = bus.port
self.kmi1.pio = bus.port
self.cf_ctrl.pio = bus.port
+ self.cf_ctrl.config = bus.port
+ self.cf_ctrl.dma = bus.port
self.dmac_fake.pio = bus.port
self.uart1_fake.pio = bus.port
self.uart2_fake.pio = bus.port
@@ -274,6 +277,7 @@ class RealViewEB(RealView):
self.timer0.pio = bus.port
self.timer1.pio = bus.port
self.clcd.pio = bus.port
+ self.clcd.dma = bus.port
self.kmi0.pio = bus.port
self.kmi1.pio = bus.port
self.dmac_fake.pio = bus.port
@@ -364,13 +368,20 @@ class VExpress_ELT(RealView):
self.elba_timer0.pio = bus.port
self.elba_timer1.pio = bus.port
self.clcd.pio = bus.port
+ self.clcd.dma = bus.port
self.kmi0.pio = bus.port
self.kmi1.pio = bus.port
self.elba_kmi0.pio = bus.port
self.elba_kmi1.pio = bus.port
self.cf_ctrl.pio = bus.port
+ self.cf_ctrl.config = bus.port
+ self.cf_ctrl.dma = bus.port
self.ide.pio = bus.port
+ self.ide.config = bus.port
+ self.ide.dma = bus.port
self.ethernet.pio = bus.port
+ self.ethernet.config = bus.port
+ self.ethernet.dma = bus.port
self.pciconfig.pio = bus.default
bus.use_default_range = True
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index c36ac11ba..534cbb173 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -150,8 +150,8 @@ PciDev::PciDev(const Params *p)
void
PciDev::init()
{
- if (!configPort)
- panic("pci config port not connected to anything!");
+ if (!configPort && !configPort->isConnected())
+ panic("PCI config port on %s not connected to anything!\n", name());
configPort->sendRangeChange();
PioDevice::init();
}
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index c23ecf01c..baff35e0b 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -105,6 +105,8 @@ class SouthBridge(SimObject):
self.cmos.pio = bus.port
self.dma1.pio = bus.port
self.ide.pio = bus.port
+ self.ide.config = bus.port
+ self.ide.dma = bus.port
self.keyboard.pio = bus.port
self.pic1.pio = bus.port
self.pic2.pio = bus.port
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 47ca32af2..84d70d663 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -273,8 +273,6 @@ class MetaSimObject(type):
assert(not hasattr(port, 'name'))
port.name = name
cls._ports[name] = port
- if hasattr(port, 'default'):
- cls._cls_get_port_ref(name).connect(port.default)
# same as _get_port_ref, effectively, but for classes
def _cls_get_port_ref(cls, attr):
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 05fe9b774..dfc703a40 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -1488,13 +1488,10 @@ class VectorPortRef(object):
# logical port in the SimObject class, not a particular port on a
# SimObject instance. The latter are represented by PortRef objects.
class Port(object):
- # Port("description") or Port(default, "description")
+ # Port("description")
def __init__(self, *args):
if len(args) == 1:
self.desc = args[0]
- elif len(args) == 2:
- self.default = args[0]
- self.desc = args[1]
else:
raise TypeError, 'wrong number of arguments'
# self.name is set by SimObject class on assignment
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 20:22:47 +0000