diff options
34 files changed, 878 insertions, 751 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py new file mode 100644 index 000000000..d86fba246 --- /dev/null +++ b/configs/common/Caches.py @@ -0,0 +1,39 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +import m5 +from m5.objects import * + +class L1Cache(BaseCache): + assoc = 2 + block_size = 64 + latency = 1 + mshrs = 10 + tgts_per_mshr = 5 + protocol = CoherenceProtocol(protocol='moesi') + diff --git a/configs/common/Options.py b/configs/common/Options.py new file mode 100644 index 000000000..d9c1cc64e --- /dev/null +++ b/configs/common/Options.py @@ -0,0 +1,57 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +# system options +parser.add_option("-d", "--detailed", action="store_true") +parser.add_option("-t", "--timing", action="store_true") +parser.add_option("-n", "--num_cpus", type="int", default=1) +parser.add_option("--caches", action="store_true") + +# Run duration options +parser.add_option("-m", "--maxtick", type="int") +parser.add_option("--maxtime", type="float") + +# Checkpointing options +###Note that performing checkpointing via python script files will override +###checkpoint instructions built into binaries. +parser.add_option("--take_checkpoints", action="store", type="string", + help="<M,N> will take checkpoint at cycle M and every N cycles \ + thereafter") +parser.add_option("--max_checkpoints", action="store", type="int", + help="the maximum number of checkpoints to drop", + default=5) +parser.add_option("--checkpoint_dir", action="store", type="string", + help="Place all checkpoints in this absolute directory") +parser.add_option("-r", "--checkpoint_restore", action="store", type="int", + help="restore from checkpoint <N>") + +# CPU Switching - default switch model goes from a checkpoint +# to a timing simple CPU with caches to warm up, then to detailed CPU for +# data measurement +parser.add_option("-s", "--standard_switch", action="store_true", + help="switch from one cpu mode to another") diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py new file mode 100644 index 000000000..b927315ba --- /dev/null +++ b/configs/common/Simulation.py @@ -0,0 +1,175 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +from os import getcwd +import m5 +from m5.objects import * +m5.AddToPath('../common') +from Caches import * + +def run(options, root, testsys): + if options.maxtick: + maxtick = options.maxtick + elif options.maxtime: + simtime = int(options.maxtime * root.clock.value) + print "simulating for: ", simtime + maxtick = simtime + else: + maxtick = -1 + + if options.checkpoint_dir: + cptdir = options.checkpoint_dir + else: + cptdir = getcwd() + + np = options.num_cpus + max_checkpoints = options.max_checkpoints + + if options.standard_switch: + switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) + for i in xrange(np)] + switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) + for i in xrange(np)] + for i in xrange(np): + switch_cpus[i].system = testsys + switch_cpus1[i].system = testsys + if not m5.build_env['FULL_SYSTEM']: + switch_cpus[i].workload = testsys.cpu[i].workload + switch_cpus1[i].workload = testsys.cpu[i].workload + switch_cpus[i].clock = testsys.cpu[0].clock + switch_cpus1[i].clock = testsys.cpu[0].clock + if options.caches: + switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB')) + + switch_cpus[i].mem = testsys.physmem + switch_cpus1[i].mem = testsys.physmem + switch_cpus[i].connectMemPorts(testsys.membus) + root.switch_cpus = switch_cpus + root.switch_cpus1 = switch_cpus1 + switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] + switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)] + + m5.instantiate(root) + + if options.checkpoint_restore: + from os.path import isdir + from os import listdir + import re + + if not isdir(cptdir): + m5.panic("checkpoint dir %s does not exist!" % cptdir) + + dirs = listdir(cptdir) + expr = re.compile('cpt.([0-9]*)') + cpts = [] + for dir in dirs: + match = expr.match(dir) + if match: + cpts.append(match.group(1)) + + cpts.sort(lambda a,b: cmp(long(a), long(b))) + + cpt_num = options.checkpoint_restore + + if cpt_num > len(cpts): + m5.panic('Checkpoint %d not found' % cpt_num) + + m5.restoreCheckpoint(root, + "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]])) + + if options.standard_switch: + exit_event = m5.simulate(10000) + + ## when you change to Timing (or Atomic), you halt the system given + ## as argument. When you are finished with the system changes + ## (including switchCpus), you must resume the system manually. + ## You DON'T need to resume after just switching CPUs if you haven't + ## changed anything on the system level. + + m5.changeToTiming(testsys) + m5.switchCpus(switch_cpu_list) + m5.resume(testsys) + + exit_event = m5.simulate(3000000) + m5.switchCpus(switch_cpu_list1) + + num_checkpoints = 0 + exit_cause = '' + + if options.take_checkpoints: + [when, period] = options.take_checkpoints.split(",", 1) + when = int(when) + period = int(period) + + print "when is ", when, " period is ", period + exit_event = m5.simulate(when) + while exit_event.getCause() == "checkpoint": + exit_event = m5.simulate(when - m5.curTick()) + + if exit_event.getCause() == "simulate() limit reached": + m5.checkpoint(root, cptdir + "cpt.%d") + num_checkpoints += 1 + + sim_ticks = when + exit_cause = "maximum %d checkpoints dropped" % max_checkpoints + while num_checkpoints < max_checkpoints: + if (sim_ticks + period) > maxtick and maxtick != -1: + exit_event = m5.simulate(maxtick - sim_ticks) + exit_cause = exit_event.getCause() + break + else: + exit_event = m5.simulate(period) + sim_ticks += period + while exit_event.getCause() == "checkpoint": + exit_event = m5.simulate(sim_ticks - m5.curTick()) + if exit_event.getCause() == "simulate() limit reached": + m5.checkpoint(root, cptdir + "cpt.%d") + num_checkpoints += 1 + + else: #no checkpoints being taken via this script + exit_event = m5.simulate(maxtick) + + while exit_event.getCause() == "checkpoint": + m5.checkpoint(root, cptdir + "cpt.%d") + num_checkpoints += 1 + if num_checkpoints == max_checkpoints: + exit_cause = "maximum %d checkpoints dropped" % max_checkpoints + break + + if maxtick == -1: + exit_event = m5.simulate(maxtick) + else: + exit_event = m5.simulate(maxtick - m5.curTick()) + + exit_cause = exit_event.getCause() + + if exit_cause == '': + exit_cause = exit_event.getCause() + print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + diff --git a/configs/example/fs.py b/configs/example/fs.py index 76b62a066..ec3be835a 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -34,6 +34,7 @@ m5.AddToPath('../common') from FSConfig import * from SysPaths import * from Benchmarks import * +import Simulation if not m5.build_env['FULL_SYSTEM']: m5.panic("This script requires full-system mode (ALPHA_FS).") @@ -48,40 +49,13 @@ parser.add_option("-b", "--benchmark", action="store", type="string", help="Specify the benchmark to run. Available benchmarks: %s"\ % DefinedBenchmarks) -# system options -parser.add_option("-d", "--detailed", action="store_true") -parser.add_option("-t", "--timing", action="store_true") -parser.add_option("-n", "--num_cpus", type="int", default=1) -parser.add_option("--caches", action="store_true") - -# Run duration options -parser.add_option("-m", "--maxtick", type="int") -parser.add_option("--maxtime", type="float") - # Metafile options parser.add_option("--etherdump", action="store", type="string", dest="etherdump", help="Specify the filename to dump a pcap capture of the" \ "ethernet traffic") -# Checkpointing options -###Note that performing checkpointing via python script files will override -###checkpoint instructions built into binaries. -parser.add_option("--take_checkpoints", action="store", type="string", - help="<M,N> will take checkpoint at cycle M and every N cycles \ - thereafter") -parser.add_option("--max_checkpoints", action="store", type="int", - help="the maximum number of checkpoints to drop", - default=5) -parser.add_option("--checkpoint_dir", action="store", type="string", - help="Place all checkpoints in this absolute directory") -parser.add_option("-r", "--checkpoint_restore", action="store", type="int", - help="restore from checkpoint <N>") -# CPU Switching - default switch model goes from a checkpoint -# to a timing simple CPU with caches to warm up, then to detailed CPU for -# data measurement -parser.add_option("-s", "--standard_switch", action="store_true", - help="switch from one cpu mode to another") +execfile("Options.py") (options, args) = parser.parse_args() @@ -89,14 +63,6 @@ if args: print "Error: script doesn't take any positional arguments" sys.exit(1) -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - latency = 1 - mshrs = 10 - tgts_per_mshr = 5 - protocol = CoherenceProtocol(protocol='moesi') - # driver system CPU is always simple... note this is an assignment of # a class, not an instance. DriveCPUClass = AtomicSimpleCPU @@ -134,8 +100,8 @@ np = options.num_cpus test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] for i in xrange(np): if options.caches and not options.standard_switch: - test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) + test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L2Cache(size = '64kB')) test_sys.cpu[i].connectMemPorts(test_sys.membus) test_sys.cpu[i].mem = test_sys.physmem @@ -151,129 +117,4 @@ else: print "Error I don't know how to create more than 2 systems." sys.exit(1) -if options.standard_switch: - switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] - switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)] - for i in xrange(np): - switch_cpus[i].system = test_sys - switch_cpus1[i].system = test_sys - switch_cpus[i].clock = TestCPUClass.clock - switch_cpus1[i].clock = TestCPUClass.clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) - - switch_cpus[i].mem = test_sys.physmem - switch_cpus1[i].mem = test_sys.physmem - switch_cpus[i].connectMemPorts(test_sys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus1 = switch_cpus1 - switch_cpu_list = [(test_sys.cpu[i], switch_cpus[i]) for i in xrange(np)] - switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)] - -m5.instantiate(root) - -if options.checkpoint_dir: - cptdir = options.checkpoint_dir -else: - cptdir = os.getcwd() - -if options.checkpoint_restore: - from os.path import isdir - from os import listdir, getcwd - import re - - if not isdir(cptdir): - m5.panic("checkpoint dir %s does not exist!" % cptdir) - - dirs = listdir(cptdir) - expr = re.compile('cpt.([0-9]*)') - cpts = [] - for dir in dirs: - match = expr.match(dir) - if match: - cpts.append(match.group(1)) - - cpts.sort(lambda a,b: cmp(long(a), long(b))) - - if options.checkpoint_restore > len(cpts): - m5.panic('Checkpoint %d not found' % options.checkpoint_restore) - - m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]])) - -if options.standard_switch: - exit_event = m5.simulate(1000) - ## when you change to Timing (or Atomic), you halt the system given - ## as argument. When you are finished with the system changes - ## (including switchCpus), you must resume the system manually. - ## You DON'T need to resume after just switching CPUs if you haven't - ## changed anything on the system level. - m5.changeToTiming(test_sys) - m5.switchCpus(switch_cpu_list) - m5.resume(test_sys) - - exit_event = m5.simulate(500000000000) - m5.switchCpus(switch_cpu_list1) - -if options.maxtick: - maxtick = options.maxtick -elif options.maxtime: - simtime = int(options.maxtime * root.clock.value) - print "simulating for: ", simtime - maxtick = simtime -else: - maxtick = -1 - -num_checkpoints = 0 - -exit_cause = '' - -if options.take_checkpoints: - [when, period] = options.take_checkpoints.split(",", 1) - when = int(when) - period = int(period) - - exit_event = m5.simulate(when) - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(when - m5.curTick()) - - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - - sim_ticks = when - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - while num_checkpoints < options.max_checkpoints: - if (sim_ticks + period) > maxtick and maxtick != -1: - exit_event = m5.simulate(maxtick - sim_ticks) - exit_cause = exit_event.getCause() - break - else: - exit_event = m5.simulate(period) - sim_ticks += period - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(period - m5.curTick()) - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - -else: #no checkpoints being taken via this script - exit_event = m5.simulate(maxtick) - - while exit_event.getCause() == "checkpoint": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - if num_checkpoints == options.max_checkpoints: - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - break - - if maxtick == -1: - exit_event = m5.simulate(maxtick) - else: - exit_event = m5.simulate(maxtick - m5.curTick()) - - exit_cause = exit_event.getCause() - -if exit_cause == '': - exit_cause = exit_event.getCause() -print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause +Simulation.run(options, root, test_sys) diff --git a/configs/example/se.py b/configs/example/se.py index c4150eed7..e4fe93294 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -34,6 +34,7 @@ import m5 from m5.objects import * import os, optparse, sys m5.AddToPath('../common') +import Simulation parser = optparse.OptionParser() @@ -47,34 +48,7 @@ parser.add_option("-o", "--options", default="", parser.add_option("-i", "--input", default="", help="A file of input to give to the binary.") -# System options -parser.add_option("-d", "--detailed", action="store_true") -parser.add_option("-t", "--timing", action="store_true") -parser.add_option("--caches", action="store_true") - -# Run duration options -parser.add_option("-m", "--maxtick", type="int") -parser.add_option("--maxtime", type="float") - -#Checkpointing options -###Note that performing checkpointing via python script files will override -###checkpoint instructions built into binaries. -parser.add_option("--take_checkpoints", action="store", type="string", - help="<M,N> will take checkpoint at cycle M and every N cycles \ - thereafter") -parser.add_option("--max_checkpoints", action="store", type="int", - help="the maximum number of checkpoints to drop", - default=5) -parser.add_option("--checkpoint_dir", action="store", type="string", - help="Place all checkpoints in this absolute directory") -parser.add_option("-r", "--checkpoint_restore", action="store", type="int", - help="restore from checkpoint <N>") - -#CPU Switching - default switch model generally goes from a checkpoint -#to a timing simple CPU with caches to warm up, then to detailed CPU for -#data measurement -parser.add_option("-s", "--standard_switch", action="store_true", - help="switch from one cpu mode to another") +execfile("Options.py") (options, args) = parser.parse_args() @@ -82,13 +56,6 @@ if args: print "Error: script doesn't take any positional arguments" sys.exit(1) -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - latency = 1 - mshrs = 10 - tgts_per_mshr = 5 - process = LiveProcess() process.executable = options.cmd process.cmd = options.cmd + " " + options.options @@ -117,160 +84,33 @@ if options.detailed: if options.timing: - cpu = TimingSimpleCPU() + CPUClass = TimingSimpleCPU + test_mem_mode = 'timing' elif options.detailed: - cpu = DerivO3CPU() + CPUClass = DerivO3CPU + test_mem_mode = 'timing' else: - cpu = AtomicSimpleCPU() + CPUClass = AtomicSimpleCPU + test_mem_mode = 'atomic' -cpu.workload = process -cpu.cpu_id = 0 +CPUClass.clock = '2GHz' -system = System(cpu = cpu, - physmem = PhysicalMemory(range=AddrRange("512MB")), - membus = Bus()) +np = options.num_cpus -if options.caches and not options.standard_switch: - system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) +system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], + physmem = PhysicalMemory(range=AddrRange("512MB")), + membus = Bus(), mem_mode = test_mem_mode) system.physmem.port = system.membus.port -system.cpu.connectMemPorts(system.membus) -system.cpu.mem = system.physmem -system.cpu.clock = '2GHz' -root = Root(system = system) - -if options.timing or options.detailed: - root.system.mem_mode = 'timing' - -if options.standard_switch: - switch_cpu = TimingSimpleCPU(defer_registration=True, cpu_id=1) - switch_cpu1 = DerivO3CPU(defer_registration=True, cpu_id=2) - switch_cpu.system = system - switch_cpu1.system = system - switch_cpu.clock = cpu.clock - switch_cpu1.clock = cpu.clock - if options.caches: - switch_cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) - - switch_cpu.workload = process - switch_cpu1.workload = process - switch_cpu.mem = system.physmem - switch_cpu1.mem = system.physmem - switch_cpu.connectMemPorts(system.membus) - root.switch_cpu = switch_cpu - root.switch_cpu1 = switch_cpu1 - switch_cpu_list = [(system.cpu, switch_cpu)] - switch_cpu_list1 = [(switch_cpu, switch_cpu1)] - -# instantiate configuration -m5.instantiate(root) - -if options.checkpoint_dir: - cptdir = options.checkpoint_dir -else: - cptdir = os.getcwd() - -if options.checkpoint_restore: - from os.path import isdir - from os import listdir, getcwd - import re - - if not isdir(cptdir): - m5.panic("checkpoint dir %s does not exist!" % cptdir) - - dirs = listdir(cptdir) - expr = re.compile('cpt.([0-9]*)') - cpts = [] - for dir in dirs: - match = expr.match(dir) - if match: - cpts.append(match.group(1)) - - cpts.sort(lambda a,b: cmp(long(a), long(b))) - if options.checkpoint_restore > len(cpts): - m5.panic('Checkpoint %d not found' % options.checkpoint_restore) - - print "restoring checkpoint from ","/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]]) - m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]])) - -if options.standard_switch: - exit_event = m5.simulate(10000) - ## when you change to Timing (or Atomic), you halt the system given - ## as argument. When you are finished with the system changes - ## (including switchCpus), you must resume the system manually. - ## You DON'T need to resume after just switching CPUs if you haven't - ## changed anything on the system level. - m5.changeToTiming(system) - m5.switchCpus(switch_cpu_list) - m5.resume(system) - - exit_event = m5.simulate(500000000000) - m5.switchCpus(switch_cpu_list1) - -if options.maxtick: - maxtick = options.maxtick -elif options.maxtime: - simtime = int(options.maxtime * root.clock.value) - print "simulating for: ", simtime - maxtick = simtime -else: - maxtick = -1 - -num_checkpoints = 0 - -exit_cause = '' - -if options.take_checkpoints: - [when, period] = options.take_checkpoints.split(",", 1) - when = int(when) - period = int(period) - - exit_event = m5.simulate(when) - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(when - m5.curTick()) - - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - - sim_ticks = when - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - while num_checkpoints < options.max_checkpoints: - if (sim_ticks + period) > maxtick and maxtick != -1: - exit_event = m5.simulate(maxtick - sim_ticks) - exit_cause = exit_event.getCause() - break - else: - exit_event = m5.simulate(period) - sim_ticks += period - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(period - m5.curTick()) - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - -else: #no checkpoints being taken via this script - exit_event = m5.simulate(maxtick) - - while exit_event.getCause() == "checkpoint": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - if num_checkpoints == options.max_checkpoints: - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - break - - if maxtick == -1: - exit_event = m5.simulate(maxtick) - else: - exit_event = m5.simulate(maxtick - m5.curTick()) - - exit_cause = exit_event.getCause() - -if exit_cause == '': - exit_cause = exit_event.getCause() -print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause +for i in xrange(np): + if options.caches and not options.standard_switch: + system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L2Cache(size = '64kB')) + system.cpu[i].connectMemPorts(system.membus) + system.cpu[i].mem = system.physmem + system.cpu[i].workload = process +root = Root(system = system) +Simulation.run(options, root, system) diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index b235398f1..6504c7b32 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1316,7 +1316,7 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') - wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name) + wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name return wb diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 7b7765935..2c8da44c5 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -29,15 +29,22 @@ * Kevin Lim */ +#include <algorithm> + #include "arch/sparc/faults.hh" -#include "cpu/thread_context.hh" -#include "cpu/base.hh" +#include "arch/sparc/isa_traits.hh" +#include "arch/sparc/process.hh" +#include "base/bitfield.hh" #include "base/trace.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" #if !FULL_SYSTEM -#include "sim/process.hh" #include "mem/page_table.hh" +#include "sim/process.hh" #endif +using namespace std; + namespace SparcISA { @@ -229,6 +236,121 @@ FaultPriority PageTableFault::_priority = 0; FaultStat PageTableFault::_count; #endif +/** + * This sets everything up for a normal trap except for actually jumping to + * the handler. It will need to be expanded to include the state machine in + * the manual. Right now it assumes that traps will always be to the + * privileged level. + */ + +void doNormalFault(ThreadContext *tc, TrapType tt) +{ + uint64_t TL = tc->readMiscReg(MISCREG_TL); + uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE); + uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE); + uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + uint64_t CCR = tc->readMiscReg(MISCREG_CCR); + uint64_t ASI = tc->readMiscReg(MISCREG_ASI); + uint64_t CWP = tc->readMiscReg(MISCREG_CWP); + uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); + uint64_t GL = tc->readMiscReg(MISCREG_GL); + uint64_t PC = tc->readPC(); + uint64_t NPC = tc->readNextPC(); + + //Increment the trap level + TL++; + tc->setMiscReg(MISCREG_TL, TL); + + //Save off state + + //set TSTATE.gl to gl + replaceBits(TSTATE, 42, 40, GL); + //set TSTATE.ccr to ccr + replaceBits(TSTATE, 39, 32, CCR); + //set TSTATE.asi to asi + replaceBits(TSTATE, 31, 24, ASI); + //set TSTATE.pstate to pstate + replaceBits(TSTATE, 20, 8, PSTATE); + //set TSTATE.cwp to cwp + replaceBits(TSTATE, 4, 0, CWP); + + //Write back TSTATE + tc->setMiscReg(MISCREG_TSTATE, TSTATE); + + //set TPC to PC + tc->setMiscReg(MISCREG_TPC, PC); + //set TNPC to NPC + tc->setMiscReg(MISCREG_TNPC, NPC); + + //set HTSTATE.hpstate to hpstate + tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); + + //TT = trap type; + tc->setMiscReg(MISCREG_TT, tt); + + //Update the global register level + if(1/*We're delivering the trap in priveleged mode*/) + tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL)); + else + tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL)); + + //PSTATE.mm is unchanged + //PSTATE.pef = whether or not an fpu is present + //XXX We'll say there's one present, even though there aren't + //implementations for a decent number of the instructions + PSTATE |= (1 << 4); + //PSTATE.am = 0 + PSTATE &= ~(1 << 3); + if(1/*We're delivering the trap in priveleged mode*/) + { + //PSTATE.priv = 1 + PSTATE |= (1 << 2); + //PSTATE.cle = PSTATE.tle + replaceBits(PSTATE, 9, 9, PSTATE >> 8); + } + else + { + //PSTATE.priv = 0 + PSTATE &= ~(1 << 2); + //PSTATE.cle = 0 + PSTATE &= ~(1 << 9); + } + //PSTATE.ie = 0 + PSTATE &= ~(1 << 1); + //PSTATE.tle is unchanged + //PSTATE.tct = 0 + //XXX Where exactly is this field? + tc->setMiscReg(MISCREG_PSTATE, PSTATE); + + if(0/*We're delivering the trap in hyperprivileged mode*/) + { + //HPSTATE.red = 0 + HPSTATE &= ~(1 << 5); + //HPSTATE.hpriv = 1 + HPSTATE |= (1 << 2); + //HPSTATE.ibe = 0 + HPSTATE &= ~(1 << 10); + //HPSTATE.tlz is unchanged + tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); + } + + bool changedCWP = true; + if(tt == 0x24) + CWP++; + else if(0x80 <= tt && tt <= 0xbf) + CWP += (CANSAVE + 2); + else if(0xc0 <= tt && tt <= 0xff) + CWP--; + else + changedCWP = false; + + if(changedCWP) + { + CWP = (CWP + NWindows) % NWindows; + tc->setMiscRegWithEffect(MISCREG_CWP, CWP); + } +} + #if FULL_SYSTEM void SparcFault::invoke(ThreadContext * tc) @@ -263,6 +385,40 @@ void TrapInstruction::invoke(ThreadContext * tc) // Should be handled in ISA. } +void SpillNNormal::invoke(ThreadContext *tc) +{ + doNormalFault(tc, trapType()); + + Process *p = tc->getProcessPtr(); + + //This will only work in faults from a SparcLiveProcess + SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); + assert(lp); + + //Then adjust the PC and NPC + Addr spillStart = lp->readSpillStart(); + tc->setPC(spillStart); + tc->setNextPC(spillStart + sizeof(MachInst)); + tc->setNextNPC(spillStart + 2*sizeof(MachInst)); +} + +void FillNNormal::invoke(ThreadContext *tc) +{ + doNormalFault(tc, trapType()); + + Process * p = tc->getProcessPtr(); + + //This will only work in faults from a SparcLiveProcess + SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); + assert(lp); + + //The adjust the PC and NPC + Addr fillStart = lp->readFillStart(); + tc->setPC(fillStart); + tc->setNextPC(fillStart + sizeof(MachInst)); + tc->setNextNPC(fillStart + 2*sizeof(MachInst)); +} + void PageTableFault::invoke(ThreadContext *tc) { Process *p = tc->getProcessPtr(); @@ -282,6 +438,7 @@ void PageTableFault::invoke(ThreadContext *tc) FaultBase::invoke(tc); } } + #endif } // namespace SparcISA diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index b279f4911..394a06294 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -39,8 +39,8 @@ namespace SparcISA { -typedef const uint32_t TrapType; -typedef const uint32_t FaultPriority; +typedef uint32_t TrapType; +typedef uint32_t FaultPriority; class SparcFault : public FaultBase { @@ -547,6 +547,7 @@ class SpillNNormal : public EnumeratedFault FaultName name() {return _name;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} + void invoke(ThreadContext * tc); }; class SpillNOther : public EnumeratedFault @@ -577,6 +578,7 @@ class FillNNormal : public EnumeratedFault FaultName name() {return _name;} FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} + void invoke(ThreadContext * tc); }; class FillNOther : public EnumeratedFault diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa index 372f5c4ef..7e884866c 100644 --- a/src/arch/sparc/isa/bitfields.isa +++ b/src/arch/sparc/isa/bitfields.isa @@ -50,7 +50,7 @@ def bitfield D16LO <13:0>; def bitfield DISP19 <18:0>; def bitfield DISP22 <21:0>; def bitfield DISP30 <29:0>; -def bitfield FCN <29:26>; +def bitfield FCN <29:25>; def bitfield I <13>; def bitfield IMM_ASI <12:5>; def bitfield IMM22 <21:0>; diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 45d3616d9..dc7597e5e 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -357,13 +357,9 @@ decode OP default Unknown::unknown() }}); } 0x29: HPriv::rdhpr({{ - // XXX Need to protect with format that traps non-priv/priv - // access Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); }}); 0x2A: Priv::rdpr({{ - // XXX Need to protect with format that traps non-priv - // access Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); }}); 0x2B: BasicOperate::flushw({{ @@ -425,18 +421,34 @@ decode OP default Unknown::unknown() xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); }}); 0x31: decode FCN { - 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); - 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); + 0x0: Priv::saved({{ + assert(Cansave < NWindows - 2); + assert(Otherwin || Canrestore); + Cansave = Cansave + 1; + if(Otherwin == 0) + Canrestore = Canrestore - 1; + else + Otherwin = Otherwin - 1; + }}); + 0x1: BasicOperate::restored({{ + assert(Cansave || Otherwin); + assert(Canrestore < NWindows - 2); + Canrestore = Canrestore + 1; + if(Otherwin == 0) + Cansave = Cansave - 1; + else + Otherwin = Otherwin - 1; + }}); } 0x32: Priv::wrpr({{ // XXX Need to protect with format that traps non-priv // access - fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); + xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); }}); 0x33: HPriv::wrhpr({{ // XXX Need to protect with format that traps non-priv/priv // access - fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); + xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); }}); 0x34: decode OPF{ format BasicOperate{ @@ -684,10 +696,6 @@ decode OP default Unknown::unknown() NNPC = target; if(fault == NoFault) { - //CWP should be set directly so that it always happens - //Also, this will allow writing to the new window and - //reading from the old one - Cwp = (Cwp - 1 + NWindows) % NWindows; if(Canrestore == 0) { if(Otherwin) @@ -697,14 +705,17 @@ decode OP default Unknown::unknown() } else { - Rd = Rs1 + Rs2_or_imm13; + //CWP should be set directly so that it always happens + //Also, this will allow writing to the new window and + //reading from the old one + Cwp = (Cwp - 1 + NWindows) % NWindows; Cansave = Cansave + 1; Canrestore = Canrestore - 1; + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); } - //This is here to make sure the CWP is written - //no matter what. This ensures that the results - //are written in the new window as well. - xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); } }}); 0x3A: decode CC @@ -747,11 +758,11 @@ decode OP default Unknown::unknown() fault = new SpillNOther(Wstate<5:3>); else fault = new SpillNNormal(Wstate<2:0>); - Cwp = (Cwp + 2) % NWindows; + //Cwp = (Cwp + 2) % NWindows; } else if(Cleanwin - Canrestore == 0) { - Cwp = (Cwp + 1) % NWindows; + //Cwp = (Cwp + 1) % NWindows; fault = new CleanWindow; } else @@ -760,17 +771,13 @@ decode OP default Unknown::unknown() Rd = Rs1 + Rs2_or_imm13; Cansave = Cansave - 1; Canrestore = Canrestore + 1; + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); } - //This is here to make sure the CWP is written - //no matter what. This ensures that the results - //are written in the new window as well. - xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); }}); 0x3D: restore({{ - //CWP should be set directly so that it always happens - //Also, this will allow writing to the new window and - //reading from the old one - Cwp = (Cwp - 1 + NWindows) % NWindows; if(Canrestore == 0) { if(Otherwin) @@ -780,14 +787,18 @@ decode OP default Unknown::unknown() } else { + //CWP should be set directly so that it always happens + //Also, this will allow writing to the new window and + //reading from the old one + Cwp = (Cwp - 1 + NWindows) % NWindows; Rd = Rs1 + Rs2_or_imm13; Cansave = Cansave + 1; Canrestore = Canrestore - 1; + //This is here to make sure the CWP is written + //no matter what. This ensures that the results + //are written in the new window as well. + xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); } - //This is here to make sure the CWP is written - //no matter what. This ensures that the results - //are written in the new window as well. - xc->setMiscRegWithEffect(MISCREG_CWP, Cwp); }}); 0x3E: decode FCN { 0x0: Priv::done({{ @@ -812,7 +823,7 @@ decode OP default Unknown::unknown() Ccr = Tstate<39:32>; Gl = Tstate<42:40>; NPC = Tpc; - NNPC = Tnpc + 4; + NNPC = Tnpc; Tl = Tl - 1; }}); } diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 2a38422a7..04c67d332 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -121,15 +121,14 @@ let {{ // Primary format for integer operate instructions: def format Priv(code, *opt_flags) {{ - checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) || - ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)''' + checkCode = "!(Pstate<2:2> || Hpstate<2:2>)" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, checkCode, name, Name, opt_flags + ('IprAccessOp',)) }}; def format HPriv(code, *opt_flags) {{ - checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)" + checkCode = "!Hpstate<2:2>" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, checkCode, name, Name, opt_flags + ('IprAccessOp',)) diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index b8b75170b..ba2c38e91 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -95,18 +95,19 @@ def operands {{ 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), - 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), + 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47), + 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48), - 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), - 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), - 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), - 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), - 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), - 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), - 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), + 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49), + 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50), + 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51), + 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52), + 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53), + 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54), + 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55), - 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), - 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56), + 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56), + 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57), # Mem gets a large number so it's always last 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 6d5aa4251..fb09121a3 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -57,12 +57,11 @@ namespace SparcISA //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; - // Alpha Does NOT have a delay slot + // SPARC have a delay slot #define ISA_HAS_DELAY_SLOT 1 - //TODO this needs to be a SPARC Noop - // Alpha UNOP (ldq_u r31,0(r0)) - const MachInst NoopMachInst = 0x2ffe0000; + // SPARC NOP (sethi %(hi(0), g0) + const MachInst NoopMachInst = 0x01000000; const int NumIntRegs = 32; const int NumFloatRegs = 64; @@ -87,7 +86,7 @@ namespace SparcISA const int MaxPGL = 2; // NWINDOWS - number of register windows, can be 3 to 32 - const int NWindows = 32; + const int NWindows = 8; // semantically meaningful register indices const int ZeroReg = 0; // architecturally meaningful diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 8041e45c0..bf4572878 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -202,282 +202,164 @@ MiscReg MiscRegFile::readReg(int miscReg) } } -MiscReg MiscRegFile::readRegWithEffect(int miscReg, - Fault &fault, ThreadContext * tc) +MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) { - fault = NoFault; switch (miscReg) { - case MISCREG_Y: - case MISCREG_CCR: - case MISCREG_ASI: - return readReg(miscReg); - case MISCREG_TICK: case MISCREG_PRIVTICK: - // Check for reading privilege - if (tickFields.npt && !isNonPriv()) { - fault = new PrivilegedAction; - return 0; - } return tc->getCpuPtr()->curCycle() - tickFields.counter | tickFields.npt << 63; - case MISCREG_PC: - return tc->readPC(); case MISCREG_FPRS: - fault = new UnimpFault("FPU not implemented\n"); - return 0; + panic("FPU not implemented\n"); case MISCREG_PCR: - fault = new UnimpFault("Performance Instrumentation not impl\n"); - return 0; case MISCREG_PIC: - fault = new UnimpFault("Performance Instrumentation not impl\n"); - return 0; - case MISCREG_GSR: - return readReg(miscReg); - - /** Privilged Registers */ - case MISCREG_TPC: - case MISCREG_TNPC: - case MISCREG_TSTATE: - case MISCREG_TT: - if (tl == 0) { - fault = new IllegalInstruction; - return 0; - } // NOTE THE FALL THROUGH! - case MISCREG_PSTATE: - case MISCREG_TL: - return readReg(miscReg); - - case MISCREG_TBA: - return readReg(miscReg) & ULL(~0x7FFF); - - case MISCREG_PIL: - - case MISCREG_CWP: - case MISCREG_CANSAVE: - case MISCREG_CANRESTORE: - case MISCREG_CLEANWIN: - case MISCREG_OTHERWIN: - case MISCREG_WSTATE: - case MISCREG_GL: - return readReg(miscReg); + panic("Performance Instrumentation not impl\n"); /** Floating Point Status Register */ case MISCREG_FSR: panic("Floating Point not implemented\n"); - default: -#if FULL_SYSTEM - return readFSRegWithEffect(miscReg, fault, tc); -#else - fault = new IllegalInstruction; - return 0; -#endif } + return readReg(miscReg); } -Fault MiscRegFile::setReg(int miscReg, const MiscReg &val) +void MiscRegFile::setReg(int miscReg, const MiscReg &val) { switch (miscReg) { case MISCREG_Y: y = val; - return NoFault; + break; case MISCREG_CCR: ccr = val; - return NoFault; + break; case MISCREG_ASI: asi = val; - return NoFault; + break; case MISCREG_FPRS: fprs = val; - return NoFault; + break; case MISCREG_TICK: - tick = val; - return NoFault; + tick = val; + break; case MISCREG_PCR: case MISCREG_PIC: panic("ASR number %d not implemented\n", miscReg - AsrStart); case MISCREG_GSR: gsr = val; + break; case MISCREG_SOFTINT: - softint = val; - return NoFault; + softint = val; + break; case MISCREG_TICK_CMPR: - tick_cmpr = val; - return NoFault; + tick_cmpr = val; + break; case MISCREG_STICK: - stick = val; - return NoFault; + stick = val; + break; case MISCREG_STICK_CMPR: - stick_cmpr = val; - return NoFault; + stick_cmpr = val; + break; /** Privilged Registers */ case MISCREG_TPC: tpc[tl-1] = val; - return NoFault; + break; case MISCREG_TNPC: tnpc[tl-1] = val; - return NoFault; + break; case MISCREG_TSTATE: tstate[tl-1] = val; - return NoFault; + break; case MISCREG_TT: tt[tl-1] = val; - return NoFault; + break; case MISCREG_PRIVTICK: panic("Priviliged access to tick regesiters not implemented\n"); case MISCREG_TBA: - tba = val; - return NoFault; + // clear lower 7 bits on writes. + tba = val & ULL(~0x7FFF); + break; case MISCREG_PSTATE: pstate = val; - return NoFault; + break; case MISCREG_TL: tl = val; - return NoFault; + break; case MISCREG_PIL: pil = val; - return NoFault; + break; case MISCREG_CWP: cwp = val; - return NoFault; + break; case MISCREG_CANSAVE: cansave = val; - return NoFault; + break; case MISCREG_CANRESTORE: canrestore = val; - return NoFault; + break; case MISCREG_CLEANWIN: cleanwin = val; - return NoFault; + break; case MISCREG_OTHERWIN: otherwin = val; - return NoFault; + break; case MISCREG_WSTATE: wstate = val; - return NoFault; + break; case MISCREG_GL: gl = val; - return NoFault; + break; /** Hyper privileged registers */ case MISCREG_HPSTATE: hpstate = val; - return NoFault; + break; case MISCREG_HTSTATE: htstate[tl-1] = val; - return NoFault; + break; case MISCREG_HINTP: panic("HINTP not implemented\n"); case MISCREG_HTBA: htba = val; - return NoFault; + break; case MISCREG_STRAND_STS_REG: strandStatusReg = val; - return NoFault; + break; case MISCREG_HSTICK_CMPR: hstick_cmpr = val; - return NoFault; + break; /** Floating Point Status Register */ case MISCREG_FSR: fsr = val; - return NoFault; + break; default: panic("Miscellaneous register %d not implemented\n", miscReg); } } -Fault MiscRegFile::setRegWithEffect(int miscReg, +void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { const uint64_t Bit64 = (1ULL << 63); switch (miscReg) { - case MISCREG_Y: - case MISCREG_CCR: - case MISCREG_ASI: - setReg(miscReg, val); - return NoFault; - case MISCREG_PRIVTICK: case MISCREG_TICK: - if (isNonPriv()) - return new PrivilegedOpcode; - if (isPriv()) - return new PrivilegedAction; tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64; tickFields.npt = val & Bit64 ? 1 : 0; - return NoFault; - case MISCREG_PC: - return new IllegalInstruction; + break; case MISCREG_FPRS: - return new UnimpFault("FPU not implemented\n"); + //Configure the fpu based on the fprs + break; case MISCREG_PCR: - return new UnimpFault("Performance Instrumentation not impl\n"); - case MISCREG_PIC: - return new UnimpFault("Performance Instrumentation not impl\n"); - case MISCREG_GSR: - return setReg(miscReg, val); - - /** Privilged Registers */ - case MISCREG_TPC: - case MISCREG_TNPC: - case MISCREG_TSTATE: - case MISCREG_TT: - if (tl == 0) - return new IllegalInstruction; - setReg(miscReg, val); - return NoFault; - - case MISCREG_TBA: - // clear lower 7 bits on writes. - setReg(miscReg, val & ULL(~0x7FFF)); - return NoFault; - - case MISCREG_PSTATE: - setReg(miscReg, val); - return NoFault; - - case MISCREG_TL: - if (isHyperPriv() && val > MaxTL) - setReg(miscReg, MaxTL); - else if (isPriv() && !isHyperPriv() && val > MaxPTL) - setReg(miscReg, MaxPTL); - else - setReg(miscReg, val); - return NoFault; - + //Set up performance counting based on pcr value + break; case MISCREG_CWP: tc->changeRegFileContext(CONTEXT_CWP, val); - case MISCREG_CANSAVE: - case MISCREG_CANRESTORE: - case MISCREG_CLEANWIN: - case MISCREG_OTHERWIN: - case MISCREG_WSTATE: - setReg(miscReg, val); - return NoFault; - + break; case MISCREG_GL: - int newval; - if (isHyperPriv() && val > MaxGL) - newval = MaxGL; - else if (isPriv() && !isHyperPriv() && val > MaxPGL) - newval = MaxPGL; - else - newval = val; - tc->changeRegFileContext(CONTEXT_GLOBALS, newval); - setReg(miscReg, newval); - return NoFault; - - /** Floating Point Status Register */ - case MISCREG_FSR: - panic("Floating Point not implemented\n"); - default: -#if FULL_SYSTEM - setFSRegWithEffect(miscReg, val, tc); -#else - return new IllegalInstruction; -#endif + tc->changeRegFileContext(CONTEXT_GLOBALS, val); + break; } + setReg(miscReg, val); } void MiscRegFile::serialize(std::ostream & os) diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index be143311f..771cb1ed6 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -56,7 +56,6 @@ namespace SparcISA MISCREG_CCR = AsrStart + 2, MISCREG_ASI = AsrStart + 3, MISCREG_TICK = AsrStart + 4, - MISCREG_PC = AsrStart + 5, MISCREG_FPRS = AsrStart + 6, MISCREG_PCR = AsrStart + 16, MISCREG_PIC = AsrStart + 17, @@ -366,31 +365,13 @@ namespace SparcISA reset(); } - /** read a value out of an either an SE or FS IPR. No checking is done - * about SE vs. FS as this is mostly used to copy the regfile. Thus more - * register are copied that are necessary for FS. However this prevents - * a bunch of ifdefs and is rarely called so is not performance - * criticial. */ MiscReg readReg(int miscReg); - /** Read a value from an IPR. Only the SE iprs are here and the rest - * are are readFSRegWithEffect (which is called by readRegWithEffect()). - * Checking is done for permission based on state bits in the miscreg - * file. */ - MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); - - /** write a value into an either an SE or FS IPR. No checking is done - * about SE vs. FS as this is mostly used to copy the regfile. Thus more - * register are copied that are necessary for FS. However this prevents - * a bunch of ifdefs and is rarely called so is not performance - * criticial.*/ - Fault setReg(int miscReg, const MiscReg &val); - - /** Write a value into an IPR. Only the SE iprs are here and the rest - * are are setFSRegWithEffect (which is called by setRegWithEffect()). - * Checking is done for permission based on state bits in the miscreg - * file. */ - Fault setRegWithEffect(int miscReg, + MiscReg readRegWithEffect(int miscReg, ThreadContext *tc); + + void setReg(int miscReg, const MiscReg &val); + + void setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); void serialize(std::ostream & os); diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 3323ba7a0..a3b7dde7c 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -66,6 +66,10 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, // Set pointer for next thread stack. Reserve 8M for main stack. next_thread_stack_base = stack_base - (8 * 1024 * 1024); + + //Initialize these to 0s + fillStart = 0; + spillStart = 0; } void @@ -88,15 +92,19 @@ SparcLiveProcess::startup() */ //No windows contain info from other programs - threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); + threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0); //There are no windows to pop - threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); + threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0); //All windows are available to save into - threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); + threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2); //All windows are "clean" - threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); + threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows); //Start with register window 0 - threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); + threadContexts[0]->setMiscReg(MISCREG_CWP, 0); + //Always use spill and fill traps 0 + threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0); + //Set the trap level to 0 + threadContexts[0]->setMiscReg(MISCREG_TL, 0); } m5_auxv_t buildAuxVect(int64_t type, int64_t val) @@ -107,6 +115,83 @@ m5_auxv_t buildAuxVect(int64_t type, int64_t val) return result; } +//We only use 19 instructions for the trap handlers, but there would be +//space for 32 in a real SPARC trap table. +const int numFillInsts = 32; +const int numSpillInsts = 32; + +MachInst fillHandler[numFillInsts] = +{ + htog(0x87802018), //wr %g0, ASI_AIUP, %asi + htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0 + htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1 + htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2 + htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3 + htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4 + htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5 + htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6 + htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7 + htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0 + htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1 + htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2 + htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3 + htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4 + htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5 + htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6 + htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7 + htog(0x83880000), //restored + htog(0x83F00000), //retry + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000) //illtrap +}; + +MachInst spillHandler[numSpillInsts] = +{ + htog(0x87802018), //wr %g0, ASI_AIUP, %asi + htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi + htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi + htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi + htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi + htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi + htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi + htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi + htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi + htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi + htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi + htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi + htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi + htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi + htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi + htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi + htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi + htog(0x81880000), //saved + htog(0x83F00000), //retry + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000) //illtrap +}; + void SparcLiveProcess::argsInit(int intSize, int pageSize) { @@ -317,6 +402,17 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); + //Stuff the trap handlers into the processes address space. + //Since the stack grows down and is the highest area in the processes + //address space, we can put stuff above it and stay out of the way. + int fillSize = sizeof(MachInst) * numFillInsts; + int spillSize = sizeof(MachInst) * numSpillInsts; + fillStart = stack_base; + spillStart = fillStart + fillSize; + initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler, fillSize); + initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler, spillSize); + + //Set up the thread context to start running the process threadContexts[0]->setIntReg(ArgumentReg0, argc); threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh index 7cc52e241..2320810c7 100644 --- a/src/arch/sparc/process.hh +++ b/src/arch/sparc/process.hh @@ -55,6 +55,9 @@ class SparcLiveProcess : public LiveProcess static const Addr StackBias = 2047; + //The locations of the fill and spill handlers + Addr fillStart, spillStart; + std::vector<m5_auxv_t> auxv; SparcLiveProcess(const std::string &nm, ObjectFile *objFile, @@ -71,6 +74,12 @@ class SparcLiveProcess : public LiveProcess void argsInit(int intSize, int pageSize); + Addr readFillStart() + { return fillStart; } + + Addr readSpillStart() + { return spillStart; } + }; #endif // __SPARC_PROCESS_HH__ diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 747426781..5eb874d39 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -82,18 +82,21 @@ MiscReg RegFile::readMiscReg(int miscReg) MiscReg RegFile::readMiscRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, fault, tc); + fault = NoFault; + return miscRegFile.readRegWithEffect(miscReg, tc); } Fault RegFile::setMiscReg(int miscReg, const MiscReg &val) { - return miscRegFile.setReg(miscReg, val); + miscRegFile.setReg(miscReg, val); + return NoFault; } Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setRegWithEffect(miscReg, val, tc); + return NoFault; } FloatReg RegFile::readFloatReg(int floatReg, int width) diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh index 879780d56..177279678 100644 --- a/src/base/bitfield.hh +++ b/src/base/bitfield.hh @@ -69,4 +69,28 @@ sext(uint64_t val) return sign_bit ? (val | ~mask(N)) : val; } +/** + * Return val with bits first to last set to bit_val + */ +template <class T, class B> +inline +T +insertBits(T val, int first, int last, B bit_val) +{ + T bmask = mask(first - last + 1) << last; + return ((bit_val << last) & bmask) | (val & ~bmask); +} + +/** + * A convenience function to replace bits first to last of val with bit_val + * in place. + */ +template <class T, class B> +inline +void +replaceBits(T& val, int first, int last, B bit_val) +{ + val = insertBits(val, first, last, bit_val); +} + #endif // __BASE_BITFIELD_HH__ diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh index 8debd277d..992f55c6e 100644 --- a/src/cpu/ozone/back_end.hh +++ b/src/cpu/ozone/back_end.hh @@ -35,7 +35,7 @@ #include <queue> #include <string> -#include "arch/faults.hh" +#include "sim/faults.hh" #include "base/timebuf.hh" #include "cpu/inst_seq.hh" #include "cpu/ozone/rename_table.hh" diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 0a1e1c139..9d42ab05b 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -28,7 +28,7 @@ * Authors: Kevin Lim */ -#include "arch/faults.hh" +#include "sim/faults.hh" #include "config/full_system.hh" #include "cpu/ozone/dyn_inst.hh" #include "kern/kernel_stats.hh" diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 36e87ec9c..60c954517 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -30,7 +30,7 @@ #include "config/use_checker.hh" -#include "arch/faults.hh" +#include "sim/faults.hh" #include "arch/isa_traits.hh" #include "arch/utility.hh" #include "base/statistics.hh" diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index 76eef6fad..b2522bdc8 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -33,7 +33,7 @@ #include <list> -#include "arch/faults.hh" +#include "sim/faults.hh" #include "base/timebuf.hh" #include "cpu/thread_context.hh" #include "cpu/inst_seq.hh" diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 16ebac163..8aef9c074 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -28,7 +28,7 @@ * Authors: Kevin Lim */ -#include "arch/faults.hh" +#include "sim/faults.hh" #include "arch/types.hh" #include "cpu/ozone/inorder_back_end.hh" #include "cpu/ozone/thread_state.hh" diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh index 49c6a1ae2..08a6863d0 100644 --- a/src/cpu/ozone/lw_back_end.hh +++ b/src/cpu/ozone/lw_back_end.hh @@ -36,7 +36,7 @@ #include <set> #include <string> -#include "arch/faults.hh" +#include "sim/faults.hh" #include "base/timebuf.hh" #include "cpu/inst_seq.hh" #include "cpu/ozone/rename_table.hh" diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index c86f3552e..985e09b52 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -31,7 +31,7 @@ #ifndef __CPU_OZONE_THREAD_STATE_HH__ #define __CPU_OZONE_THREAD_STATE_HH__ -#include "arch/faults.hh" +#include "sim/faults.hh" #include "arch/types.hh" #include "arch/regfile.hh" #include "base/callback.hh" diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index edba55b0d..11e4d2acb 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -188,8 +188,11 @@ AtomicSimpleCPU::resume() changeState(SimObject::Running); if (thread->status() == ThreadContext::Active) { - if (!tickEvent.scheduled()) - tickEvent.schedule(curTick); + if (!tickEvent.scheduled()) { + Tick nextTick = curTick + cycles(1) - 1; + nextTick -= (nextTick % (cycles(1))); + tickEvent.schedule(nextTick); + } } } } @@ -217,7 +220,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) ThreadContext *tc = threadContexts[i]; if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; - tickEvent.schedule(curTick); + Tick nextTick = curTick + cycles(1) - 1; + nextTick -= (nextTick % (cycles(1))); + tickEvent.schedule(nextTick); break; } } @@ -234,7 +239,10 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) assert(!tickEvent.scheduled()); notIdleFraction++; - tickEvent.schedule(curTick + cycles(delay)); + //Make sure ticks are still on multiples of cycles + Tick nextTick = curTick + cycles(delay + 1) - 1; + nextTick -= (nextTick % (cycles(1))); + tickEvent.schedule(nextTick); _status = Running; } diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 21028fa63..9da46d74f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -91,6 +91,8 @@ uid=100 [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index f5be4e3bd..fc125a624 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index e87e77b8f..5c79f4d62 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2175 # Simulator instruction rate (inst/s) -host_mem_usage 147292 # Number of bytes of host memory used -host_seconds 2.06 # Real time elapsed on the host -host_tick_rate 2174 # Simulator tick rate (ticks/s) +host_inst_rate 58121 # Simulator instruction rate (inst/s) +host_mem_usage 148396 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 57840 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4483 # Number of instructions simulated +sim_insts 4863 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 4482 # Number of ticks simulated +sim_ticks 4862 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4483 # number of cpu cycles simulated -system.cpu.num_insts 4483 # Number of instructions executed -system.cpu.num_refs 965 # Number of memory references +system.cpu.numCycles 4863 # number of cpu cycles simulated +system.cpu.num_insts 4863 # Number of instructions executed +system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index c9df3a17c..1d76c6089 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:19:59 -M5 started Sun Oct 8 14:20:03 2006 +M5 compiled Oct 27 2006 02:07:29 +M5 started Fri Oct 27 02:08:08 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic -Exiting @ tick 4482 because target called exit() +command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic +Exiting @ tick 4862 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 982973385..da87d03a1 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -20,7 +20,6 @@ print_effaddr=true print_fetchseq=false print_iregs=false print_opclass=true -print_reg_delta=false print_thread=true speculative=true trace_system=client diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index c4dc22855..3645207b1 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 53689 # Simulator instruction rate (inst/s) -host_mem_usage 177104 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 17808084 # Simulator tick rate (ticks/s) +host_inst_rate 48159 # Simulator instruction rate (inst/s) +host_mem_usage 179620 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 15510230 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4483 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1497001 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 464 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3972.166667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2972.166667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 410 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214497 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.116379 # miss rate for ReadReq accesses +sim_insts 4863 # Number of instructions simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 1573001 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 160497 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.116379 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 501 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3980.840580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2980.840580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 432 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 274678 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.137725 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 69 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 205678 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.137725 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 69 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.845528 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 965 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3977.032520 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency -system.cpu.dcache.demand_hits 842 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 489175 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.127461 # miss rate for demand accesses -system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses +system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 366175 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.127461 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 123 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 965 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3977.032520 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 842 # number of overall hits -system.cpu.dcache.overall_miss_latency 489175 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.127461 # miss rate for overall accesses -system.cpu.dcache.overall_misses 123 # number of overall misses +system.cpu.dcache.overall_hits 1131 # number of overall hits +system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses +system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 366175 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.127461 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 123 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,56 +74,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 123 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 71.370810 # Cycle average of tags in use -system.cpu.dcache.total_refs 842 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use +system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4484 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3979.178571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.178571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4232 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1002753 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.056200 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 252 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 750753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.056200 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 252 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16.793651 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4484 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3979.178571 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency -system.cpu.icache.demand_hits 4232 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1002753 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.056200 # miss rate for demand accesses -system.cpu.icache.demand_misses 252 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency +system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses +system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 750753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.056200 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 252 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4484 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3979.178571 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4232 # number of overall hits -system.cpu.icache.overall_miss_latency 1002753 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.056200 # miss rate for overall accesses -system.cpu.icache.overall_misses 252 # number of overall misses +system.cpu.icache.overall_hits 4608 # number of overall hits +system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses +system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 750753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.056200 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 252 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -136,57 +136,57 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 252 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.914677 # Cycle average of tags in use -system.cpu.icache.total_refs 4232 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use +system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2986.473118 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1985.473118 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1110968 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.992000 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 372 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 738596 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.008065 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 375 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2986.473118 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1110968 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 372 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 738596 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 375 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2986.473118 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1110968 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 372 # number of overall misses +system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 738596 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 372 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,16 +199,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 372 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 185.896040 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1497001 # number of cpu cycles simulated -system.cpu.num_insts 4483 # Number of instructions executed -system.cpu.num_refs 965 # Number of memory references +system.cpu.numCycles 1573001 # number of cpu cycles simulated +system.cpu.num_insts 4863 # Number of instructions executed +system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 3c17ee40b..b1da2e4ab 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 23 2006 07:47:36 -M5 started Mon Oct 23 07:47:41 2006 -M5 executing on zeep +M5 compiled Oct 27 2006 02:07:29 +M5 started Fri Oct 27 02:08:11 2006 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing -Exiting @ tick 1497001 because target called exit() +Exiting @ tick 1573001 because target called exit() |