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-rw-r--r--src/arch/arm/isa/insts/misc64.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index cf82ea3e4..17d8df10d 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -177,7 +177,7 @@ let {{
hltCode = '''
ThreadContext *tc = xc->tcBase();
- if (ArmSystem::haveSemihosting(tc) && bits(machInst, 20, 5) == 0xF000) {
+ if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) {
X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1);
} else {
// HLT instructions aren't implemented, so treat them as undefined