diff options
26 files changed, 671 insertions, 250 deletions
@@ -29,13 +29,13 @@ Steven K. Reinhardt Ali G. Saidi ----------------------- +* SPARC Full System Support * Alpha Linux support * Alpha (Tsunami) platform and devices * I/O <-> memory interface * PCI device interface * Multiple ISA support * Memory bridge, bus, packet, port interfaces -* SPARC IPRs Kevin T. Lim ----------------------- diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 03eec3aab..eebe0eb57 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,3 +1,19 @@ +Apr. XX, 2007: m5_2.0_beta3 +-------------------- +New Features +1. Some support for SPARC full-system simulation + +Bug fixes since beta 2: +1. Many SPARC linux syscall emulation support fixes +2. Multiprocessor linux boot using the detailed O3 CPU module +3. Simulator performance and memory leak fixes +4. Fix issues with remote debugging +5. Many other minor fixes and enhancements + +Outstanding issues for 2.0 release: +-------------------- +1. ??? + Nov. 28, 2006: m5_2.0_beta2 -------------------- Bug fixes since beta 1: @@ -7,7 +23,7 @@ Bug fixes since beta 1: 4. Draining/Switchover 5. Functional Accesses 6. Bus now has real timing -7. Single config file fro all SpecCPU2000 benchmarks +7. Single config file for all SpecCPU2000 benchmarks 8. Several other minor bug fixes and enhancements Outstading issues for 2.0 release: diff --git a/src/SConscript b/src/SConscript index 5efd2f794..34c5453b7 100644 --- a/src/SConscript +++ b/src/SConscript @@ -30,28 +30,71 @@ import os import sys +import zipfile +from os.path import basename from os.path import join as joinpath +import SCons + # This file defines how to build a particular configuration of M5 # based on variable settings in the 'env' build environment. Import('*') +# Children need to see the environment +Export('env') + +######################################################################## +# Code for adding source files +# sources = [] -def Source(*args): - for arg in args: - if isinstance(arg, (list, tuple)): - # Recurse to load a list - Source(*arg) - elif isinstance(arg, str): - sources.extend([ File(f) for f in Split(arg) ]) - else: - sources.append(File(arg)) +def Source(source): + if isinstance(source, SCons.Node.FS.File): + sources.append(source) + else: + sources.append(File(source)) -Export('env') +# Children should have access Export('Source') +######################################################################## +# Code for adding python objects +# +py_sources = [] +py_source_packages = {} +def PySource(package, source): + if not isinstance(source, SCons.Node.FS.File): + source = File(source) + py_source_packages[source] = package + py_sources.append(source) + +sim_objects = [] +def SimObject(source): + if not isinstance(source, SCons.Node.FS.File): + source = File(source) + PySource('m5.objects', source) + modname = basename(str(source)) + sim_objects.append(modname) + +swig_sources = [] +swig_source_packages = {} +def SwigSource(package, source): + if not isinstance(source, SCons.Node.FS.File): + source = File(source) + swig_source_packages[source] = package + swig_sources.append(source) + +# Children should have access +Export('PySource') +Export('SimObject') +Export('SwigSource') + +######################################################################## +# +# Set some compiler variables +# + # Include file paths are rooted in this directory. SCons will # automatically expand '.' to refer to both the source directory and # the corresponding build directory to pick up generated include @@ -61,7 +104,9 @@ env.Append(CPPPATH=Dir('.')) # Add a flag defining what THE_ISA should be for all compilation env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())]) +######################################################################## # Walk the tree and execute all SConscripts +# scripts = [] srcdir = env['SRCDIR'] for root, dirs, files in os.walk(srcdir, topdown=True): @@ -78,6 +123,132 @@ for root, dirs, files in os.walk(srcdir, topdown=True): for opt in env.ExportOptions: env.ConfigFile(opt) +######################################################################## +# +# Deal with python/swig, object code. Collect .py files and +# generating a zip archive that is appended to the m5 binary. +# + +# Generate Python file that contains a dict specifying the current +# build_env flags. +def MakeDefinesPyFile(target, source, env): + f = file(str(target[0]), 'w') + print >>f, "m5_build_env = ", source[0] + f.close() + +optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions]) +env.Command('python/m5/defines.py', Value(optionDict), MakeDefinesPyFile) +PySource('m5', 'python/m5/defines.py') + +def MakeInfoPyFile(target, source, env): + f = file(str(target[0]), 'w') + for src in source: + data = ''.join(file(src.srcnode().abspath, 'r').xreadlines()) + print >>f, "%s = %s" % (src, repr(data)) + f.close() + +env.Command('python/m5/info.py', + [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], + MakeInfoPyFile) +PySource('m5', 'python/m5/info.py') + +def MakeObjectsInitFile(target, source, env): + f = file(str(target[0]), 'w') + print >>f, 'from m5.SimObject import *' + for src_path in source: + src_file = basename(src_path.get_contents()) + assert(src_file.endswith('.py')) + src_module = src_file[:-3] + print >>f, 'from %s import *' % src_module + f.close() + +env.Command('python/m5/objects/__init__.py', + [ Value(o) for o in sim_objects], + MakeObjectsInitFile) +PySource('m5.objects', 'python/m5/objects/__init__.py') + +swig_modules = [] +for source in swig_sources: + source.rfile() # Hack to cause the symlink to the .i file to be created + package = swig_source_packages[source] + filename = str(source) + module = basename(filename) + + assert(module.endswith('.i')) + module = module[:-2] + cc_file = 'swig/%s_wrap.cc' % module + py_file = 'm5/internal/%s.py' % module + + env.Command([cc_file, py_file], source, + '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' + '-o ${TARGETS[0]} $SOURCES') + env.Depends(py_file, source) + env.Depends(cc_file, source) + + swig_modules.append(Value(module)) + Source(cc_file) + PySource(package, py_file) + +def MakeSwigInit(target, source, env): + f = file(str(target[0]), 'w') + print >>f, 'extern "C" {' + for module in source: + print >>f, ' void init_%s();' % module.get_contents() + print >>f, '}' + print >>f, 'void init_swig() {' + for module in source: + print >>f, ' init_%s();' % module.get_contents() + print >>f, '}' + f.close() +env.Command('python/swig/init.cc', swig_modules, MakeSwigInit) + +def CompilePyFile(target, source, env): + import py_compile + py_compile.compile(str(source[0]), str(target[0])) + +py_compiled = [] +py_arcname = {} +py_zip_depends = [] +for source in py_sources: + filename = str(source) + package = py_source_packages[source] + arc_path = package.split('.') + [ basename(filename) + 'c' ] + zip_path = [ 'zip' ] + arc_path + arcname = joinpath(*arc_path) + zipname = joinpath(*zip_path) + f = File(zipname) + + env.Command(f, source, CompilePyFile) + py_compiled.append(f) + py_arcname[f] = arcname + + # make the zipfile depend on the archive name so that the archive + # is rebuilt if the name changes + py_zip_depends.append(Value(arcname)) + +# Action function to build the zip archive. Uses the PyZipFile module +# included in the standard Python library. +def buildPyZip(target, source, env): + zf = zipfile.ZipFile(str(target[0]), 'w') + for s in source: + arcname = py_arcname[s] + zipname = str(s) + zf.write(zipname, arcname) + zf.close() + +# Add the zip file target to the environment. +env.Command('m5py.zip', py_compiled, buildPyZip) +env.Depends('m5py.zip', py_zip_depends) + +######################################################################## +# +# Define binaries. Each different build type (debug, opt, etc.) gets +# a slightly different build environment. +# + +# List of constructed environments to pass back to SConstruct +envList = [] + # This function adds the specified sources to the given build # environment, and returns a list of all the corresponding SCons # Object nodes (including an extra one for date.cc). We explicitly @@ -92,16 +263,6 @@ def make_objs(sources, env): objs.append(date_obj) return objs -################################################### -# -# Define binaries. Each different build type (debug, opt, etc.) gets -# a slightly different build environment. -# -################################################### - -# List of constructed environments to pass back to SConstruct -envList = [] - # Function to create a new build environment as clone of current # environment 'env' with modified object suffix and optional stripped # binary. Additional keyword arguments are appended to corresponding @@ -120,7 +281,7 @@ def makeEnv(label, objsfx, strip = False, **kwargs): else: newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET') bin = stripped_bin - targets = newEnv.Concat(exe, [bin, 'python/m5py.zip']) + targets = newEnv.Concat(exe, [bin, 'm5py.zip']) newEnv.M5Binary = targets[0] envList.append(newEnv) diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index bba63f407..4339003e0 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -154,6 +154,76 @@ def template ROrImmDecode {{ } }}; +output header {{ + union DoubleSingle + { + double d; + uint64_t ui; + uint32_t s[2]; + DoubleSingle(double _d) : d(_d) + {} + DoubleSingle(uint64_t _ui) : ui(_ui) + {} + DoubleSingle(uint32_t _s0, uint32_t _s1) + { + s[0] = _s0; + s[1] = _s1; + } + }; +}}; + +let {{ + def filterDoubles(code): + assignRE = re.compile(r'\s*=(?!=)', re.MULTILINE) + for opName in ("Frd", "Frs1", "Frs2", "Frd_N"): + next_pos = 0 + operandsREString = (r''' + (?<![\w\.]) # neg. lookbehind assertion: prevent partial matches + ((%s)(?:\.(\w+))?) # match: operand with optional '.' then suffix + (?![\w\.]) # neg. lookahead assertion: prevent partial matches + ''' % opName) + operandsRE = re.compile(operandsREString, re.MULTILINE|re.VERBOSE) + is_src = False + is_dest = False + extension = None + foundOne = False + while 1: + match = operandsRE.search(code, next_pos) + if not match: + break + foundOne = True + op = match.groups() + (op_full, op_base, op_ext) = op + is_dest_local = (assignRE.match(code, match.end()) != None) + is_dest = is_dest or is_dest_local + is_src = is_src or not is_dest_local + if extension and extension != op_ext: + raise Exception, "Inconsistent extensions in double filter." + extension = op_ext + next_pos = match.end() + if foundOne: + # Get rid of any unwanted extension + code = operandsRE.sub(op_base, code) + is_int = False + member = "d" + if extension in ("sb", "ub", "shw", "uhw", "sw", "uw", "sdw", "udw"): + is_int = True + member = "ui" + if is_src: + code = ("%s = DoubleSingle(%s_high, %s_low).%s;" % \ + (opName, opName, opName, member)) + code + if is_dest: + code += ''' + %s_low = DoubleSingle(%s).s[1]; + %s_high = DoubleSingle(%s).s[0];''' % \ + (opName, opName, opName, opName) + if is_int: + code = ("uint64_t %s;" % opName) + code + else: + code = ("double %s;" % opName) + code + return code +}}; + let {{ def splitOutImm(code): matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?') diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 017f43780..7665d2d4f 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -97,6 +97,7 @@ def template BasicDecodeWithMnemonic {{ // The most basic instruction format... used only for a few misc. insts def format BasicOperate(code, *flags) {{ + code = filterDoubles(code) iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) @@ -140,6 +141,7 @@ def format FpBasic(code, *flags) {{ fesetround(oldrnd); #endif """ + fp_code = filterDoubles(fp_code) iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index 751262811..2f62c7bef 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -71,6 +71,7 @@ let {{ }}; def format LoadAlt(code, asi, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, @@ -79,6 +80,7 @@ def format LoadAlt(code, asi, *opt_flags) {{ }}; def format StoreAlt(code, asi, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, @@ -87,6 +89,7 @@ def format StoreAlt(code, asi, *opt_flags) {{ }}; def format Load(code, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, @@ -95,6 +98,7 @@ def format Load(code, *opt_flags) {{ }}; def format Store(code, *opt_flags) {{ + code = filterDoubles(code) (header_output, decoder_output, exec_output, diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 499685a5c..e19016bd0 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -317,6 +317,7 @@ let {{ }}; def format BlockLoad(code, asi, *opt_flags) {{ + code = filterDoubles(code) # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten # rather than the other way around. @@ -329,6 +330,7 @@ def format BlockLoad(code, asi, *opt_flags) {{ }}; def format BlockStore(code, asi, *opt_flags) {{ + code = filterDoubles(code) # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten # rather than the other way around. diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index 82d7fb4cb..da0f97d1b 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -26,6 +26,33 @@ // // Authors: Gabe Black +//This delcares the initiateAcc function in memory operations +def template MacroInitiateAcc {{ + Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + return NoFault; + } +}}; + +def template MacroCompleteAcc {{ + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, + Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + return NoFault; + } +}}; + +//This template provides the execute functions for a store +def template MacroExecute {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + return NoFault; + } +}}; + output header {{ class SparcMacroInst : public SparcStaticInst @@ -60,7 +87,9 @@ output header {{ return microOps[microPC]; } - %(BasicExecPanic)s + %(MacroExecute)s + %(MacroInitiateAcc)s + %(MacroCompleteAcc)s }; class SparcMicroInst : public SparcStaticInst diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 038919bd1..58d616a7a 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -52,6 +52,16 @@ output header {{ { return (regNum & (~1)) | ((regNum & 1) << 5); } + + static inline unsigned int dfprl(unsigned int regNum) + { + return dfpr(regNum) & (~0x1); + } + + static inline unsigned int dfprh(unsigned int regNum) + { + return dfpr(regNum) | 0x1; + } }}; def operands {{ @@ -79,21 +89,43 @@ def operands {{ # differently, they get different operands. The single precision versions # have an s post pended to their name. 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), - 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), + #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), + 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), + 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), # Each Frd_N refers to the Nth double precision register from Frd. # Note that this adds twice N to the register number. - 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), - 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), - 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), - 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), - 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), - 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), - 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), - 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), + #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), + 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), + 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), + #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), + 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), + 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), + #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), + 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), + 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), + #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), + 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), + 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), + #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), + 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), + 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), + #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), + 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), + 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), + #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), + 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), + 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), + #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), + 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), + 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), - 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), + #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), + 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), + 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), - 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), + #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), + 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), + 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), # Registers which are used explicitly in instructions diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index 6d89c273a..8c9afcdb5 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -65,12 +65,32 @@ namespace X86ISA { class X86Fault : public FaultBase { + protected: + const char * name() + { + return "generic_x86_fault"; + } + void invoke(ThreadContext * tc) { panic("X86 faults are not implemented!"); } }; + class UnimpInstFault : public FaultBase + { + public: + const char * name() + { + return "unimplemented_micro"; + } + + void invoke(ThreadContext * tc) + { + panic("Unimplemented instruction!"); + } + }; + static inline Fault genPageTableFault(Addr va) { panic("Page table fault not implemented in x86!\n"); diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa index cd166b306..eba24f709 100644 --- a/src/arch/x86/isa/base.isa +++ b/src/arch/x86/isa/base.isa @@ -58,6 +58,38 @@ // Base class for sparc instructions, and some support functions // +let {{ + # This class will help make dealing with output a little less verbose + class OutputBlocks(object): + def __init__(self, header_output="", + decoder_output="", + decode_block="", + exec_output=""): + self.header_output = header_output + self.decoder_output = decoder_output + self.decode_block = decode_block + self.exec_output = exec_output + + def append(self, blocks): + if isinstance(blocks, list) or isinstance(blocks, tuple): + assert(len(blocks) == 4) + self.header_output += blocks[0] + self.decoder_output += blocks[1] + self.decode_block += blocks[2] + self.exec_output += blocks[3] + else: + self.header_output += blocks.header_output + self.decoder_output += blocks.decoder_output + self.decode_block += blocks.decode_block + self.exec_output += blocks.exec_output + + def makeList(self): + return (self.header_output, + self.decoder_output, + self.decode_block, + self.exec_output) +}}; + output header {{ /** diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index fed6dda28..4e044363b 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -61,11 +61,11 @@ 0x1: decode OPCODE_OP_TOP5 { format WarnUnimpl { 0x00: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::add(rAl,Ib); - 0x5: Inst::add(rAx,Iz); + 0x4: Inst::ADD(rAl,Ib); + 0x5: Inst::ADD(rAx,Iz); 0x6: push_ES(); 0x7: pop_ES(); - default: MultiInst::add(OPCODE_OP_BOTTOM3, + default: MultiInst::ADD(OPCODE_OP_BOTTOM3, [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); } 0x01: decode OPCODE_OP_BOTTOM3 { @@ -123,12 +123,12 @@ 0x7: das(); } 0x06: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::xor(rAl,Ib); - 0x5: Inst::xor(rAx,Iz); + 0x4: Inst::XOR(rAl,Ib); + 0x5: Inst::XOR(rAx,Iz); 0x6: M5InternalError::error( {{"Tried to execute the SS segment override prefix!"}}); 0x7: aaa(); - default: MultiInst::xor(OPCODE_OP_BOTTOM3, + default: MultiInst::XOR(OPCODE_OP_BOTTOM3, [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); } 0x07: decode OPCODE_OP_BOTTOM3 { @@ -237,11 +237,11 @@ 0x7: xchg_Ev_Gv(); } 0x11: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_Eb_Gb(); - 0x1: mov_Ev_Gv(); - 0x2: mov_Gb_Eb(); - 0x3: mov_Gv_Ev(); - 0x4: mov_MwRv_Sw(); + 0x0: Inst::MOV(); //mov_Eb_Gb(); + 0x1: Inst::MOV(); //mov_Ev_Gv(); + 0x2: Inst::MOV(); //mov_Gb_Eb(); + 0x3: Inst::MOV(); //mov_Gv_Ev(); + 0x4: Inst::MOV(); //mov_MwRv_Sw(); 0x5: lea_Gv_M(); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 7ad5ecd48..8f91c249c 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -72,7 +72,7 @@ def format Inst(*opTypeSet) {{ (header_output, decoder_output, decode_block, - exec_output) = doInst(name, Name, list(opTypeSet)) + exce_output) = doInst(name, Name, list(opTypeSet)).makeList() }}; def format MultiInst(switchVal, *opTypeSets) {{ @@ -82,5 +82,5 @@ def format MultiInst(switchVal, *opTypeSets) {{ (header_output, decoder_output, decode_block, - exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher) + exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList() }}; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 7d41a2dea..663ec7aee 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -55,26 +55,30 @@ // // Authors: Gabe Black +////////////////////////////////////////////////////////////////////////////// +// +// Architecture independent +// + // Execute method for macroops. def template MacroExecPanic {{ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const { panic("Tried to execute macroop directly!"); - M5_DUMMY_RETURN + return NoFault; } }}; output header {{ - // Base class for most macroops, except ones that need to commit as - // they go. - class X86MacroInst : public StaticInst + // Base class for macroops + class MacroOp : public StaticInst { protected: const uint32_t numMicroOps; //Constructor. - X86MacroInst(const char *mnem, ExtMachInst _machInst, + MacroOp(const char *mnem, ExtMachInst _machInst, uint32_t _numMicroOps) : StaticInst(mnem, _machInst, No_OpClass), numMicroOps(_numMicroOps) @@ -84,7 +88,7 @@ output header {{ flags[IsMacroOp] = true; } - ~X86MacroInst() + ~MacroOp() { delete [] microOps; } @@ -97,10 +101,29 @@ output header {{ return microOps[microPC]; } + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + return mnemonic; + } + %(MacroExecPanic)s }; }}; +// Basic instruction class declaration template. +def template MacroDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(ExtMachInst machInst); + }; +}}; + // Basic instruction class constructor template. def template MacroConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) @@ -113,23 +136,27 @@ def template MacroConstructor {{ } }}; +////////////////////////////////////////////////////////////////////////////// +// +// X86 specific +// + let {{ def genMacroOp(name, Name, opSeq): - baseClass = 'X86MacroInst' - numMicroOps = len(opSeq.ops) + numMicroOps = len(opSeq) allocMicroOps = '' micropc = 0 - for op in opSeq.ops: + for op in opSeq: allocMicroOps += \ "microOps[%d] = %s;\n" % \ - (micropc, op.getAllocator(True, op.delayed, + (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed, micropc == 0, micropc == numMicroOps - 1)) micropc += 1 - iop = InstObjParams(name, Name, baseClass, + iop = InstObjParams(name, Name, 'MacroOp', {'code' : '', 'num_micro_ops' : numMicroOps, 'alloc_micro_ops' : allocMicroOps}) - header_output = BasicDeclare.subst(iop) + header_output = MacroDeclare.subst(iop) decoder_output = MacroConstructor.subst(iop) decode_block = BasicDecode.subst(iop) exec_output = '' diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 23567aae9..9d21b6bcc 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -85,7 +85,7 @@ let {{ text += ", false" return text - def getAllocator(self, *microFlags): + def getAllocator(self, mnemonic, *microFlags): args = '' signature = "<" emptySig = True @@ -104,7 +104,7 @@ let {{ else: raise Exception, "Unrecognized operand type." signature += ">" - return 'new %s%s(machInst%s%s)' % (self.className, signature, self.microFlagsText(microFlags), args) + return 'new %s%s(machInst, %s%s%s)' % (self.className, signature, mnemonic, self.microFlagsText(microFlags), args) }}; let{{ @@ -123,7 +123,7 @@ let{{ # the beginning of the line, so the previous component is stripped # before continuing. labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:') - lineRe = re.compile(r'^(?P<line>[^\n][^\n]*)$') + lineRe = re.compile(r'^(?P<line>..*)(\n|$)') classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)') # This recognizes three different flavors of operands: # 1. Raw decimal numbers composed of digits between 0 and 9 @@ -145,14 +145,14 @@ let{{ # Get a line and seperate it from the rest of the code line = lineMatch.group("line") orig_line = line - # print "Parsing line %s" % line + #print "Parsing line %s" % line code = lineRe.sub('', code, 1) # Find the label, if any labelMatch = labelRe.search(line) if labelMatch != None: statement.label = labelMatch.group("label") - # print "Found label %s." % statement.label + #print "Found label %s." % statement.label # Clear the label from the statement line = labelRe.sub('', line, 1) @@ -163,7 +163,7 @@ let{{ % orig_line else: statement.className = classMatch.group("className") - # print "Found class name %s." % statement.className + #print "Found class name %s." % statement.className # Clear the class name from the statement line = classRe.sub('', line, 1) @@ -185,9 +185,9 @@ let{{ print "Problem parsing operand in statement: %s" \ % orig_line line = opRe.sub('', line, 1) - # print "Found operand %s." % statement.args[-1] + #print "Found operand %s." % statement.args[-1] opMatch = opRe.search(line) - # print "Found operands", statement.args + #print "Found operands", statement.args # Add this statement to our collection statements.append(statement) @@ -215,11 +215,14 @@ let{{ arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1 micropc += 1 + if len(statements) == 0: + raise Exception, "Didn't find any microops in microcode: \n%s" % orig_code + # If we can implement this instruction with exactly one microop, just # use that directly. if len(statements) == 1: decode_block = "return %s;" % \ - statements[0].getAllocator() + statements[0].getAllocator('"' + name + '"') return ('', '', decode_block, '') else: # Build a macroop to contain the sequence of microops we've diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 4254994f3..f0aab7872 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -69,20 +69,33 @@ output header {{ class X86MicroOpBase : public X86StaticInst { protected: + const char * instMnem; uint8_t opSize; uint8_t addrSize; - X86MicroOpBase(bool isMicro, bool isDelayed, + X86MicroOpBase(ExtMachInst _machInst, + const char *mnem, const char *_instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, - const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - X86StaticInst(mnem, _machInst, __opClass) + X86StaticInst(mnem, _machInst, __opClass), + instMnem(_instMnem) { flags[IsMicroOp] = isMicro; flags[IsDelayedCommit] = isDelayed; flags[IsFirstMicroOp] = isFirst; flags[IsLastMicroOp] = isLast; } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "\t%s.%s", instMnem, mnemonic); + + return ss.str(); + } }; }}; @@ -127,7 +140,7 @@ let {{ }}; // A tmeplate for building a specialized version of the microcode -// instruction which knows specifies which arguments it wants +// instruction which specifies which arguments it wants def template MicroOpDeclare {{ template<> class %(class_name)s%(signature)s : public X86MicroOpBase @@ -137,11 +150,15 @@ def template MicroOpDeclare {{ void buildMe(); public: - %(class_name)s(bool isMicro, bool isDelayed, - bool isFirst, bool isLast, - ExtMachInst _machInst %(param_arg_dec)s); + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast + %(param_arg_dec)s); - %(class_name)s(ExtMachInst _machInst %(param_arg_dec)s); + %(class_name)s(ExtMachInst _machInst, + const char * instMnem + %(param_arg_dec)s); %(BasicExecDeclare)s }; @@ -155,19 +172,21 @@ def template MicroOpConstructor {{ } inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst %(param_arg_dec)s) : - %(base_class)s(false, false, false, false, - "%(mnemonic)s", machInst, %(op_class)s) + ExtMachInst machInst, const char * instMnem + %(param_arg_dec)s) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s) %(param_init)s { buildMe(); } inline %(class_name)s%(signature)s::%(class_name)s( - bool isMicro, bool isDelayed, bool isFirst, bool isLast, - ExtMachInst machInst %(param_arg_dec)s) - : %(base_class)s(isMicro, isDelayed, isFirst, isLast, - "%(mnemonic)s", machInst, %(op_class)s) + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast + %(param_arg_dec)s) + : %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s) %(param_init)s { buildMe(); diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa index bb136fc81..d877152eb 100644 --- a/src/arch/x86/isa/microops/microops.isa +++ b/src/arch/x86/isa/microops/microops.isa @@ -56,5 +56,8 @@ //Common microop stuff ##include "base.isa" +//A microop that generates a specified fault +##include "fault.isa" + //Integer microop definitions ##include "int.isa" diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index 9cac09770..ff92c3551 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -67,30 +67,18 @@ let {{ # builder is called on the exploded contents of "vals" values to generate # whatever code should be used. def doSplitDecode(name, Name, builder, switchVal, vals, default = None): - header_output = '' - decoder_output = '' - decode_block = 'switch(%s) {\n' % switchVal - exec_output = '' + blocks = OutputBlocks() + blocks.decode_block += 'switch(%s) {\n' % switchVal for (val, todo) in vals.items(): - (new_header_output, - new_decoder_output, - new_decode_block, - new_exec_output) = builder(name, Name, *todo) - header_output += new_header_output - decoder_output += new_decoder_output - decode_block += '\tcase %s: %s\n' % (val, new_decode_block) - exec_output += new_exec_output + built = builder(name, Name, *todo) + built.decode_block = '\tcase %s: %s\n' % (val, built.decode_block) + blocks.append(built) if default: - (new_header_output, - new_decoder_output, - new_decode_block, - new_exec_output) = builder(name, Name, *default) - header_output += new_header_output - decoder_output += new_decoder_output - decode_block += '\tdefault: %s\n' % new_decode_block - exec_output += new_exec_output - decode_block += '}\n' - return (header_output, decoder_output, decode_block, exec_output) + built = builder(name, Name, *default) + built.decode_block = '\tdefault: %s\n' % built.decode_block + blocks.append(built) + blocks.decode_block += '}\n' + return blocks }}; let {{ @@ -143,6 +131,7 @@ let {{ # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. + code = "GenFault ${new UnimpInstFault}\n" + code memCode = opRe.sub("%0", code) memTypes = copy.copy(opTypes) memTypes.pop(-1) @@ -156,6 +145,7 @@ let {{ # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. + code = "GenFault ${new UnimpInstFault}\n" + code code = opRe.sub("%0", code) elif opType.tag in ("PR", "R", "VR"): # There should probably be a check here to verify that mod @@ -168,5 +158,7 @@ let {{ # At this point, we've built up "code" to have all the necessary extra # instructions needed to implement whatever types of operands were # specified. Now we'll assemble it it into a StaticInst. - return assembleMicro(name, Name, code) + blocks = OutputBlocks() + blocks.append(assembleMicro(name, Name, code)) + return blocks }}; diff --git a/src/base/SConscript b/src/base/SConscript index 6fc140145..5e4aaafc2 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -97,3 +97,5 @@ Source('stats/visit.cc') if env['USE_MYSQL']: Source('mysql.cc') Source('stats/mysql.cc') + +PySource('m5', 'traceflags.py') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index c568b1439..3e2b0f03e 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -652,7 +652,7 @@ Trace::InstRecord::dump() predecoder.setTC(thread); predecoder.moreBytes(m5Pc, 0, shared_data->instruction); - assert(predecoder.extMachInstRead()); + assert(predecoder.extMachInstReady()); StaticInstPtr legionInst = StaticInst::decode(predecoder.getExtMachInst()); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 6f69b5ac4..b0a01c3a3 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -557,7 +557,7 @@ AtomicSimpleCPU::tick() } } - if(predecoder.needMoreBytes()) + if(predecoder.needMoreBytes() || fault != NoFault) advancePC(fault); } diff --git a/src/python/SConscript b/src/python/SConscript index 6662c8a45..e1095eabe 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -30,129 +30,91 @@ # Nathan Binkert import os -import zipfile - -# handy function for path joins -def join(*args): - return os.path.normpath(os.path.join(*args)) - Import('*') -# This SConscript is in charge of collecting .py files and generating -# a zip archive that is appended to the m5 binary. - -# List of files & directories to include in the zip file. To include -# a package, list only the root directory of the package, not any -# internal .py files (else they will get the path stripped off when -# they are imported into the zip file). -pyzip_files = [] - -# List of additional files on which the zip archive depends, but which -# are not included in pyzip_files... i.e. individual .py files within -# a package. -pyzip_dep_files = [] - -# Add the specified package to the zip archive. Adds the directory to -# pyzip_files and all included .py files to pyzip_dep_files. -def addPkg(pkgdir): - pyzip_files.append(pkgdir) - origdir = os.getcwd() - srcdir = join(Dir('.').srcnode().abspath, pkgdir) - os.chdir(srcdir) - for path, dirs, files in os.walk('.'): - for i,dir in enumerate(dirs): - if dir == 'SCCS': - del dirs[i] - break - - for f in files: - if f.endswith('.py'): - pyzip_dep_files.append(join(pkgdir, path, f)) - - os.chdir(origdir) - -# Generate Python file that contains a dict specifying the current -# build_env flags. -def MakeDefinesPyFile(target, source, env): - f = file(str(target[0]), 'w') - print >>f, "m5_build_env = ", source[0] - f.close() - -optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions]) -env.Command('m5/defines.py', Value(optionDict), MakeDefinesPyFile) - -def MakeInfoPyFile(target, source, env): - f = file(str(target[0]), 'w') - for src in source: - data = ''.join(file(src.srcnode().abspath, 'r').xreadlines()) - print >>f, "%s = %s" % (src, repr(data)) - f.close() - -env.Command('m5/info.py', - [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], - MakeInfoPyFile) - -# Now specify the packages & files for the zip archive. -addPkg('m5') -pyzip_files.append('m5/defines.py') -pyzip_files.append('m5/info.py') -pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py')) -pyzip_files.append(join(env['ROOT'], 'src/base/traceflags.py')) - -swig_modules = [] -def swig_it(module): - env.Command(['swig/%s_wrap.cc' % module, 'm5/internal/%s.py' % module], - 'swig/%s.i' % module, - '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' - '-o ${TARGETS[0]} $SOURCES') - swig_modules.append(module) - Source('swig/%s_wrap.cc' % module) - Source('swig/init.cc') Source('swig/pyevent.cc') Source('swig/pyobject.cc') -swig_it('core') -swig_it('debug') -swig_it('event') -swig_it('random') -swig_it('sim_object') -swig_it('stats') -swig_it('trace') - -# Automatically generate m5/internals/__init__.py -def MakeInternalsInit(target, source, env): - f = file(str(target[0]), 'w') - for m in swig_modules: - print >>f, 'import %s' % m - f.close() - -swig_py_files = [ 'm5/internal/%s.py' % m for m in swig_modules ] -env.Command('m5/internal/__init__.py', swig_py_files, MakeInternalsInit) -pyzip_dep_files.append('m5/internal/__init__.py') - -def MakeSwigInit(target, source, env): - f = file(str(target[0]), 'w') - print >>f, 'extern "C" {' - for m in swig_modules: - print >>f, ' void init_%s();' % m - print >>f, '}' - print >>f, 'void init_swig() {' - for m in swig_modules: - print >>f, ' init_%s();' % m - print >>f, '}' - f.close() - -swig_cc_files = [ 'swig/%s_wrap.cc' % m for m in swig_modules ] -env.Command('swig/init.cc', swig_cc_files, MakeSwigInit) - -# Action function to build the zip archive. Uses the PyZipFile module -# included in the standard Python library. -def buildPyZip(target, source, env): - pzf = zipfile.PyZipFile(str(target[0]), 'w') - for s in source: - pzf.writepy(str(s)) - -# Add the zip file target to the environment. -env.Command('m5py.zip', pyzip_files, buildPyZip) -env.Depends('m5py.zip', pyzip_dep_files) +PySource('m5', 'm5/__init__.py') +PySource('m5', 'm5/SimObject.py') +PySource('m5', 'm5/attrdict.py') +PySource('m5', 'm5/convert.py') +PySource('m5', 'm5/event.py') +PySource('m5', 'm5/main.py') +PySource('m5', 'm5/multidict.py') +PySource('m5', 'm5/params.py') +PySource('m5', 'm5/proxy.py') +PySource('m5', 'm5/smartdict.py') +PySource('m5', 'm5/stats.py') +PySource('m5', 'm5/ticks.py') +PySource('m5', 'm5/util.py') + +PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py')) + +SwigSource('m5.internal', 'swig/core.i') +SwigSource('m5.internal', 'swig/debug.i') +SwigSource('m5.internal', 'swig/event.i') +SwigSource('m5.internal', 'swig/random.i') +SwigSource('m5.internal', 'swig/sim_object.i') +SwigSource('m5.internal', 'swig/stats.i') +SwigSource('m5.internal', 'swig/trace.i') +PySource('m5.internal', 'm5/internal/__init__.py') + +SimObject('m5/objects/AlphaConsole.py') +SimObject('m5/objects/AlphaTLB.py') +SimObject('m5/objects/BadDevice.py') +SimObject('m5/objects/BaseCPU.py') +SimObject('m5/objects/BaseCache.py') +SimObject('m5/objects/BaseHier.py') +SimObject('m5/objects/BaseMem.py') +SimObject('m5/objects/BaseMemory.py') +SimObject('m5/objects/BranchPred.py') +SimObject('m5/objects/Bridge.py') +SimObject('m5/objects/Bus.py') +SimObject('m5/objects/Checker.py') +SimObject('m5/objects/CoherenceProtocol.py') +SimObject('m5/objects/DRAMMemory.py') +SimObject('m5/objects/Device.py') +SimObject('m5/objects/DiskImage.py') +SimObject('m5/objects/Ethernet.py') +SimObject('m5/objects/FUPool.py') +SimObject('m5/objects/FastCPU.py') +#SimObject('m5/objects/FreebsdSystem.py') +SimObject('m5/objects/FullCPU.py') +SimObject('m5/objects/FuncUnit.py') +SimObject('m5/objects/FuncUnitConfig.py') +SimObject('m5/objects/FunctionalMemory.py') +SimObject('m5/objects/HierParams.py') +SimObject('m5/objects/Ide.py') +SimObject('m5/objects/IntrControl.py') +SimObject('m5/objects/LinuxSystem.py') +SimObject('m5/objects/MainMemory.py') +SimObject('m5/objects/MemObject.py') +SimObject('m5/objects/MemTest.py') +SimObject('m5/objects/MemoryController.py') +SimObject('m5/objects/O3CPU.py') +SimObject('m5/objects/OzoneCPU.py') +SimObject('m5/objects/Pci.py') +SimObject('m5/objects/PhysicalMemory.py') +SimObject('m5/objects/PipeTrace.py') +SimObject('m5/objects/Platform.py') +SimObject('m5/objects/Process.py') +SimObject('m5/objects/Repl.py') +SimObject('m5/objects/Root.py') +SimObject('m5/objects/Sampler.py') +SimObject('m5/objects/Scsi.py') +SimObject('m5/objects/SimConsole.py') +SimObject('m5/objects/SimpleCPU.py') +SimObject('m5/objects/SimpleDisk.py') +#SimObject('m5/objects/SimpleOzoneCPU.py') +SimObject('m5/objects/SparcTLB.py') +SimObject('m5/objects/System.py') +SimObject('m5/objects/T1000.py') +#SimObject('m5/objects/Tru64System.py') +SimObject('m5/objects/Tsunami.py') +SimObject('m5/objects/Uart.py') + +if env['ALPHA_TLASER']: + SimObject('m5/objects/DmaEngine.py') + SimObject('m5/objects/Turbolaser.py') diff --git a/src/python/m5/internal/__init__.py b/src/python/m5/internal/__init__.py new file mode 100644 index 000000000..6b7859cd7 --- /dev/null +++ b/src/python/m5/internal/__init__.py @@ -0,0 +1,35 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import core +import debug +import event +import random +import sim_object +import stats +import trace diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 9892df97c..da7ddd65e 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -51,6 +51,7 @@ import sys import time import convert +import proxy import ticks from util import * @@ -477,12 +478,13 @@ def IncEthernetAddr(addr, val = 1): assert(bytes[0] <= 255) return ':'.join(map(lambda x: '%02x' % x, bytes)) -class NextEthernetAddr(object): - addr = "00:90:00:00:00:01" +_NextEthernetAddr = "00:90:00:00:00:01" +def NextEthernetAddr(): + global _NextEthernetAddr - def __init__(self, inc = 1): - self.value = NextEthernetAddr.addr - NextEthernetAddr.addr = IncEthernetAddr(NextEthernetAddr.addr, inc) + value = _NextEthernetAddr + _NextEthernetAddr = IncEthernetAddr(_NextEthernetAddr, 1) + return value class EthernetAddr(ParamValue): cxx_type = 'Net::EthAddr' @@ -508,17 +510,11 @@ class EthernetAddr(ParamValue): def unproxy(self, base): if self.value == NextEthernetAddr: - self.addr = self.value().value + return EthernetAddr(self.value()) return self - def __str__(self): - if self.value == NextEthernetAddr: - if hasattr(self, 'addr'): - return self.addr - else: - return "NextEthernetAddr (unresolved)" - else: - return self.value + def ini_str(self): + return self.value time_formats = [ "%a %b %d %H:%M:%S %Z %Y", "%a %b %d %H:%M:%S %Z %Y", @@ -1028,6 +1024,5 @@ __all__ = ['Param', 'VectorParam', # see comment on imports at end of __init__.py. from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass -import proxy import objects import internal diff --git a/src/sim/process.cc b/src/sim/process.cc index 2b283c9d1..68239fa52 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -157,12 +157,12 @@ Process::registerThreadContext(ThreadContext *tc) int myIndex = threadContexts.size(); threadContexts.push_back(tc); - RemoteGDB *rgdb = new RemoteGDB(system, tc); - GDBListener *gdbl = new GDBListener(rgdb, 7000 + myIndex); - gdbl->listen(); +// RemoteGDB *rgdb = new RemoteGDB(system, tc); +// GDBListener *gdbl = new GDBListener(rgdb, 7000 + myIndex); +// gdbl->listen(); //gdbl->accept(); - remoteGDB.push_back(rgdb); +// remoteGDB.push_back(rgdb); // return CPU number to caller return myIndex; diff --git a/util/make_release.py b/util/make_release.py index f07bafe3b..8d69614dc 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -127,6 +127,7 @@ rmtree(release_dir, 'configs/test') rmtree(release_dir, 'configs/splash2') rmtree(release_dir, 'tests/long/*/ref') rmtree(release_dir, 'tests/old') +rmtree(release_dir, 'src/dev/i8*') # get rid of some of private scripts remove(release_dir, 'util/chgcopyright') @@ -143,6 +144,20 @@ for line in inscript: outscript.write(line) outscript.close() +# fix up the SConscript to deal with files we've removed +mem_expr = re.compile('.*i8254xGBe.*') +inscript = file(joinpath(release_dir, 'src', 'dev', 'SConscript'), 'r').readlines() +outscript = file(joinpath(release_dir, 'src', 'dev', 'SConscript'), 'w') +for line in inscript: + if mem_expr.match(line): + continue + + outscript.write(line) +outscript.close() + + + + benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', 'twolf', 'vortex' ] for bench in benches: |