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-rw-r--r--dev/tsunami_cchip.cc91
-rw-r--r--dev/tsunami_cchip.hh9
-rw-r--r--dev/tsunami_io.cc7
3 files changed, 85 insertions, 22 deletions
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 2f0e6a883..ba49c361b 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -31,11 +31,12 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
dim[i] = 0;
dir[i] = 0;
dirInterrupting[i] = false;
+ ipiInterrupting[i] = false;
+ RTCInterrupting[i] = false;
}
drir = 0;
misc = 0;
- RTCInterrupting = false;
//Put back pointer in tsunami
tsunami->cchip = this;
@@ -135,25 +136,67 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
+ bool supportedWrite = false;
+ uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+
switch (req->size) {
case sizeof(uint64_t):
switch(daddr) {
- case TSDEV_CC_CSR:
+ case TSDEV_CC_CSR:
panic("TSDEV_CC_CSR write\n");
return No_Fault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR write not implemented\n");
return No_Fault;
case TSDEV_CC_MISC:
- //If it is the seventh bit, clear the RTC interrupt
- if ((*(uint64_t*) data) & (1<<4)) {
- RTCInterrupting = false;
- tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0);
- DPRINTF(Tsunami, "clearing rtc interrupt\n");
- misc &= ~(1<<4);
- } else panic("TSDEV_CC_MISC write not implemented\n");
- return No_Fault;
+ //If it is the 4-7th bit, clear the RTC interrupt
+ uint64_t itintr;
+ if ((itintr = (*(uint64_t*) data) & (0xf<<4))) {
+ //Clear the bits in ITINTR
+ misc &= ~(itintr);
+ for (int i=0; i < size; i++) {
+ if ((itintr & (1 << (i+4))) && RTCInterrupting[i]) {
+ tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
+ RTCInterrupting[i] = false;
+ DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
+ }
+ }
+ supportedWrite = true;
+ }
+ //If it is 12th-15th bit, IPI sent to Processor 1
+ uint64_t ipreq;
+ if ((ipreq = (*(uint64_t*) data) & (0xf << 12))) {
+ //Set the bits in IPINTR
+ misc |= (ipreq >> 4);
+ for (int i=0; i < size; i++) {
+ if ((ipreq & (1 << (i + 12)))) {
+ if (!ipiInterrupting[i])
+ tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ3, 0);
+ ipiInterrupting[i]++;
+ DPRINTF(IPI, "send cpu=%d pending=%d from=%d\n", i,
+ ipiInterrupting[i], req->cpu_num);
+ }
+ }
+ supportedWrite = true;
+ }
+ //If it is bits 8-11, then clearing IPI's
+ uint64_t ipintr;
+ if ((ipintr = (*(uint64_t*) data) & (0xf << 8))) {
+ //Clear the bits in IPINTR
+ misc &= ~(ipintr);
+ for (int i=0; i < size; i++) {
+ if ((ipintr & (1 << (i + 8))) && ipiInterrupting[i]) {
+ if (!(--ipiInterrupting[i]))
+ tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ3, 0);
+ DPRINTF(IPI, "clearing cpu=%d pending=%d from=%d\n", i,
+ ipiInterrupting[i] + 1, req->cpu_num);
+ }
+ }
+ supportedWrite = true;
+ }
+ if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n");
+ return No_Fault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
@@ -246,11 +289,28 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
void
+TsunamiCChip::postRTC()
+{
+ int size = tsunami->intrctrl->cpu->system->execContexts.size();
+
+ for (int i = 0; i < size; i++) {
+ if (!RTCInterrupting[i]) {
+ misc |= 16 << i;
+ RTCInterrupting[i] = true;
+ tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
+ DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
+ }
+ }
+
+}
+
+void
TsunamiCChip::postDRIR(uint32_t interrupt)
{
uint64_t bitvector = (uint64_t)0x1 << interrupt;
drir |= bitvector;
- for(int i=0; i < Tsunami::Max_CPUs; i++) {
+ uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ for(int i=0; i < size; i++) {
dir[i] = dim[i] & drir;
if (dim[i] & bitvector) {
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
@@ -264,10 +324,11 @@ void
TsunamiCChip::clearDRIR(uint32_t interrupt)
{
uint64_t bitvector = (uint64_t)0x1 << interrupt;
+ uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
if (drir & bitvector)
{
drir &= ~bitvector;
- for(int i=0; i < Tsunami::Max_CPUs; i++) {
+ for(int i=0; i < size; i++) {
if (dir[i] & bitvector) {
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
@@ -287,9 +348,10 @@ TsunamiCChip::serialize(std::ostream &os)
SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
SERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs);
+ SERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs);
SERIALIZE_SCALAR(drir);
SERIALIZE_SCALAR(misc);
- SERIALIZE_SCALAR(RTCInterrupting);
+ SERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs);
}
void
@@ -298,9 +360,10 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
UNSERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs);
+ UNSERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs);
UNSERIALIZE_SCALAR(drir);
UNSERIALIZE_SCALAR(misc);
- UNSERIALIZE_SCALAR(RTCInterrupting);
+ UNSERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index 75214c527..adb05a572 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -72,6 +72,11 @@ class TsunamiCChip : public FunctionalMemory
*/
uint64_t drir;
+ uint64_t misc;
+
+ uint64_t ipiInterrupting[Tsunami::Max_CPUs];
+ bool RTCInterrupting[Tsunami::Max_CPUs];
+
public:
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
MemoryController *mmu);
@@ -79,14 +84,12 @@ class TsunamiCChip : public FunctionalMemory
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ void postRTC();
void postDRIR(uint32_t interrupt);
void clearDRIR(uint32_t interrupt);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
-
- uint64_t misc;
- bool RTCInterrupting;
};
#endif // __TSUNAMI_CCHIP_HH__
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index fa87a72c4..d32291d0d 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -65,11 +65,8 @@ TsunamiIO::RTCEvent::process()
DPRINTF(MC146818, "RTC Timer Interrupt\n");
schedule(curTick + ticksPerSecond/RTC_RATE);
//Actually interrupt the processor here
- if (!tsunami->cchip->RTCInterrupting) {
- tsunami->cchip->misc |= 1 << 7;
- tsunami->cchip->RTCInterrupting = true;
- tsunami->intrctrl->post(0, TheISA::INTLEVEL_IRQ2, 0);
- }
+ tsunami->cchip->postRTC();
+
}
const char *
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-28 02:25:04 +0000