diff options
49 files changed, 3754 insertions, 273 deletions
diff --git a/configs/boot/nat-netperf-maerts-client.rcS b/configs/boot/nat-netperf-maerts-client.rcS index 863766a6b..d8a6d4dc4 100644 --- a/configs/boot/nat-netperf-maerts-client.rcS +++ b/configs/boot/nat-netperf-maerts-client.rcS @@ -41,7 +41,6 @@ eval $SHORT echo "netperf benchmark" echo $LONG -/sbin/m5 ivlb 1 /sbin/m5 resetstats /sbin/m5 dumpresetstats 200000000 2000000000 /sbin/m5 checkpoint 200000000 2000000000 diff --git a/configs/boot/netperf-maerts-client.rcS b/configs/boot/netperf-maerts-client.rcS index 3270d0058..7766713aa 100644 --- a/configs/boot/netperf-maerts-client.rcS +++ b/configs/boot/netperf-maerts-client.rcS @@ -21,7 +21,7 @@ echo "100000" > /proc/sys/net/core/netdev_max_backlog echo -n "waiting for server..." /usr/bin/netcat -c -l -p 8000 -BINARY=/benchmarks/netperf/netperf +BINARY=/benchmarks/netperf-bin/netperf TEST="TCP_MAERTS" SHORT_ARGS="-l -100k" LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 1c0a56362..eb74346c8 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -89,17 +89,18 @@ def makeSparcSystem(mem_mode, mdesc = None): self.bridge = Bridge() self.t1000 = T1000() self.t1000.attachIO(self.iobus) - self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) + self.physmem = PhysicalMemory(range = AddrRange('64MB'), zero = True) + self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port self.physmem.port = self.membus.port + self.physmem2.port = self.membus.port self.rom.port = self.membus.port self.nvram.port = self.membus.port self.hypervisor_desc.port = self.membus.port self.partition_desc.port = self.membus.port self.intrctrl = IntrControl() self.mem_mode = mem_mode - self.kernel = binary('vmlinux') self.reset_bin = binary('reset.bin') self.hypervisor_bin = binary('q.bin') diff --git a/configs/example/fs.py b/configs/example/fs.py index a70a60b97..d479d717e 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -92,7 +92,13 @@ else: else: bm = [SysConfig()] -test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) +if m5.build_env['TARGET_ISA'] == "alpha": + test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) +elif m5.build_env['TARGET_ISA'] == "sparc": + test_sys = makeSparcSystem(test_mem_mode, bm[0]) +else: + m5.panic("incapable of building non-alpha or non-sparc full system!") + np = options.num_cpus if options.l2cache: @@ -113,7 +119,10 @@ for i in xrange(np): test_sys.cpu[i].connectMemPorts(test_sys.membus) if len(bm) == 2: - drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) + if m5.build_env['TARGET_ISA'] == 'alpha': + drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) + elif m5.build_env['TARGET_ISA'] == 'sparc': + drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) drive_sys.cpu = DriveCPUClass(cpu_id=0) drive_sys.cpu.connectMemPorts(drive_sys.membus) root = makeDualRoot(test_sys, drive_sys, options.etherdump) diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index a0a6112de..c2ef97bfa 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -60,6 +60,7 @@ full_system_sources = Split(''' stacktrace.cc system.cc tlb.cc + ua2005.cc vtophys.cc ''') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index a355816ac..781958c77 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -377,7 +377,9 @@ decode OP default Unknown::unknown() //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); - 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); + 0x04: PrivCheck::rdtick( + {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}}, + {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ if(Pstate<3:>) Rd = (xc->readPC())<31:0>; @@ -403,9 +405,15 @@ decode OP default Unknown::unknown() }}); //0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); - 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); - 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); - 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); + 0x17: Priv::rdtick_cmpr({{ + Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR); + }}); + 0x18: PrivCheck::rdstick({{ + Rd = xc->readMiscRegWithEffect(MISCREG_STICK); + }}, {{Stick<63:>}}); + 0x19: Priv::rdstick_cmpr({{ + Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR); + }}); 0x1A: Priv::rdstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) Rd = StrandStsReg<0:>; @@ -429,7 +437,9 @@ decode OP default Unknown::unknown() 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 0x06: HPriv::rdhprhver({{Rd = Hver;}}); //0x07-0x1E should cause an illegal instruction exception - 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); + 0x1F: HPriv::rdhprhstick_cmpr({{ + Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR); + }}); } 0x2A: decode RS1 { 0x00: Priv::rdprtpc({{ @@ -452,7 +462,9 @@ decode OP default Unknown::unknown() return new IllegalInstruction; Rd = Tt; }}); - 0x04: Priv::rdprtick({{Rd = Tick;}}); + 0x04: Priv::rdprtick({{ + Rd = xc->readMiscRegWithEffect(MISCREG_TICK); + }}); 0x05: Priv::rdprtba({{Rd = Tba;}}); 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 0x07: Priv::rdprtl({{Rd = Tl;}}); @@ -542,13 +554,17 @@ decode OP default Unknown::unknown() 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); - 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); + 0x17: Priv::wrtick_cmpr({{ + xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13); + }}); 0x18: NoPriv::wrstick({{ if(!Hpstate<2:>) return new IllegalInstruction; - Stick = Rs1 ^ Rs2_or_imm13; + xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13); + }}); + 0x19: Priv::wrstick_cmpr({{ + xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13); }}); - 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x1A: Priv::wrstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) StrandStsReg = StrandStsReg<63:1> | @@ -605,7 +621,9 @@ decode OP default Unknown::unknown() else Tt = Rs1 ^ Rs2_or_imm13; }}); - 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); + 0x04: HPriv::wrprtick({{ + xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13); + }}); 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 0x07: Priv::wrprtl({{ @@ -642,7 +660,9 @@ decode OP default Unknown::unknown() //0x04 should cause an illegal instruction exception 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); //0x06-0x01D should cause an illegal instruction exception - 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); + 0x1F: HPriv::wrhprhstick_cmpr({{ + xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13); + }}); } 0x34: decode OPF{ format BasicOperate{ diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index d2164155f..046d811e0 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -72,7 +72,7 @@ void MiscRegFile::clear() y = 0; ccr = 0; asi = 0; - tick = 0; + tick = ULL(1) << 63; fprs = 0; gsr = 0; softint = 0; @@ -282,10 +282,19 @@ MiscReg MiscRegFile::readReg(int miscReg) MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) { switch (miscReg) { + // tick and stick are aliased to each other in niagra + case MISCREG_STICK: case MISCREG_TICK: case MISCREG_PRIVTICK: - return tc->getCpuPtr()->curCycle() - (tick & mask(63)) | - (tick & ~(mask(63))) << 63; + // I'm not sure why legion ignores the lowest two bits, but we'll go + // with it + // change from curCycle() to instCount() until we're done with legion + DPRINTFN("Instruction Count when STICK read: %#X\n", + tc->getCpuPtr()->instCount()); + uint64_t t1 = mbits(tc->getCpuPtr()->instCount() - (tick & + mask(63)),62,2); + uint64_t t2 = mbits(tick,63,63) ; + return t1 | t2; case MISCREG_FPRS: panic("FPU not implemented\n"); case MISCREG_PCR: @@ -296,13 +305,13 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) panic("Floating Point not implemented\n"); //We'll include this only in FS so we don't need the SparcSystem type around //in SE. -#if FULL_SYSTEM +/*#if FULL_SYSTEM case MISCREG_STICK: SparcSystem *sys; sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); -#endif +#endif*/ case MISCREG_HVER: return NWindows | MaxTL << 8 | MaxGL << 16; } @@ -518,8 +527,10 @@ void MiscRegFile::setRegWithEffect(int miscReg, SparcSystem *sys; #endif switch (miscReg) { + case MISCREG_STICK: case MISCREG_TICK: - tick = tc->getCpuPtr()->curCycle() - val & ~Bit64; + // change from curCycle() to instCount() until we're done with legion + tick = tc->getCpuPtr()->instCount() - val & ~Bit64; tick |= val & Bit64; break; case MISCREG_FPRS: @@ -575,12 +586,14 @@ void MiscRegFile::setRegWithEffect(int miscReg, //We'll include this only in FS so we don't need the SparcSystem type around //in SE. #if FULL_SYSTEM - case MISCREG_STICK: + // @todo figure out how we're actualy going to do this. In niagra the + // registers are aliased to the same thing (see tick above) + /*case MISCREG_STICK: sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; stick |= val & Bit64; - break; + break;*/ case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index e7779d333..916c23028 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -213,6 +213,10 @@ namespace SparcISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM + void setFSRegWithEffect(int miscReg, const MiscReg &val, + ThreadContext *tc); + MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ void processTickCompare(ThreadContext *tc); diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmaped_ipr.hh index d87d127b0..b11c16754 100644 --- a/src/arch/sparc/mmaped_ipr.hh +++ b/src/arch/sparc/mmaped_ipr.hh @@ -37,6 +37,7 @@ * ISA-specific helper functions for memory mapped IPR accesses. */ +#include "config/full_system.hh" #include "cpu/thread_context.hh" #include "mem/packet.hh" #include "arch/sparc/tlb.hh" @@ -47,14 +48,22 @@ namespace SparcISA inline Tick handleIprRead(ThreadContext *xc, Packet *pkt) { +#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegRead(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif } inline Tick handleIprWrite(ThreadContext *xc, Packet *pkt) { +#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif } diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index 72c87f0ad..da83d86fc 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -155,6 +155,11 @@ SparcSystem::SparcSystem(Params *p) if (!hypervisor->loadLocalSymbols(debugSymbolTable)) panic("could not load hypervisor symbols\n"); + // Strip off the rom address so when the hypervisor is copied into memory we + // have symbols still + if (!hypervisor->loadLocalSymbols(debugSymbolTable, 0xFFFFFF)) + panic("could not load hypervisor symbols\n"); + if (!nvram->loadGlobalSymbols(debugSymbolTable)) panic("could not load reset symbols\n"); diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 5fde4d36d..51f867612 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -29,10 +29,11 @@ */ #include "arch/sparc/asi.hh" -#include "arch/sparc/tlb.hh" -#include "sim/builder.hh" #include "arch/sparc/miscregfile.hh" +#include "arch/sparc/tlb.hh" +#include "base/trace.hh" #include "cpu/thread_context.hh" +#include "sim/builder.hh" /* @todo remove some of the magic constants. -- ali * */ @@ -72,6 +73,10 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, MapIter i; TlbEntry *new_entry; + + DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n", + va, partition_id, context_id, (int)real); + int x = -1; for (x = 0; x < size; x++) { if (!tlb[x].valid || !tlb[x].used) { @@ -104,6 +109,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, i->second->used = false; usedEntries--; } + DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); lookupTable.erase(i); } @@ -127,6 +133,8 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id) TlbRange tr; TlbEntry *t; + DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", + va, partition_id, context_id, real); // Assemble full address structure tr.va = va; tr.size = va + MachineBytes; @@ -137,8 +145,10 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id) // Try to find the entry i = lookupTable.find(tr); if (i == lookupTable.end()) { + DPRINTF(TLB, "TLB: No valid entry found\n"); return NULL; } + DPRINTF(TLB, "TLB: Valid entry found\n"); // Mark the entries used bit and clear other used bits in needed t = i->second; @@ -279,6 +289,8 @@ void ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, bool se, FaultTypes ft, int asi) { + DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", + (int)write, ct, ft, asi); TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); } @@ -286,6 +298,8 @@ void DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi) { + DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", + a, (int)write, ct, ft, asi); TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); } @@ -308,6 +322,9 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) bool real = false; TlbEntry *e; + DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", + vaddr, req->getSize()); + assert(req->getAsi() == ASI_IMPLICIT); if (tl > 0) { @@ -385,14 +402,17 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) bool implicit = false; bool real = false; Addr vaddr = req->getVaddr(); + Addr size = req->getSize(); ContextType ct; int context; ASI asi; TlbEntry *e; - asi = (ASI)req->getAsi(); + DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", + vaddr, size, asi); + if (asi == ASI_IMPLICIT) implicit = true; @@ -432,7 +452,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } // If the asi is unaligned trap - if (AsiIsBlock(asi) && vaddr & 0x3f || vaddr & 0x7) { + if (vaddr & size-1) { writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); return new MemAddressNotAligned; } @@ -478,6 +498,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (e == NULL || !e->valid) { tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, vaddr & ~BytesInPageMask | context); + DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); if (real) return new DataRealTranslationMiss; else @@ -516,6 +537,7 @@ handleScratchRegAccess: return new DataAccessException; } handleMmuRegAccess: + DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); req->setMmapedIpr(true); req->setPaddr(req->getVaddr()); return NoFault; diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 6493ddfd5..32bc2a44b 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -28,27 +28,32 @@ * Authors: Ali Saidi */ -#include "arch/sparc/regfile.hh" +#include "arch/sparc/miscregfile.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" -Fault -SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, +using namespace SparcISA; + +void +MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, ThreadContext *tc) { int64_t time; - SparcSystem *sys; + int oldLevel, newLevel; switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - if (isNonPriv()) - return new PrivilegedOpcode; // Check if we are going to interrupt because of something - int oldLevel = InterruptLevel(softint); - int newLevel = InterruptLevel(val); + oldLevel = InterruptLevel(softint); + newLevel = InterruptLevel(val); setReg(miscReg, val); if (newLevel > oldLevel) ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX //tc->getCpuPtr()->checkInterrupts = true; - return NoFault; + panic("SOFTINT not implemented\n"); + break; case MISCREG_SOFTINT_CLR: return setRegWithEffect(miscReg, ~val & softint, tc); @@ -56,152 +61,100 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, return setRegWithEffect(miscReg, val | softint, tc); case MISCREG_TICK_CMPR: - if (isNonPriv()) - return new PrivilegedOpcode; if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); setReg(miscReg, val); - if (tick_cmprFields.int_dis && tickCompare.scheduled()) - tickCompare.deschedule(); - time = tick_cmprFields.tick_cmpr - tickFields.counter; - if (!tick_cmprFields.int_dis && time > 0) - tickCompare.schedule(time * tc->getCpuPtr()->cycles(1)); - return NoFault; - - case MISCREG_STICK: - if (isNonPriv()) - return new PrivilegedOpcode; - if (isPriv()) - return new PrivilegedAction; - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); - sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; - stickFields.npt = val & Bit64 ? 1 : 0; - return NoFault; + if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) + tickCompare->deschedule(); + time = (tick_cmpr & mask(63)) - (tick & mask(63)); + if (!(tick_cmpr & ~mask(63)) && time > 0) + tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; case MISCREG_STICK_CMPR: - if (isNonPriv()) - return new PrivilegedOpcode; if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); setReg(miscReg, val); - if (stick_cmprFields.int_dis && sTickCompare.scheduled()) - sTickCompare.deschedule(); - time = stick_cmprFields.tick_cmpr - sys->sysTick; - if (!stick_cmprFields.int_dis && time > 0) - sTickCompare.schedule(time * Clock::Int::ns); - return NoFault; - - /* Fullsystem only Priv registers. */ + if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) + sTickCompare->deschedule(); + time = (stick_cmpr & mask(63)) - (stick & mask(63)); + if (!(stick_cmpr & ~mask(63)) && time > 0) + sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; + case MISCREG_PIL: - if (FULL_SYSTEM) { - setReg(miscReg, val); - //tc->getCpuPtr()->checkInterrupts; - // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX - return NoFault; - } else - panic("PIL not implemented for syscall emulation\n"); - - /* Hyper privileged registers */ - case MISCREG_HPSTATE: - case MISCREG_HINTP: setReg(miscReg, val); - return NoFault; - case MISCREG_HTSTATE: - if (tl == 0) - return new IllegalInstruction; - setReg(miscReg, val); - return NoFault; + //tc->getCpuPtr()->checkInterrupts; + // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX + panic("PIL not implemented\n"); + break; + + case MISCREG_HVER: + panic("Shouldn't be writing HVER\n"); case MISCREG_HTBA: // clear lower 7 bits on writes. setReg(miscReg, val & ULL(~0x7FFF)); - return NoFault; + break; - case MISCREG_STRAND_STS_REG: - setReg(miscReg, strandStatusReg); - return NoFault; case MISCREG_HSTICK_CMPR: - if (isNonPriv()) - return new PrivilegedOpcode; if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); setReg(miscReg, val); - if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) - hSTickCompare.deschedule(); - int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; - if (!hstick_cmprFields.int_dis && time > 0) - hSTickCompare.schedule(time * Clock::Int::ns); - return NoFault; + if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) + hSTickCompare->deschedule(); + time = (hstick_cmpr & mask(63)) - (stick & mask(63)); + if (!(hstick_cmpr & ~mask(63)) && time > 0) + hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; + + case MISCREG_HPSTATE: + case MISCREG_HTSTATE: + case MISCREG_STRAND_STS_REG: + setReg(miscReg, val); + break; + default: - return new IllegalInstruction; + panic("Invalid write to FS misc register\n"); } } MiscReg -MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) +MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) { switch (miscReg) { /* Privileged registers. */ case MISCREG_SOFTINT: - if (isNonPriv()) { - fault = new PrivilegedOpcode; - return 0; - } - return readReg(miscReg); case MISCREG_TICK_CMPR: - if (isNonPriv()) { - fault = new PrivilegedOpcode; - return 0; - } - return readReg(miscReg); - case MISCREG_STICK: - SparcSystem *sys; - if (stickFields.npt && !isNonPriv()) { - fault = new PrivilegedAction; - return 0; - } - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); - return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; case MISCREG_STICK_CMPR: - if (isNonPriv()) { - fault = new PrivilegedOpcode; - return 0; - } - return readReg(miscReg); - - - /* Hyper privileged registers */ + case MISCREG_PIL: case MISCREG_HPSTATE: case MISCREG_HINTP: - return readReg(miscReg); case MISCREG_HTSTATE: - if (tl == 0) { - fault = new IllegalInstruction; - return 0; - } - return readReg(miscReg); + case MISCREG_STRAND_STS_REG: + case MISCREG_HSTICK_CMPR: + return readReg(miscReg) ; case MISCREG_HTBA: return readReg(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: return NWindows | MaxTL << 8 | MaxGL << 16; - case MISCREG_STRAND_STS_REG: - return strandStatusReg; - case MISCREG_HSTICK_CMPR: - return hstick_cmpr; default: - fault = new IllegalInstruction; - return 0; + panic("Invalid read to FS misc register\n"); } } +/* + In Niagra STICK==TICK so this isn't needed + case MISCREG_STICK: + SparcSystem *sys; + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); + assert(sys != NULL); + return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); +*/ + + void MiscRegFile::processTickCompare(ThreadContext *tc) @@ -221,4 +174,3 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) panic("tick compare not implemented\n"); } -}; // namespace SparcISA diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh index 177279678..1fc0bad5d 100644 --- a/src/base/bitfield.hh +++ b/src/base/bitfield.hh @@ -58,6 +58,18 @@ bits(T val, int first, int last) } /** + * Mask off the given bits in place like bits() but without shifting. + * msb = 63, lsb = 0 + */ +template <class T> +inline +T +mbits(T val, int first, int last) +{ + return val & (mask(first+1) & ~mask(last)); +} + +/** * Sign-extend an N-bit value to 64 bits. */ template <int N> diff --git a/src/base/loader/aout_object.cc b/src/base/loader/aout_object.cc index 6691bd4ae..8fbad8030 100644 --- a/src/base/loader/aout_object.cc +++ b/src/base/loader/aout_object.cc @@ -82,14 +82,14 @@ AoutObject::AoutObject(const string &_filename, int _fd, bool -AoutObject::loadGlobalSymbols(SymbolTable *symtab) +AoutObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { // a.out symbols not supported yet return false; } bool -AoutObject::loadLocalSymbols(SymbolTable *symtab) +AoutObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { // a.out symbols not supported yet return false; diff --git a/src/base/loader/aout_object.hh b/src/base/loader/aout_object.hh index d180d69f3..7bac5be65 100644 --- a/src/base/loader/aout_object.hh +++ b/src/base/loader/aout_object.hh @@ -48,8 +48,10 @@ class AoutObject : public ObjectFile public: virtual ~AoutObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/base/loader/ecoff_object.cc b/src/base/loader/ecoff_object.cc index 134f2d98d..a5a0ad9a4 100644 --- a/src/base/loader/ecoff_object.cc +++ b/src/base/loader/ecoff_object.cc @@ -86,7 +86,7 @@ EcoffObject::EcoffObject(const string &_filename, int _fd, bool -EcoffObject::loadGlobalSymbols(SymbolTable *symtab) +EcoffObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { if (!symtab) return false; @@ -115,7 +115,7 @@ EcoffObject::loadGlobalSymbols(SymbolTable *symtab) } bool -EcoffObject::loadLocalSymbols(SymbolTable *symtab) +EcoffObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { if (!symtab) return false; diff --git a/src/base/loader/ecoff_object.hh b/src/base/loader/ecoff_object.hh index 05c604b2b..ca6fa2dd0 100644 --- a/src/base/loader/ecoff_object.hh +++ b/src/base/loader/ecoff_object.hh @@ -52,8 +52,10 @@ class EcoffObject : public ObjectFile public: virtual ~EcoffObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 2ca0d4f4a..7339507f6 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -330,13 +330,13 @@ ElfObject::loadSomeSymbols(SymbolTable *symtab, int binding) } bool -ElfObject::loadGlobalSymbols(SymbolTable *symtab) +ElfObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { return loadSomeSymbols(symtab, STB_GLOBAL); } bool -ElfObject::loadLocalSymbols(SymbolTable *symtab) +ElfObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { return loadSomeSymbols(symtab, STB_LOCAL); } diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh index 9755426b4..fb728b3c5 100644 --- a/src/base/loader/elf_object.hh +++ b/src/base/loader/elf_object.hh @@ -53,8 +53,10 @@ class ElfObject : public ObjectFile public: virtual ~ElfObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh index 64085185d..6e98332c5 100644 --- a/src/base/loader/object_file.hh +++ b/src/base/loader/object_file.hh @@ -78,8 +78,10 @@ class ObjectFile virtual bool loadSections(Port *memPort, Addr addrMask = std::numeric_limits<Addr>::max()); - virtual bool loadGlobalSymbols(SymbolTable *symtab) = 0; - virtual bool loadLocalSymbols(SymbolTable *symtab) = 0; + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()) = 0; + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()) = 0; Arch getArch() const { return arch; } OpSys getOpSys() const { return opSys; } diff --git a/src/base/loader/raw_object.cc b/src/base/loader/raw_object.cc index 1faf33426..2a52b0d6e 100644 --- a/src/base/loader/raw_object.cc +++ b/src/base/loader/raw_object.cc @@ -61,21 +61,21 @@ RawObject::RawObject(const std::string &_filename, int _fd, size_t _len, } bool -RawObject::loadGlobalSymbols(SymbolTable *symtab) +RawObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { int fnameStart = filename.rfind('/',filename.size()) + 1; int extStart = filename.rfind('.',filename.size()); - symtab->insert(text.baseAddr, filename.substr(fnameStart, + symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart, extStart-fnameStart) + "_start"); return true; } bool -RawObject::loadLocalSymbols(SymbolTable *symtab) +RawObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { int fnameStart = filename.rfind('/',filename.size()) + 1; int extStart = filename.rfind('.',filename.size()); - symtab->insert(text.baseAddr, filename.substr(fnameStart, + symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart, extStart-fnameStart) + "_start"); return true; } diff --git a/src/base/loader/raw_object.hh b/src/base/loader/raw_object.hh index c7fff4e66..9014a2d30 100644 --- a/src/base/loader/raw_object.hh +++ b/src/base/loader/raw_object.hh @@ -41,8 +41,10 @@ class RawObject: public ObjectFile public: virtual ~RawObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 7cbbb0b96..31604ad58 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -96,7 +96,7 @@ CPUProgressEvent::description() #if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) - : MemObject(p->name), clock(p->clock), checkInterrupts(true), + : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true), params(p), number_of_threads(p->numberOfThreads), system(p->system), phase(p->phase) #else diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 1d9b6a93b..8c6b079da 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -70,12 +70,16 @@ class BaseCPU : public MemObject protected: // CPU's clock period in terms of the number of ticks of curTime. Tick clock; + // @todo remove me after debugging with legion done + Tick instCnt; public: // Tick currentTick; inline Tick frequency() const { return Clock::Frequency / clock; } inline Tick cycles(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } + // @todo remove me after debugging with legion done + Tick instCount() { return instCnt; } /** The next cycle the CPU should be scheduled, given a cache * access or quiesce event returning on this cycle. This function diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index f3b9b51b2..71e974a36 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -279,12 +279,13 @@ Trace::InstRecord::dump(ostream &outs) // outs << endl; } -#if THE_ISA == SPARC_ISA +#if THE_ISA == SPARC_ISA && FULL_SYSTEM // Compare if (flags[LEGION_LOCKSTEP]) { bool compared = false; bool diffPC = false; + bool diffCC = false; bool diffInst = false; bool diffRegs = false; bool diffTpc = false; @@ -317,6 +318,11 @@ Trace::InstRecord::dump(ostream &outs) lgnPc = shared_data->pc & TheISA::PAddrImplMask; if (lgnPc != m5Pc) diffPC = true; + + if (shared_data->cycle_count != + thread->getCpuPtr()->instCount()) + diffCC = true; + if (shared_data->instruction != (SparcISA::MachInst)staticInst->machInst) { diffInst = true; @@ -332,19 +338,19 @@ Trace::InstRecord::dump(ostream &outs) for (int i = 1; i <= MaxTL; i++) { thread->setMiscReg(MISCREG_TL, i); if (thread->readMiscReg(MISCREG_TPC) != - shared_data->tpc[i]) + shared_data->tpc[i-1]) diffTpc = true; if (thread->readMiscReg(MISCREG_TNPC) != - shared_data->tnpc[i]) + shared_data->tnpc[i-1]) diffTnpc = true; if (thread->readMiscReg(MISCREG_TSTATE) != - shared_data->tstate[i]) + shared_data->tstate[i-1]) diffTstate = true; if (thread->readMiscReg(MISCREG_TT) != - shared_data->tt[i]) + shared_data->tt[i-1]) diffTt = true; if (thread->readMiscReg(MISCREG_HTSTATE) != - shared_data->htstate[i]) + shared_data->htstate[i-1]) diffHtstate = true; } thread->setMiscReg(MISCREG_TL, oldTl); @@ -385,8 +391,8 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) diffCleanwin = true; - if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc || - diffTstate || diffTt || diffHpstate || + if (diffPC || diffCC || diffInst || diffRegs || diffTpc || + diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || @@ -394,6 +400,8 @@ Trace::InstRecord::dump(ostream &outs) outs << "Differences found between M5 and Legion:"; if (diffPC) outs << " [PC]"; + if (diffCC) + outs << " [CC]"; if (diffInst) outs << " [Instruction]"; if (diffRegs) @@ -445,6 +453,13 @@ Trace::InstRecord::dump(ostream &outs) << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex << lgnPc << endl << endl; + outs << right << setfill(' ') << setw(15) + << "M5 CC: " << "0x"<< setw(16) << setfill('0') + << hex << thread->getCpuPtr()->instCount() << endl; + outs << setfill(' ') << setw(15) + << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex + << shared_data->cycle_count << endl << endl; + outs << setfill(' ') << setw(15) << "M5 Inst: " << "0x"<< setw(8) << setfill('0') << hex << staticInst->machInst @@ -512,19 +527,19 @@ Trace::InstRecord::dump(ostream &outs) thread->setMiscReg(MISCREG_TL, i); printRegPair(outs, "Tpc", thread->readMiscReg(MISCREG_TPC), - shared_data->tpc[i]); + shared_data->tpc[i-1]); printRegPair(outs, "Tnpc", thread->readMiscReg(MISCREG_TNPC), - shared_data->tnpc[i]); + shared_data->tnpc[i-1]); printRegPair(outs, "Tstate", thread->readMiscReg(MISCREG_TSTATE), - shared_data->tstate[i]); + shared_data->tstate[i-1]); printRegPair(outs, "Tt", thread->readMiscReg(MISCREG_TT), - shared_data->tt[i]); + shared_data->tt[i-1]); printRegPair(outs, "Htstate", thread->readMiscReg(MISCREG_HTSTATE), - shared_data->htstate[i]); + shared_data->htstate[i-1]); } thread->setMiscReg(MISCREG_TL, oldTl); outs << endl; diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index 373fbeb11..bfb88485a 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -30,7 +30,7 @@ #include <unistd.h> -#define VERSION 0xA1000005 +#define VERSION 0xA1000006 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -42,6 +42,8 @@ typedef struct { uint64_t pc; uint64_t new_pc; + uint64_t cycle_count; + uint64_t new_cycle_count; uint32_t instruction; uint32_t new_instruction; uint64_t intregs[32]; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 67611e815..8db864153 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -295,8 +295,11 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) else dcache_latency = dcachePort.sendAtomic(pkt); dcache_access = true; - - assert(pkt->result == Packet::Success); +#if !defined(NDEBUG) + if (pkt->result != Packet::Success) + panic("Unable to find responder for address pa = %#X va = %#X\n", + pkt->req->getPaddr(), pkt->req->getVaddr()); +#endif data = pkt->get<T>(); if (req->isLocked()) { @@ -391,7 +394,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } dcache_access = true; - assert(pkt->result == Packet::Success); +#if !defined(NDEBUG) + if (pkt->result != Packet::Success) + panic("Unable to find responder for address pa = %#X va = %#X\n", + pkt->req->getPaddr(), pkt->req->getVaddr()); +#endif } if (req->isLocked()) { @@ -484,9 +491,15 @@ AtomicSimpleCPU::tick() dcache_access = false; // assume no dcache access preExecute(); + fault = curStaticInst->execute(this, traceData); postExecute(); + // @todo remove me after debugging with legion done + if (curStaticInst && (!curStaticInst->isMicroOp() || + curStaticInst->isLastMicroOp())) + instCnt++; + if (simulate_stalls) { Tick icache_stall = icache_latency - cycles(1); Tick dcache_stall = diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc index 40909c6a1..c36ddeb83 100644 --- a/src/dev/isa_fake.cc +++ b/src/dev/isa_fake.cc @@ -47,7 +47,10 @@ IsaFake::IsaFake(Params *p) if (!params()->retBadAddr) pioSize = p->pio_size; - memset(&retData, p->retData, sizeof(retData)); + retData8 = params()->retData8; + retData16 = params()->retData16; + retData32 = params()->retData32; + retData64 = params()->retData64; } Tick @@ -55,6 +58,9 @@ IsaFake::read(PacketPtr pkt) { assert(pkt->result == Packet::Unknown); + if (params()->warnAccess != "") + warn("Device %s accessed by read to address %#x size=%d\n", + name(), pkt->getAddr(), pkt->getSize()); if (params()->retBadAddr) { DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); @@ -65,16 +71,16 @@ IsaFake::read(PacketPtr pkt) pkt->getAddr(), pkt->getSize()); switch (pkt->getSize()) { case sizeof(uint64_t): - pkt->set(retData); + pkt->set(retData64); break; case sizeof(uint32_t): - pkt->set((uint32_t)retData); + pkt->set(retData32); break; case sizeof(uint16_t): - pkt->set((uint16_t)retData); + pkt->set(retData16); break; case sizeof(uint8_t): - pkt->set((uint8_t)retData); + pkt->set(retData8); break; default: panic("invalid access size!\n"); @@ -87,6 +93,27 @@ IsaFake::read(PacketPtr pkt) Tick IsaFake::write(PacketPtr pkt) { + if (params()->warnAccess != "") { + uint64_t data; + switch (pkt->getSize()) { + case sizeof(uint64_t): + data = pkt->get<uint64_t>(); + break; + case sizeof(uint32_t): + data = pkt->get<uint32_t>(); + break; + case sizeof(uint16_t): + data = pkt->get<uint16_t>(); + break; + case sizeof(uint8_t): + data = pkt->get<uint8_t>(); + break; + default: + panic("invalid access size!\n"); + } + warn("Device %s accessed by write to address %#x size=%d data=%#x\n", + name(), pkt->getAddr(), pkt->getSize(), data); + } if (params()->retBadAddr) { DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); @@ -94,6 +121,25 @@ IsaFake::write(PacketPtr pkt) } else { DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); + + if (params()->updateData) { + switch (pkt->getSize()) { + case sizeof(uint64_t): + retData64 = pkt->get<uint64_t>(); + break; + case sizeof(uint32_t): + retData32 = pkt->get<uint32_t>(); + break; + case sizeof(uint16_t): + retData16 = pkt->get<uint16_t>(); + break; + case sizeof(uint8_t): + retData8 = pkt->get<uint8_t>(); + break; + default: + panic("invalid access size!\n"); + } + } pkt->result = Packet::Success; } return pioDelay; @@ -105,7 +151,12 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake) Param<Tick> pio_latency; Param<Addr> pio_size; Param<bool> ret_bad_addr; - Param<uint8_t> ret_data; + Param<bool> update_data; + Param<std::string> warn_access; + Param<uint8_t> ret_data8; + Param<uint16_t> ret_data16; + Param<uint32_t> ret_data32; + Param<uint64_t> ret_data64; SimObjectParam<Platform *> platform; SimObjectParam<System *> system; @@ -117,7 +168,12 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake) INIT_PARAM(pio_latency, "Programmed IO latency"), INIT_PARAM(pio_size, "Size of address range"), INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"), - INIT_PARAM(ret_data, "Data to return if not bad addr"), + INIT_PARAM(update_data, "Update returned data"), + INIT_PARAM(warn_access, "Warn if this device is touched"), + INIT_PARAM(ret_data8, "Data to return if not bad addr"), + INIT_PARAM(ret_data16, "Data to return if not bad addr"), + INIT_PARAM(ret_data32, "Data to return if not bad addr"), + INIT_PARAM(ret_data64, "Data to return if not bad addr"), INIT_PARAM(platform, "platform"), INIT_PARAM(system, "system object") @@ -131,7 +187,12 @@ CREATE_SIM_OBJECT(IsaFake) p->pio_delay = pio_latency; p->pio_size = pio_size; p->retBadAddr = ret_bad_addr; - p->retData = ret_data; + p->updateData = update_data; + p->warnAccess = warn_access; + p->retData8= ret_data8; + p->retData16 = ret_data16; + p->retData32 = ret_data32; + p->retData64 = ret_data64; p->platform = platform; p->system = system; return new IsaFake(p); diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh index fee41e325..dc2ad48e8 100644 --- a/src/dev/isa_fake.hh +++ b/src/dev/isa_fake.hh @@ -40,6 +40,8 @@ #include "dev/alpha/tsunami.hh" #include "mem/packet.hh" +#include <string> + /** * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and * rites. It is meant to be placed at an address range @@ -54,11 +56,20 @@ class IsaFake : public BasicPioDevice { Addr pio_size; bool retBadAddr; - uint8_t retData; + bool updateData; + uint8_t retData8; + uint16_t retData16; + uint32_t retData32; + uint64_t retData64; + std::string warnAccess; }; protected: const Params *params() const { return (const Params*)_params; } - uint64_t retData; + uint8_t retData8; + uint16_t retData16; + uint32_t retData32; + uint64_t retData64; + public: /** diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc index 1df6bf15f..5fc787084 100644 --- a/src/dev/sparc/t1000.cc +++ b/src/dev/sparc/t1000.cc @@ -56,50 +56,56 @@ T1000::T1000(const string &name, System *s, IntrControl *ic) Tick T1000::intrFrequency() { - return (Tick)0; + panic("Need implementation\n"); } void T1000::postConsoleInt() { + panic("Need implementation\n"); } void T1000::clearConsoleInt() { + panic("Need implementation\n"); } void T1000::postPciInt(int line) { + panic("Need implementation\n"); } void T1000::clearPciInt(int line) { + panic("Need implementation\n"); } Addr T1000::pciToDma(Addr pciAddr) const { - return (Addr)0; + panic("Need implementation\n"); } Addr T1000::calcConfigAddr(int bus, int dev, int func) { - return (Addr)0; + panic("Need implementation\n"); } void T1000::serialize(std::ostream &os) { + panic("Need implementation\n"); } void T1000::unserialize(Checkpoint *cp, const std::string §ion) { + panic("Need implementation\n"); } BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000) diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh index fb82dff11..2955763a9 100644 --- a/src/dev/sparc/t1000.hh +++ b/src/dev/sparc/t1000.hh @@ -30,7 +30,7 @@ /** * @file - * Declaration of top level class for the Tsunami chipset. This class just + * Declaration of top level class for the T1000 platform chips. This class just * retains pointers to all its children so the children can communicate. */ @@ -69,7 +69,7 @@ class T1000 : public Platform virtual void postConsoleInt(); /** - * Clear a posted CPU interrupt (id=55) + * Clear a posted CPU interrupt */ virtual void clearConsoleInt(); diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index e7019f3ac..8226fe8d2 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -2,7 +2,7 @@ from m5 import build_env from m5.params import * from m5.proxy import * from MemObject import MemObject -from Tsunami import BadAddr +from Device import BadAddr class Bus(MemObject): type = 'Bus' @@ -12,7 +12,7 @@ class Bus(MemObject): width = Param.Int(64, "bus width (bytes)") responder_set = Param.Bool(False, "Did the user specify a default responder.") if build_env['FULL_SYSTEM']: - default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") else: default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index 4672d1065..f4b873a60 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,3 +19,19 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + +class IsaFake(BasicPioDevice): + type = 'IsaFake' + pio_size = Param.Addr(0x8, "Size of address range") + ret_data8 = Param.UInt8(0xFF, "Default data to return") + ret_data16 = Param.UInt16(0xFFFF, "Default data to return") + ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") + ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") + ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") + update_data = Param.Bool(False, "Update the data that is returned on writes") + warn_access = Param.String("", "String to print when device is accessed") + +class BadAddr(IsaFake): + ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") + + diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py index 7ac4dd701..810a320be 100644 --- a/src/python/m5/objects/System.py +++ b/src/python/m5/objects/System.py @@ -15,7 +15,7 @@ class System(SimObject): "boot processor frequency") init_param = Param.UInt64(0, "numerical value to pass into simulator") boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("file that contains the kernel code") + kernel = Param.String("", "file that contains the kernel code") readfile = Param.String("", "file to read startup script from") symbolfile = Param.String("", "file to get the symbols from") diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py index bb0d37bf8..f4ec5bec4 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/python/m5/objects/T1000.py @@ -1,31 +1,62 @@ from m5.params import * from m5.proxy import * -from Device import BasicPioDevice +from Device import BasicPioDevice, IsaFake, BadAddr from Uart import Uart8250 from Platform import Platform from SimConsole import SimConsole, ConsoleListener -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - ret_data = Param.UInt8(0xFF, "Default data to return") - ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") - -class BadAddr(IsaFake): - ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") - class T1000(Platform): type = 'T1000' system = Param.System(Parent.any, "system") - fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000) + fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000, + warn_access="Accessing Clock Unit -- Unimplemented!") + + fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, + ret_data64=0x0000000000000000, update_data=False, + warn_access="Accessing Memory Banks -- Unimplemented!") + + fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000, + warn_access="Accessing IOB -- Unimplemented!") + + fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000, + warn_access="Accessing JBI -- Unimplemented!") + + fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000, + warn_access="Accessing SSI -- Unimplemented!") - uart = Uart8250(pio_addr=0xfff0c2c000) + hvuart = Uart8250(pio_addr=0xfff0c2c000) + puart0 = Uart8250(pio_addr=0x1f10000000) console = SimConsole(listener = ConsoleListener()) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): + self.fake_clk.pio = bus.port + self.fake_membnks.pio = bus.port self.fake_iob.pio = bus.port - self.uart.pio = bus.port + self.fake_jbi.pio = bus.port + self.fake_l2_1.pio = bus.port + self.fake_l2_2.pio = bus.port + self.fake_l2_3.pio = bus.port + self.fake_l2_4.pio = bus.port + self.fake_ssi.pio = bus.port + self.puart0.pio = bus.port + self.hvuart.pio = bus.port diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index ffe93727b..c18210bba 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -1,6 +1,6 @@ from m5.params import * from m5.proxy import * -from Device import BasicPioDevice +from Device import BasicPioDevice, IsaFake, BadAddr from Platform import Platform from AlphaConsole import AlphaConsole from Uart import Uart8250 @@ -11,15 +11,6 @@ class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' tsunami = Param.Tsunami(Parent.any, "Tsunami") -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - ret_data = Param.UInt8(0xFF, "Default data to return") - ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") - -class BadAddr(IsaFake): - ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") - class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' time = Param.UInt64(1136073600, diff --git a/src/sim/system.cc b/src/sim/system.cc index 4b42d41fc..b3ba1b8f1 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -89,36 +89,41 @@ System::System(Params *p) /** * Load the kernel code into memory */ - // Load kernel code - kernel = createObjectFile(params()->kernel_path); - if (kernel == NULL) - fatal("Could not load kernel file %s", params()->kernel_path); - - // Load program sections into memory - kernel->loadSections(&functionalPort, LoadAddrMask); - - // setup entry points - kernelStart = kernel->textBase(); - kernelEnd = kernel->bssBase() + kernel->bssSize(); - kernelEntry = kernel->entryPoint(); - - // load symbols - if (!kernel->loadGlobalSymbols(kernelSymtab)) - panic("could not load kernel symbols\n"); - - if (!kernel->loadLocalSymbols(kernelSymtab)) - panic("could not load kernel local symbols\n"); - - if (!kernel->loadGlobalSymbols(debugSymbolTable)) - panic("could not load kernel symbols\n"); - - if (!kernel->loadLocalSymbols(debugSymbolTable)) - panic("could not load kernel local symbols\n"); - - DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); - DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); - DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); - DPRINTF(Loader, "Kernel loaded...\n"); + if (params()->kernel_path == "") { + warn("No kernel set for full system simulation. Assuming you know what" + " you're doing...\n"); + } else { + // Load kernel code + kernel = createObjectFile(params()->kernel_path); + if (kernel == NULL) + fatal("Could not load kernel file %s", params()->kernel_path); + + // Load program sections into memory + kernel->loadSections(&functionalPort, LoadAddrMask); + + // setup entry points + kernelStart = kernel->textBase(); + kernelEnd = kernel->bssBase() + kernel->bssSize(); + kernelEntry = kernel->entryPoint(); + + // load symbols + if (!kernel->loadGlobalSymbols(kernelSymtab)) + panic("could not load kernel symbols\n"); + + if (!kernel->loadLocalSymbols(kernelSymtab)) + panic("could not load kernel local symbols\n"); + + if (!kernel->loadGlobalSymbols(debugSymbolTable)) + panic("could not load kernel symbols\n"); + + if (!kernel->loadLocalSymbols(debugSymbolTable)) + panic("could not load kernel local symbols\n"); + + DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); + DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); + DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); + DPRINTF(Loader, "Kernel loaded...\n"); + } #endif // FULL_SYSTEM // increment the number of running systms diff --git a/tests/SConscript b/tests/SConscript index 1228e78d2..8560363f9 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -205,7 +205,9 @@ if env['FULL_SYSTEM']: configs += ['tsunami-simple-atomic', 'tsunami-simple-timing', 'tsunami-simple-atomic-dual', - 'tsunami-simple-timing-dual'] + 'tsunami-simple-timing-dual', + 'twosys-tsunami-simple-atomic'] + else: configs += ['simple-atomic', 'simple-timing', 'o3-timing'] diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py new file mode 100644 index 000000000..e7214a059 --- /dev/null +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -0,0 +1,47 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +from FSConfig import * +from Benchmarks import * + +test_sys = makeLinuxAlphaSystem('atomic', + SysConfig('netperf-stream-client.rcS')) +test_sys.cpu = AtomicSimpleCPU(cpu_id=0) +test_sys.cpu.connectMemPorts(test_sys.membus) + +drive_sys = makeLinuxAlphaSystem('atomic', + SysConfig('netperf-server.rcS')) +drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) +drive_sys.cpu.connectMemPorts(drive_sys.membus) + +root = makeDualRoot(test_sys, drive_sys, "ethertrace") + +maxtick = 199999999 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 3645207b1..b0f73986b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48159 # Simulator instruction rate (inst/s) -host_mem_usage 179620 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 15510230 # Simulator tick rate (ticks/s) +host_inst_rate 158849 # Simulator instruction rate (inst/s) +host_mem_usage 179428 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 50697812 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses @@ -143,49 +143,48 @@ system.cpu.icache.total_refs 4608 # To system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -202,7 +201,7 @@ system.cpu.l2cache.replacements 0 # nu system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini new file mode 100644 index 000000000..dff95e358 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -0,0 +1,1205 @@ +[root] +type=Root +children=drivesys etherdump etherlink testsys +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[drivesys] +type=LinuxAlphaSystem +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +boot_cpu_frequency=1 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=atomic +pal=/dist/m5/system/binaries/ts_osfpal +physmem=drivesys.physmem +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS +symbolfile= +system_rev=1024 +system_type=34 + +[drivesys.bridge] +type=Bridge +delay=0 +queue_size_a=16 +queue_size_b=16 +write_ack=false +side_a=drivesys.iobus.port[0] +side_b=drivesys.membus.port[0] + +[drivesys.cpu] +type=AtomicSimpleCPU +children=dtb itb +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=drivesys.cpu.dtb +function_trace=false +function_trace_start=0 +itb=drivesys.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +profile=0 +progress_interval=0 +simulate_stalls=false +system=drivesys +width=1 +dcache_port=drivesys.membus.port[3] +icache_port=drivesys.membus.port[2] + +[drivesys.cpu.dtb] +type=AlphaDTB +size=64 + +[drivesys.cpu.itb] +type=AlphaITB +size=48 + +[drivesys.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=drivesys.disk0.image + +[drivesys.disk0.image] +type=CowDiskImage +children=child +child=drivesys.disk0.image.child +read_only=false +table_size=65536 + +[drivesys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=drivesys.disk2.image + +[drivesys.disk2.image] +type=CowDiskImage +children=child +child=drivesys.disk2.image.child +read_only=false +table_size=65536 + +[drivesys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[drivesys.intrctrl] +type=IntrControl +cpu=drivesys.cpu + +[drivesys.iobus] +type=Bus +bus_id=0 +clock=1000 +responder_set=true +width=64 +default=drivesys.tsunami.pciconfig.pio +port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.console.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.tsunami.ethernet.dma drivesys.tsunami.ide.config drivesys.tsunami.ide.dma + +[drivesys.membus] +type=Bus +children=responder +bus_id=1 +clock=1000 +responder_set=false +width=64 +default=drivesys.membus.responder.pio +port=drivesys.bridge.side_b drivesys.physmem.port drivesys.cpu.icache_port drivesys.cpu.dcache_port + +[drivesys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=true +ret_data=255 +system=drivesys +pio=drivesys.membus.default + +[drivesys.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=drivesys.membus.port[1] + +[drivesys.sim_console] +type=SimConsole +children=listener +append_name=true +intr_control=drivesys.intrctrl +listener=drivesys.sim_console.listener +number=0 +output=console + +[drivesys.sim_console.listener] +type=ConsoleListener +port=3456 + +[drivesys.simple_disk] +type=SimpleDisk +children=disk +disk=drivesys.simple_disk.disk +system=drivesys + +[drivesys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.tsunami] +type=Tsunami +children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=drivesys.intrctrl +system=drivesys + +[drivesys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami +pio=drivesys.iobus.port[1] + +[drivesys.tsunami.console] +type=AlphaConsole +cpu=drivesys.cpu +disk=drivesys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=drivesys.tsunami +sim_console=drivesys.sim_console +system=drivesys +pio=drivesys.iobus.port[25] + +[drivesys.tsunami.etherint] +type=NSGigEInt +device=drivesys.tsunami.ethernet +peer=Null + +[drivesys.tsunami.ethernet] +type=NSGigE +children=configdata +clock=0 +config_latency=20000 +configdata=drivesys.tsunami.ethernet.configdata +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:02 +intr_delay=10000000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=drivesys.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=drivesys +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=drivesys.iobus.port[28] +dma=drivesys.iobus.port[29] +pio=drivesys.iobus.port[27] + +[drivesys.tsunami.ethernet.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=256 +BAR1=0 +BAR1Size=4096 +BAR2=0 +BAR2Size=0 +BAR3=0 +BAR3Size=0 +BAR4=0 +BAR4Size=0 +BAR5=0 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 + +[drivesys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[9] + +[drivesys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[20] + +[drivesys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[21] + +[drivesys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[10] + +[drivesys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[12] + +[drivesys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[13] + +[drivesys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[14] + +[drivesys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[15] + +[drivesys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[16] + +[drivesys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[17] + +[drivesys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[18] + +[drivesys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[19] + +[drivesys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[11] + +[drivesys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[8] + +[drivesys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[3] + +[drivesys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[4] + +[drivesys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[5] + +[drivesys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[6] + +[drivesys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=drivesys.tsunami +ret_bad_addr=false +ret_data=255 +system=drivesys +pio=drivesys.iobus.port[7] + +[drivesys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +pio=drivesys.iobus.port[22] + +[drivesys.tsunami.ide] +type=IdeController +children=configdata +config_latency=20000 +configdata=drivesys.tsunami.ide.configdata +disks=drivesys.disk0 drivesys.disk2 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +config=drivesys.iobus.port[30] +dma=drivesys.iobus.port[31] +pio=drivesys.iobus.port[26] + +[drivesys.tsunami.ide.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=8 +BAR1=1 +BAR1Size=4 +BAR2=1 +BAR2Size=8 +BAR3=1 +BAR3Size=4 +BAR4=1 +BAR4Size=16 +BAR5=1 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 + +[drivesys.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +time=1136073600 +tsunami=drivesys.tsunami +pio=drivesys.iobus.port[23] + +[drivesys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami +pio=drivesys.iobus.port[2] + +[drivesys.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=drivesys.tsunami +size=16777216 +system=drivesys +pio=drivesys.iobus.default + +[drivesys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=drivesys.tsunami +sim_console=drivesys.sim_console +system=drivesys +pio=drivesys.iobus.port[24] + +[etherdump] +type=EtherDump +file=ethertrace +maxlen=96 + +[etherlink] +type=EtherLink +delay=0 +delay_var=0 +dump=etherdump +int1=testsys.tsunami.etherint +int2=drivesys.tsunami.etherint +speed=8000.000000 + +[exetrace] +intel_format=false +legion_lockstep=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[testsys] +type=LinuxAlphaSystem +children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami +boot_cpu_frequency=1 +boot_osflags=root=/dev/hda1 console=ttyS0 +console=/dist/m5/system/binaries/console +init_param=0 +kernel=/dist/m5/system/binaries/vmlinux +mem_mode=atomic +pal=/dist/m5/system/binaries/ts_osfpal +physmem=testsys.physmem +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS +symbolfile= +system_rev=1024 +system_type=34 + +[testsys.bridge] +type=Bridge +delay=0 +queue_size_a=16 +queue_size_b=16 +write_ack=false +side_a=testsys.iobus.port[0] +side_b=testsys.membus.port[0] + +[testsys.cpu] +type=AtomicSimpleCPU +children=dtb itb +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=testsys.cpu.dtb +function_trace=false +function_trace_start=0 +itb=testsys.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +profile=0 +progress_interval=0 +simulate_stalls=false +system=testsys +width=1 +dcache_port=testsys.membus.port[3] +icache_port=testsys.membus.port[2] + +[testsys.cpu.dtb] +type=AlphaDTB +size=64 + +[testsys.cpu.itb] +type=AlphaITB +size=48 + +[testsys.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=testsys.disk0.image + +[testsys.disk0.image] +type=CowDiskImage +children=child +child=testsys.disk0.image.child +read_only=false +table_size=65536 + +[testsys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=testsys.disk2.image + +[testsys.disk2.image] +type=CowDiskImage +children=child +child=testsys.disk2.image.child +read_only=false +table_size=65536 + +[testsys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[testsys.intrctrl] +type=IntrControl +cpu=testsys.cpu + +[testsys.iobus] +type=Bus +bus_id=0 +clock=1000 +responder_set=true +width=64 +default=testsys.tsunami.pciconfig.pio +port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.console.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.tsunami.ethernet.dma testsys.tsunami.ide.config testsys.tsunami.ide.dma + +[testsys.membus] +type=Bus +children=responder +bus_id=1 +clock=1000 +responder_set=false +width=64 +default=testsys.membus.responder.pio +port=testsys.bridge.side_b testsys.physmem.port testsys.cpu.icache_port testsys.cpu.dcache_port + +[testsys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=true +ret_data=255 +system=testsys +pio=testsys.membus.default + +[testsys.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=testsys.membus.port[1] + +[testsys.sim_console] +type=SimConsole +children=listener +append_name=true +intr_control=testsys.intrctrl +listener=testsys.sim_console.listener +number=0 +output=console + +[testsys.sim_console.listener] +type=ConsoleListener +port=3456 + +[testsys.simple_disk] +type=SimpleDisk +children=disk +disk=testsys.simple_disk.disk +system=testsys + +[testsys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.tsunami] +type=Tsunami +children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=testsys.intrctrl +system=testsys + +[testsys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami +pio=testsys.iobus.port[1] + +[testsys.tsunami.console] +type=AlphaConsole +cpu=testsys.cpu +disk=testsys.simple_disk +pio_addr=8804682956800 +pio_latency=1000 +platform=testsys.tsunami +sim_console=testsys.sim_console +system=testsys +pio=testsys.iobus.port[25] + +[testsys.tsunami.etherint] +type=NSGigEInt +device=testsys.tsunami.ethernet +peer=Null + +[testsys.tsunami.ethernet] +type=NSGigE +children=configdata +clock=0 +config_latency=20000 +configdata=testsys.tsunami.ethernet.configdata +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:02 +intr_delay=10000000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=testsys.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=testsys +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=testsys.iobus.port[28] +dma=testsys.iobus.port[29] +pio=testsys.iobus.port[27] + +[testsys.tsunami.ethernet.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=256 +BAR1=0 +BAR1Size=4096 +BAR2=0 +BAR2Size=0 +BAR3=0 +BAR3Size=0 +BAR4=0 +BAR4Size=0 +BAR5=0 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 + +[testsys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[9] + +[testsys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[20] + +[testsys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[21] + +[testsys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[10] + +[testsys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[12] + +[testsys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[13] + +[testsys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[14] + +[testsys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[15] + +[testsys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[16] + +[testsys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[17] + +[testsys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[18] + +[testsys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[19] + +[testsys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[11] + +[testsys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[8] + +[testsys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[3] + +[testsys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[4] + +[testsys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[5] + +[testsys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[6] + +[testsys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +platform=testsys.tsunami +ret_bad_addr=false +ret_data=255 +system=testsys +pio=testsys.iobus.port[7] + +[testsys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +pio=testsys.iobus.port[22] + +[testsys.tsunami.ide] +type=IdeController +children=configdata +config_latency=20000 +configdata=testsys.tsunami.ide.configdata +disks=testsys.disk0 testsys.disk2 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +config=testsys.iobus.port[30] +dma=testsys.iobus.port[31] +pio=testsys.iobus.port[26] + +[testsys.tsunami.ide.configdata] +type=PciConfigData +BAR0=1 +BAR0Size=8 +BAR1=1 +BAR1Size=4 +BAR2=1 +BAR2Size=8 +BAR3=1 +BAR3Size=4 +BAR4=1 +BAR4Size=16 +BAR5=1 +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 + +[testsys.tsunami.io] +type=TsunamiIO +frequency=976562500 +pio_addr=8804615847936 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +time=1136073600 +tsunami=testsys.tsunami +pio=testsys.iobus.port[23] + +[testsys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami +pio=testsys.iobus.port[2] + +[testsys.tsunami.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=testsys.tsunami +size=16777216 +system=testsys +pio=testsys.iobus.default + +[testsys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=testsys.tsunami +sim_console=testsys.sim_console +system=testsys +pio=testsys.iobus.port[24] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out new file mode 100644 index 000000000..19bb5af44 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -0,0 +1,1101 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[testsys.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[testsys] +type=LinuxAlphaSystem +boot_cpu_frequency=1 +physmem=testsys.physmem +mem_mode=atomic +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal +boot_osflags=root=/dev/hda1 console=ttyS0 +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-stream-client.rcS +symbolfile= +init_param=0 +system_type=34 +system_rev=1024 + +[testsys.cpu.itb] +type=AlphaITB +size=48 + +[testsys.cpu.dtb] +type=AlphaDTB +size=64 + +[testsys.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=testsys +cpu_id=0 +itb=testsys.cpu.itb +dtb=testsys.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[testsys.intrctrl] +type=IntrControl +cpu=testsys.cpu + +[testsys.tsunami] +type=Tsunami +system=testsys +intrctrl=testsys.intrctrl + +[testsys.tsunami.ethernet.configdata] +type=PciConfigData +VendorID=4107 +DeviceID=34 +Command=0 +Status=656 +Revision=0 +ProgIF=0 +SubClassCode=0 +ClassCode=2 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=0 +BAR2=0 +BAR3=0 +BAR4=0 +BAR5=0 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=30 +InterruptPin=1 +MinimumGrant=176 +MaximumLatency=52 +BAR0Size=256 +BAR1Size=4096 +BAR2Size=0 +BAR3Size=0 +BAR4Size=0 +BAR5Size=0 + +[testsys.tsunami.ethernet] +type=NSGigE +system=testsys +platform=testsys.tsunami +configdata=testsys.tsunami.ethernet.configdata +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +config_latency=20000 +clock=0 +dma_desc_free=false +dma_data_free=false +dma_read_delay=0 +dma_write_delay=0 +dma_read_factor=0 +dma_write_factor=0 +dma_no_allocate=true +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 +rx_fifo_size=524288 +tx_fifo_size=524288 +rx_filter=true +hardware_address=00:90:00:00:00:02 +rx_thread=false +tx_thread=false +rss=false + +[testsys.tsunami.etherint] +type=NSGigEInt +peer=null +device=testsys.tsunami.ethernet + +[drivesys.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[drivesys] +type=LinuxAlphaSystem +boot_cpu_frequency=1 +physmem=drivesys.physmem +mem_mode=atomic +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal +boot_osflags=root=/dev/hda1 console=ttyS0 +readfile=/z/hsul/work/m5/newmem/configs/boot/netperf-server.rcS +symbolfile= +init_param=0 +system_type=34 +system_rev=1024 + +[drivesys.cpu.itb] +type=AlphaITB +size=48 + +[drivesys.cpu.dtb] +type=AlphaDTB +size=64 + +[drivesys.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=drivesys +cpu_id=0 +itb=drivesys.cpu.itb +dtb=drivesys.cpu.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[drivesys.intrctrl] +type=IntrControl +cpu=drivesys.cpu + +[drivesys.tsunami] +type=Tsunami +system=drivesys +intrctrl=drivesys.intrctrl + +[drivesys.tsunami.ethernet.configdata] +type=PciConfigData +VendorID=4107 +DeviceID=34 +Command=0 +Status=656 +Revision=0 +ProgIF=0 +SubClassCode=0 +ClassCode=2 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=0 +BAR2=0 +BAR3=0 +BAR4=0 +BAR5=0 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=30 +InterruptPin=1 +MinimumGrant=176 +MaximumLatency=52 +BAR0Size=256 +BAR1Size=4096 +BAR2Size=0 +BAR3Size=0 +BAR4Size=0 +BAR5Size=0 + +[drivesys.tsunami.ethernet] +type=NSGigE +system=drivesys +platform=drivesys.tsunami +configdata=drivesys.tsunami.ethernet.configdata +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +config_latency=20000 +clock=0 +dma_desc_free=false +dma_data_free=false +dma_read_delay=0 +dma_write_delay=0 +dma_read_factor=0 +dma_write_factor=0 +dma_no_allocate=true +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 +rx_fifo_size=524288 +tx_fifo_size=524288 +rx_filter=true +hardware_address=00:90:00:00:00:02 +rx_thread=false +tx_thread=false +rss=false + +[drivesys.tsunami.etherint] +type=NSGigEInt +peer=null +device=drivesys.tsunami.ethernet + +[etherdump] +type=EtherDump +file=ethertrace +maxlen=96 + +[etherlink] +type=EtherLink +int1=testsys.tsunami.etherint +int2=drivesys.tsunami.etherint +speed=8000 +delay=0 +delay_var=0 +dump=etherdump + +[testsys.membus] +type=Bus +bus_id=1 +clock=1000 +width=64 +responder_set=false + +[testsys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.bridge] +type=Bridge +queue_size_a=16 +queue_size_b=16 +delay=0 +write_ack=false + +[testsys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.disk0.image] +type=CowDiskImage +child=testsys.disk0.image.child +image_file= +table_size=65536 +read_only=false + +[testsys.disk0] +type=IdeDisk +image=testsys.disk0.image +driveID=master +delay=1000000 + +[testsys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[testsys.disk2.image] +type=CowDiskImage +child=testsys.disk2.image.child +image_file= +table_size=65536 +read_only=false + +[testsys.disk2] +type=IdeDisk +image=testsys.disk2.image +driveID=master +delay=1000000 + +[testsys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[testsys.simple_disk] +type=SimpleDisk +system=testsys +disk=testsys.simple_disk.disk + +[testsys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami + +[testsys.tsunami.io] +type=TsunamiIO +pio_addr=8804615847936 +pio_latency=1000 +frequency=976562500 +platform=testsys.tsunami +system=testsys +time=1136073600 +tsunami=testsys.tsunami + +[] +type=PciConfigAll +pio_latency=1 +bus=0 +size=16777216 +platform=testsys.tsunami +system=testsys + +[testsys.sim_console.listener] +type=ConsoleListener +port=3456 + +[testsys.sim_console] +type=SimConsole +listener=testsys.sim_console.listener +intr_control=testsys.intrctrl +output=console +append_name=true +number=0 + +[testsys.tsunami.console] +type=AlphaConsole +sim_console=testsys.sim_console +disk=testsys.simple_disk +pio_addr=8804682956800 +system=testsys +cpu=testsys.cpu +platform=testsys.tsunami +pio_latency=1000 + +[testsys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +tsunami=testsys.tsunami + +[testsys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +system=testsys +platform=testsys.tsunami +pio_latency=1000 + +[testsys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=testsys.tsunami +sim_console=testsys.sim_console +system=testsys + +[testsys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=testsys.tsunami +system=testsys + +[testsys.tsunami.ide.configdata] +type=PciConfigData +VendorID=32902 +DeviceID=28945 +Command=0 +Status=640 +Revision=0 +ProgIF=133 +SubClassCode=1 +ClassCode=1 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=1 +BAR2=1 +BAR3=1 +BAR4=1 +BAR5=1 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=31 +InterruptPin=1 +MinimumGrant=0 +MaximumLatency=0 +BAR0Size=8 +BAR1Size=4 +BAR2Size=8 +BAR3Size=4 +BAR4Size=16 +BAR5Size=0 + +[testsys.tsunami.ide] +type=IdeController +system=testsys +platform=testsys.tsunami +configdata=testsys.tsunami.ide.configdata +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +config_latency=20000 +disks=testsys.disk0 testsys.disk2 + +[testsys.iobus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=true + +[drivesys.membus] +type=Bus +bus_id=1 +clock=1000 +width=64 +responder_set=false + +[drivesys.membus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.bridge] +type=Bridge +queue_size_a=16 +queue_size_b=16 +delay=0 +write_ack=false + +[drivesys.disk0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.disk0.image] +type=CowDiskImage +child=drivesys.disk0.image.child +image_file= +table_size=65536 +read_only=false + +[drivesys.disk0] +type=IdeDisk +image=drivesys.disk0.image +driveID=master +delay=1000000 + +[drivesys.disk2.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[drivesys.disk2.image] +type=CowDiskImage +child=drivesys.disk2.image.child +image_file= +table_size=65536 +read_only=false + +[drivesys.disk2] +type=IdeDisk +image=drivesys.disk2.image +driveID=master +delay=1000000 + +[drivesys.simple_disk.disk] +type=RawDiskImage +image_file=/dist/m5/system/disks/myimg.img +read_only=true + +[drivesys.simple_disk] +type=SimpleDisk +system=drivesys +disk=drivesys.simple_disk.disk + +[drivesys.tsunami.fake_uart1] +type=IsaFake +pio_addr=8804615848696 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_uart2] +type=IsaFake +pio_addr=8804615848936 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_uart3] +type=IsaFake +pio_addr=8804615848680 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_uart4] +type=IsaFake +pio_addr=8804615848944 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_ppc] +type=IsaFake +pio_addr=8804615848892 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.cchip] +type=TsunamiCChip +pio_addr=8803072344064 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami + +[drivesys.tsunami.io] +type=TsunamiIO +pio_addr=8804615847936 +pio_latency=1000 +frequency=976562500 +platform=drivesys.tsunami +system=drivesys +time=1136073600 +tsunami=drivesys.tsunami + +[] +type=PciConfigAll +pio_latency=1 +bus=0 +size=16777216 +platform=drivesys.tsunami +system=drivesys + +[drivesys.sim_console.listener] +type=ConsoleListener +port=3456 + +[drivesys.sim_console] +type=SimConsole +listener=drivesys.sim_console.listener +intr_control=drivesys.intrctrl +output=console +append_name=true +number=0 + +[drivesys.tsunami.console] +type=AlphaConsole +sim_console=drivesys.sim_console +disk=drivesys.simple_disk +pio_addr=8804682956800 +system=drivesys +cpu=drivesys.cpu +platform=drivesys.tsunami +pio_latency=1000 + +[drivesys.tsunami.fake_ata1] +type=IsaFake +pio_addr=8804615848304 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_ata0] +type=IsaFake +pio_addr=8804615848432 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.pchip] +type=TsunamiPChip +pio_addr=8802535473152 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +tsunami=drivesys.tsunami + +[drivesys.tsunami.fake_pnp_read3] +type=IsaFake +pio_addr=8804615848643 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read2] +type=IsaFake +pio_addr=8804615848579 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read1] +type=IsaFake +pio_addr=8804615848515 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read0] +type=IsaFake +pio_addr=8804615848451 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read7] +type=IsaFake +pio_addr=8804615848899 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read6] +type=IsaFake +pio_addr=8804615848835 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read5] +type=IsaFake +pio_addr=8804615848771 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_read4] +type=IsaFake +pio_addr=8804615848707 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_write] +type=IsaFake +pio_addr=8804615850617 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fb] +type=BadDevice +devicename=FrameBuffer +pio_addr=8804615848912 +system=drivesys +platform=drivesys.tsunami +pio_latency=1000 + +[drivesys.tsunami.fake_OROM] +type=IsaFake +pio_addr=8796093677568 +pio_latency=1000 +pio_size=393216 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.uart] +type=Uart8250 +pio_addr=8804615848952 +pio_latency=1000 +platform=drivesys.tsunami +sim_console=drivesys.sim_console +system=drivesys + +[drivesys.tsunami.fake_sm_chip] +type=IsaFake +pio_addr=8804615848816 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.fake_pnp_addr] +type=IsaFake +pio_addr=8804615848569 +pio_latency=1000 +pio_size=8 +ret_bad_addr=false +ret_data=255 +platform=drivesys.tsunami +system=drivesys + +[drivesys.tsunami.ide.configdata] +type=PciConfigData +VendorID=32902 +DeviceID=28945 +Command=0 +Status=640 +Revision=0 +ProgIF=133 +SubClassCode=1 +ClassCode=1 +CacheLineSize=0 +LatencyTimer=0 +HeaderType=0 +BIST=0 +BAR0=1 +BAR1=1 +BAR2=1 +BAR3=1 +BAR4=1 +BAR5=1 +CardbusCIS=0 +SubsystemVendorID=0 +SubsystemID=0 +ExpansionROM=0 +InterruptLine=31 +InterruptPin=1 +MinimumGrant=0 +MaximumLatency=0 +BAR0Size=8 +BAR1Size=4 +BAR2Size=8 +BAR3Size=4 +BAR4Size=16 +BAR5Size=0 + +[drivesys.tsunami.ide] +type=IdeController +system=drivesys +platform=drivesys.tsunami +configdata=drivesys.tsunami.ide.configdata +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +config_latency=20000 +disks=drivesys.disk0 drivesys.disk2 + +[drivesys.iobus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=true + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +legion_lockstep=false +trace_system=client + +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console new file mode 100644 index 000000000..931411c03 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console @@ -0,0 +1,111 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 +
Got Configuration 623 +
memsize 8000000 pages 4000 +
First free page after ROM 0xFFFFFC0000018000 +
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 +
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 +
CPU Clock at 1000000 MHz IntrClockFrequency=1024 +
Booting with 1 processor(s) +
KSP: 0x20043FE8 PTBR 0x20 +
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 +
Memory cluster 0 [0 - 392] +
Memory cluster 1 [392 - 15992] +
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 +
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 +
unix_boot_mem ends at FFFFFC0000076000 +
k_argc = 0 +
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) +
CallbackFixup 0 18000, t7=FFFFFC000070C000 +
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 +
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM +
Major Options: SMP LEGACY_START VERBOSE_MCHECK +
Command line: root=/dev/hda1 console=ttyS0 +
memcluster 0, usage 1, start 0, end 392 +
memcluster 1, usage 0, start 392, end 16384 +
freeing pages 1069:16384 +
reserving pages 1069:1070 +
SMP: 1 CPUs probed -- cpu_present_mask = 1 +
Built 1 zonelists +
Kernel command line: root=/dev/hda1 console=ttyS0 +
PID hash table entries: 1024 (order: 10, 32768 bytes) +
Using epoch = 1900 +
Console: colour dummy device 80x25 +
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) +
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) +
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) +
Mount-cache hash table entries: 512 +
SMP mode deactivated. +
Brought up 1 CPUs +
SMP: Total of 1 processors activated (1998756.81 BogoMIPS). +
NET: Registered protocol family 16 +
EISA bus registered +
pci: enabling save/restore of SRM state +
SCSI subsystem initialized +
srm_env: version 0.0.5 loaded successfully +
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +
Initializing Cryptographic API +
rtc: Standard PC (1900) epoch (1900) detected +
Real Time Clock Driver v1.12 +
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled +
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 +
io scheduler noop registered +
io scheduler anticipatory registered +
io scheduler deadline registered +
io scheduler cfq registered +
loop: loaded (max 8 devices) +
nbd: registered device at major 43 +
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 +
eth0: enabling optical transceiver +
eth0: using 64 bit addressing. +
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg +
tun: Universal TUN/TAP device driver, 1.6 +
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> +
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 +
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +
PIIX4: IDE controller at PCI slot 0000:00:00.0 +
PIIX4: chipset revision 0 +
PIIX4: 100% native mode on irq 31 +
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA +
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA +
hda: M5 IDE Disk, ATA DISK drive +
hdb: M5 IDE Disk, ATA DISK drive +
ide0 at 0x8410-0x8417,0x8422 on irq 31 +
hda: max request size: 128KiB +
hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33) +
hda: cache flushes not supported +
hda: hda1 +
hdb: max request size: 128KiB +
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) +
hdb: cache flushes not supported +
hdb: unknown partition table +
mice: PS/2 mouse device common for all mice +
NET: Registered protocol family 2 +
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) +
TCP established hash table entries: 16384 (order: 5, 262144 bytes) +
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) +
TCP: Hash tables configured (established 16384 bind 16384) +
TCP reno registered +
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack +
ip_tables: (C) 2000-2002 Netfilter core team +
arp_tables: (C) 2002 David S. Miller +
TCP bic registered +
Initializing IPsec netlink socket +
NET: Registered protocol family 1 +
NET: Registered protocol family 17 +
NET: Registered protocol family 15 +
Bridge firewalling registered +
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> +
All bugs added by David S. Miller <davem@redhat.com> +
VFS: Mounted root (ext2 filesystem) readonly. +
Freeing unused kernel memory: 224k freed +
init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary +mounting filesystems... +loading script... +setting up network... +eth0: link now 1000F mbps, full duplex and up. +
running netserver... +Starting netserver at port 12865 +signal client to begin...done. +starting bash... +#
\ No newline at end of file diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console new file mode 100644 index 000000000..aea9af01d --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console @@ -0,0 +1,120 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 +
Got Configuration 623 +
memsize 8000000 pages 4000 +
First free page after ROM 0xFFFFFC0000018000 +
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 +
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 +
CPU Clock at 1000000 MHz IntrClockFrequency=1024 +
Booting with 1 processor(s) +
KSP: 0x20043FE8 PTBR 0x20 +
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 +
Memory cluster 0 [0 - 392] +
Memory cluster 1 [392 - 15992] +
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 +
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 +
unix_boot_mem ends at FFFFFC0000076000 +
k_argc = 0 +
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) +
CallbackFixup 0 18000, t7=FFFFFC000070C000 +
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 +
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM +
Major Options: SMP LEGACY_START VERBOSE_MCHECK +
Command line: root=/dev/hda1 console=ttyS0 +
memcluster 0, usage 1, start 0, end 392 +
memcluster 1, usage 0, start 392, end 16384 +
freeing pages 1069:16384 +
reserving pages 1069:1070 +
SMP: 1 CPUs probed -- cpu_present_mask = 1 +
Built 1 zonelists +
Kernel command line: root=/dev/hda1 console=ttyS0 +
PID hash table entries: 1024 (order: 10, 32768 bytes) +
Using epoch = 1900 +
Console: colour dummy device 80x25 +
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) +
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) +
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) +
Mount-cache hash table entries: 512 +
SMP mode deactivated. +
Brought up 1 CPUs +
SMP: Total of 1 processors activated (1998756.81 BogoMIPS). +
NET: Registered protocol family 16 +
EISA bus registered +
pci: enabling save/restore of SRM state +
SCSI subsystem initialized +
srm_env: version 0.0.5 loaded successfully +
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +
Initializing Cryptographic API +
rtc: Standard PC (1900) epoch (1900) detected +
Real Time Clock Driver v1.12 +
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled +
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 +
io scheduler noop registered +
io scheduler anticipatory registered +
io scheduler deadline registered +
io scheduler cfq registered +
loop: loaded (max 8 devices) +
nbd: registered device at major 43 +
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 +
eth0: enabling optical transceiver +
eth0: using 64 bit addressing. +
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg +
tun: Universal TUN/TAP device driver, 1.6 +
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> +
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 +
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +
PIIX4: IDE controller at PCI slot 0000:00:00.0 +
PIIX4: chipset revision 0 +
PIIX4: 100% native mode on irq 31 +
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA +
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA +
hda: M5 IDE Disk, ATA DISK drive +
hdb: M5 IDE Disk, ATA DISK drive +
ide0 at 0x8410-0x8417,0x8422 on irq 31 +
hda: max request size: 128KiB +
hda: 409248 sectors (209 MB), CHS=406/16/63, UDMA(33) +
hda: cache flushes not supported +
hda: hda1 +
hdb: max request size: 128KiB +
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) +
hdb: cache flushes not supported +
hdb: unknown partition table +
mice: PS/2 mouse device common for all mice +
NET: Registered protocol family 2 +
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) +
TCP established hash table entries: 16384 (order: 5, 262144 bytes) +
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) +
TCP: Hash tables configured (established 16384 bind 16384) +
TCP reno registered +
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack +
ip_tables: (C) 2000-2002 Netfilter core team +
arp_tables: (C) 2002 David S. Miller +
TCP bic registered +
Initializing IPsec netlink socket +
NET: Registered protocol family 1 +
NET: Registered protocol family 17 +
NET: Registered protocol family 15 +
Bridge firewalling registered +
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> +
All bugs added by David S. Miller <davem@redhat.com> +
VFS: Mounted root (ext2 filesystem) readonly. +
Freeing unused kernel memory: 224k freed +
init started: BusyBox v1.1.0 (2006.10.31-01:25+0000) multi-call binary +mounting filesystems... +loading script... +setting up network... +eth0: link now 1000F mbps, full duplex and up. +
waiting for server...server ready +starting test... +netperf warmup +/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k +TCP STREAM TEST to 10.0.0.1 : dirty data +Recv Send Send +Socket Socket Message Elapsed +Size Size Size Time Throughput +bytes bytes bytes secs. 10^6bits/sec + +5000000 5000000 5000000 1.29 30.91 +netperf benchmark +/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144 +TCP STREAM TEST to 10.0.0.1 : dirty data diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt new file mode 100644 index 000000000..328846907 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -0,0 +1,476 @@ + +---------- Begin Simulation Statistics ---------- +drivesys.cpu.dtb.accesses 401302 # DTB accesses +drivesys.cpu.dtb.acv 40 # DTB access violations +drivesys.cpu.dtb.hits 624298 # DTB hits +drivesys.cpu.dtb.misses 569 # DTB misses +drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses +drivesys.cpu.dtb.read_acv 30 # DTB read access violations +drivesys.cpu.dtb.read_hits 393538 # DTB read hits +drivesys.cpu.dtb.read_misses 487 # DTB read misses +drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses +drivesys.cpu.dtb.write_acv 10 # DTB write access violations +drivesys.cpu.dtb.write_hits 230760 # DTB write hits +drivesys.cpu.dtb.write_misses 82 # DTB write misses +drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles +drivesys.cpu.itb.accesses 1337980 # ITB accesses +drivesys.cpu.itb.acv 22 # ITB acv +drivesys.cpu.itb.hits 1337786 # ITB hits +drivesys.cpu.itb.misses 194 # ITB misses +drivesys.cpu.kern.callpal 4443 # number of callpals executed +drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed +drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed +drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed +drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed +drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed +drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed +drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed +drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed +drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed +drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed +drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed +drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks 199572064366 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199571744403 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.mode_good_kernel 110 +drivesys.cpu.kern.mode_good_user 107 +drivesys.cpu.kern.mode_good_idle 3 +drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches +drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches +drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 106483912 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed +drivesys.cpu.kern.syscall 22 # number of syscalls executed +drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed +drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed +drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed +drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed +drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed +drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed +drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed +drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed +drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed +drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed +drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed +drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles +drivesys.cpu.numCycles 1959293 # number of cpu cycles simulated +drivesys.cpu.num_insts 1959077 # Number of instructions executed +drivesys.cpu.num_refs 626286 # Number of memory references +drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. +drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA +drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +drivesys.tsunami.ethernet.postedRxDesc 6 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 4 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +drivesys.tsunami.ethernet.rxBandwidth 38400 # Receive Bandwidth (bits/s) +drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received +drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device +drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) +drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received +drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device +drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device +drivesys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) +drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes +drivesys.tsunami.ethernet.totPackets 13 # Total Packets +drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR +drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) +drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted +drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device +drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) +drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted +drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device +drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +host_inst_rate 38374803 # Simulator instruction rate (inst/s) +host_mem_usage 411180 # Number of bytes of host memory used +host_seconds 7.20 # Real time elapsed on the host +host_tick_rate 27794359444 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 276122825 # Number of instructions simulated +sim_seconds 0.200001 # Number of seconds simulated +sim_ticks 200000789468 # Number of ticks simulated +testsys.cpu.dtb.accesses 335402 # DTB accesses +testsys.cpu.dtb.acv 161 # DTB access violations +testsys.cpu.dtb.hits 1163399 # DTB hits +testsys.cpu.dtb.misses 3815 # DTB misses +testsys.cpu.dtb.read_accesses 225414 # DTB read accesses +testsys.cpu.dtb.read_acv 80 # DTB read access violations +testsys.cpu.dtb.read_hits 658556 # DTB read hits +testsys.cpu.dtb.read_misses 3287 # DTB read misses +testsys.cpu.dtb.write_accesses 109988 # DTB write accesses +testsys.cpu.dtb.write_acv 81 # DTB write access violations +testsys.cpu.dtb.write_hits 504843 # DTB write hits +testsys.cpu.dtb.write_misses 528 # DTB write misses +testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles +testsys.cpu.itb.accesses 1249804 # ITB accesses +testsys.cpu.itb.acv 69 # ITB acv +testsys.cpu.itb.hits 1248307 # ITB hits +testsys.cpu.itb.misses 1497 # ITB misses +testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal_swpctx 440 3.35% 3.35% # number of callpals executed +testsys.cpu.kern.callpal_tbi 20 0.15% 3.51% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11075 84.39% 87.89% # number of callpals executed +testsys.cpu.kern.callpal_rdps 359 2.74% 90.63% # number of callpals executed +testsys.cpu.kern.callpal_wrusp 3 0.02% 90.65% # number of callpals executed +testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed +testsys.cpu.kern.callpal_rti 1040 7.92% 98.60% # number of callpals executed +testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed +testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed +testsys.cpu.kern.inst.arm 0 # number of arm instructions executed +testsys.cpu.kern.inst.hwrei 19054 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12503 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_21 183 1.46% 41.94% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7054 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_good 10498 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks 199569923608 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569308038 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used 0.839638 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 654 +testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.mode_good_idle 5 +testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 0.614085 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.594545 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1821232 2.16% 2.16% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 81402474 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 440 # number of times the context was actually changed +testsys.cpu.kern.syscall 83 # number of syscalls executed +testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed +testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed +testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed +testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed +testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed +testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed +testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed +testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed +testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed +testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed +testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed +testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed +testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed +testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed +testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed +testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed +testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed +testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed +testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed +testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed +testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed +testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles +testsys.cpu.numCycles 3566237 # number of cpu cycles simulated +testsys.cpu.num_insts 3564671 # Number of instructions executed +testsys.cpu.num_refs 1173698 # Number of memory references +testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. +testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA +testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU +testsys.tsunami.ethernet.postedRxDesc 4 # number of RxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 6 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +testsys.tsunami.ethernet.rxBandwidth 31920 # Receive Bandwidth (bits/s) +testsys.tsunami.ethernet.rxBytes 798 # Bytes Received +testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device +testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) +testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received +testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device +testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device +testsys.tsunami.ethernet.totBandwidth 70320 # Total Bandwidth (bits/s) +testsys.tsunami.ethernet.totBytes 1758 # Total Bytes +testsys.tsunami.ethernet.totPackets 13 # Total Packets +testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR +testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) +testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted +testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device +testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) +testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted +testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device +testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device + +---------- End Simulation Statistics ---------- + +---------- Begin Simulation Statistics ---------- +drivesys.cpu.dtb.accesses 0 # DTB accesses +drivesys.cpu.dtb.acv 0 # DTB access violations +drivesys.cpu.dtb.hits 0 # DTB hits +drivesys.cpu.dtb.misses 0 # DTB misses +drivesys.cpu.dtb.read_accesses 0 # DTB read accesses +drivesys.cpu.dtb.read_acv 0 # DTB read access violations +drivesys.cpu.dtb.read_hits 0 # DTB read hits +drivesys.cpu.dtb.read_misses 0 # DTB read misses +drivesys.cpu.dtb.write_accesses 0 # DTB write accesses +drivesys.cpu.dtb.write_acv 0 # DTB write access violations +drivesys.cpu.dtb.write_hits 0 # DTB write hits +drivesys.cpu.dtb.write_misses 0 # DTB write misses +drivesys.cpu.idle_fraction 1 # Percentage of idle cycles +drivesys.cpu.itb.accesses 0 # ITB accesses +drivesys.cpu.itb.acv 0 # ITB acv +drivesys.cpu.itb.hits 0 # ITB hits +drivesys.cpu.itb.misses 0 # ITB misses +drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed +drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed +drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +drivesys.cpu.kern.mode_good_kernel 0 +drivesys.cpu.kern.mode_good_user 0 +drivesys.cpu.kern.mode_good_idle 0 +drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed +drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles +drivesys.cpu.numCycles 0 # number of cpu cycles simulated +drivesys.cpu.num_insts 0 # Number of instructions executed +drivesys.cpu.num_refs 0 # Number of memory references +drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. +drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. +drivesys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +host_inst_rate 76361400719 # Simulator instruction rate (inst/s) +host_mem_usage 411180 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host +host_tick_rate 203621244 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 276122825 # Number of instructions simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 785978 # Number of ticks simulated +testsys.cpu.dtb.accesses 0 # DTB accesses +testsys.cpu.dtb.acv 0 # DTB access violations +testsys.cpu.dtb.hits 0 # DTB hits +testsys.cpu.dtb.misses 0 # DTB misses +testsys.cpu.dtb.read_accesses 0 # DTB read accesses +testsys.cpu.dtb.read_acv 0 # DTB read access violations +testsys.cpu.dtb.read_hits 0 # DTB read hits +testsys.cpu.dtb.read_misses 0 # DTB read misses +testsys.cpu.dtb.write_accesses 0 # DTB write accesses +testsys.cpu.dtb.write_acv 0 # DTB write access violations +testsys.cpu.dtb.write_hits 0 # DTB write hits +testsys.cpu.dtb.write_misses 0 # DTB write misses +testsys.cpu.idle_fraction 1 # Percentage of idle cycles +testsys.cpu.itb.accesses 0 # ITB accesses +testsys.cpu.itb.acv 0 # ITB acv +testsys.cpu.itb.hits 0 # ITB hits +testsys.cpu.itb.misses 0 # ITB misses +testsys.cpu.kern.inst.arm 0 # number of arm instructions executed +testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +testsys.cpu.kern.mode_good_kernel 0 +testsys.cpu.kern.mode_good_user 0 +testsys.cpu.kern.mode_good_idle 0 +testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 0 # number of times the context was actually changed +testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles +testsys.cpu.numCycles 0 # number of cpu cycles simulated +testsys.cpu.num_insts 0 # Number of instructions executed +testsys.cpu.num_refs 0 # Number of memory references +testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. +testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. +testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. +testsys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped +testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr new file mode 100644 index 000000000..3aa8423b9 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -0,0 +1,8 @@ + 0: testsys.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 +Listening for console connection on port 3456 + 0: drivesys.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 +Listening for console connection on port 3457 +0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 +warn: Entering event queue @ 0. Starting simulation... +warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout new file mode 100644 index 000000000..765e59472 --- /dev/null +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Nov 29 2006 16:48:25 +M5 started Fri Dec 1 01:07:49 2006 +M5 executing on zed.eecs.umich.edu +command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py long/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +WTF +9685900: testsys.sim_console: attach console 0 +3327958029: drivesys.sim_console: attach console 0 +Resetting stats at cycle 4100234765800! +Resetting stats at cycle 4300235555268! +Exiting @ tick 4300236341246 because checkpoint diff --git a/tests/quick/80.netperf-stream/test.py b/tests/quick/80.netperf-stream/test.py new file mode 100644 index 000000000..1da47fca4 --- /dev/null +++ b/tests/quick/80.netperf-stream/test.py @@ -0,0 +1,28 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + diff --git a/util/make_release.py b/util/make_release.py new file mode 100755 index 000000000..d1161166d --- /dev/null +++ b/util/make_release.py @@ -0,0 +1,155 @@ +#!/usr/bin/env python +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi +# Steve Reinhardt +# Nathan Binkert + +import os +import re +import shutil +import sys + +from glob import glob +from os import system +from os.path import basename, dirname, exists, isdir, isfile, join as joinpath + +def mkdir(*args): + path = joinpath(*args) + os.mkdir(path) + +def touch(*args): + path = joinpath(*args) + os.utime(path, None) + +def rmtree(*args): + path = joinpath(*args) + for match in glob(path): + if isdir(match): + shutil.rmtree(match) + else: + os.unlink(match) + +def remove(*args): + path = joinpath(*args) + for match in glob(path): + if not isdir(match): + os.unlink(match) + +def movedir(srcdir, destdir, dir): + src = joinpath(srcdir, dir) + dest = joinpath(destdir, dir) + + if not isdir(src): + raise AttributeError + + os.makedirs(dirname(dest)) + shutil.move(src, dest) + +if not isdir('BitKeeper'): + sys.exit('Not in the top level of an m5 tree!') + +usage = '%s <destdir> <release name>' % sys.argv[0] + +if len(sys.argv) != 3: + sys.exit(usage) + +destdir = sys.argv[1] +releasename = sys.argv[2] + +if exists(destdir): + if not isdir(destdir): + raise AttributeError, '%s exists, but is not a directory' % destdir + rmtree(destdir) + +release_dir = joinpath(destdir, 'release', releasename) +encumbered_dir = joinpath(destdir, 'encumbered', releasename) + +mkdir(destdir) +mkdir(destdir, 'release') +mkdir(destdir, 'encumbered') +mkdir(release_dir) +mkdir(encumbered_dir) + +system('bk export -tplain -w -r+ %s' % release_dir) + +# make sure scons doesn't try to run flex unnecessarily +touch(release_dir, 'src/encumbered/eio/exolex.cc') + +# get rid of non-shipping code +rmtree(release_dir, 'src/encumbered/dev') +rmtree(release_dir, 'src/cpu/ozone') +rmtree(release_dir, 'src/mem/cache/tags/split*.cc') +rmtree(release_dir, 'src/mem/cache/tags/split*.hh') +rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc') +rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh') +rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc') +rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh') +rmtree(release_dir, 'src/oldmem') +rmtree(release_dir, 'configs/fullsys') +rmtree(release_dir, 'configs/test') +rmtree(release_dir, 'configs/splash2') +rmtree(release_dir, 'tests/long/*/ref') +rmtree(release_dir, 'tests/old') + +# get rid of some of private scripts +remove(release_dir, 'util/chgcopyright') +remove(release_dir, 'util/make_release.py') + +# fix up the SConscript to deal with files we've removed +mem_expr = re.compile('.*mem/cache/(tags/split|prefetch/(ghb|stride)).*') +inscript = file(joinpath(release_dir, 'src', 'SConscript'), 'r').readlines() +outscript = file(joinpath(release_dir, 'src', 'SConscript'), 'w') +for line in inscript: + if mem_expr.match(line): + continue + + outscript.write(line) +outscript.close() + +benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', + 'twolf', 'vortex' ] +for bench in benches: + rmtree(release_dir, 'tests', 'test-progs', bench) + +movedir(release_dir, encumbered_dir, 'src/encumbered') +movedir(release_dir, encumbered_dir, 'tests/test-progs/anagram') +movedir(release_dir, encumbered_dir, 'tests/quick/20.eio-short') + +def taritup(directory, destdir, filename): + basedir = dirname(directory) + tarball = joinpath(destdir, filename) + tardir = basename(directory) + + system('cd %s; tar cfj %s %s' % (basedir, tarball, tardir)) + +taritup(release_dir, destdir, '%s.tar.bz2' % releasename) +taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename) + +print "release created in %s" % destdir +print "don't forget to tag the repository! The following command will do it:" +print "bk tag %s" % releasename |