diff options
| -rw-r--r-- | README | 2 | ||||
| -rw-r--r-- | RELEASE_NOTES | 16 | ||||
| -rwxr-xr-x | util/make_release.py | 7 |
3 files changed, 22 insertions, 3 deletions
@@ -1,4 +1,4 @@ -This is release 2.0_beta4 of the M5 simulator. +This is release 2.0_beta5 of the M5 simulator. For detailed information about building the simulator and getting started please refer to http://www.m5sim.org. diff --git a/RELEASE_NOTES b/RELEASE_NOTES index cd62fb86b..ad0278b89 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -9,6 +9,22 @@ Outstanding issues for 2.0 release: 7. Testing 8. Validation +March 1, 2008: m5_2.0_beta5 +-------------------- +New Features +1. Rick Strong's Simpoints config changes +2. Support for FSU ARM port +3. EXTRAS= option allow architectures to be specified + +Bug fixes +1. Bus timing more realistic +2. Cache writeback, LL/SC fixes +3. Minor IGbE NIC fixes +4. O3 op latency fix +5. SPARC TLB demap fixes +6. SPARC SE memory layout fixes +7. Variety of MIPS fixes + Nov 4, 2007: m5_2.0_beta4 -------------------- New Features diff --git a/util/make_release.py b/util/make_release.py index 5ed23e594..7c68feeba 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2006-2008 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -211,14 +211,17 @@ remove_lines(r'.*X86.*', None, 'AUTHORS') remove_lines(r'.*X86.*', None, 'src/base/loader/object_file.hh') remove_lines(r'.*_X86_.*', '.*else.*', 'src/base/loader/elf_object.cc') remove_lines(r'.*X86_ISA.*', r'^.el.*','src/sim/process.cc') +remove_lines(r".*'x86' and build.*", None, 'src/cpu/BaseCPU.py') +remove_lines(r".*walker.port.*", None, 'src/cpu/BaseCPU.py') remove_lines(r'.*x86.*', r'.*mips.*','src/cpu/BaseCPU.py') -remove_lines(r'.*X86_ISA.*', r'^.*else.*','src/cpu/o3/dyn_inst.hh') +remove_lines(r'.*X86_ISA.*', r'^.*elif.*','src/cpu/o3/dyn_inst.hh') remove_lines(r'.*X86_ISA.*', r'.*stay.*','src/cpu/simple/base.cc') remove_lines(r'.*x86.*', r'^if.*','src/cpu/SConscript') remove_lines(r'.*makeX86System.*', r'.*makeDualRoot.*','configs/common/FSConfig.py') remove_lines(r'.*X86.*', None, 'configs/example/fs.py') remove_lines(r'.*x86.*', None, 'configs/example/fs.py') +remove_lines(r'.*x86.*', r'.*makeDualRoot.*', 'configs/common/FSConfig.py') replace_line(r'.*X86_SE.*', 'util/regress', " 'SPARC_SE,SPARC_FS',") benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', |