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-rw-r--r--configs/common/FSConfig.py139
-rw-r--r--configs/example/fs.py8
-rw-r--r--src/dev/x86/I82094AA.py1
-rw-r--r--src/dev/x86/i82094aa.cc2
-rw-r--r--src/dev/x86/i82094aa.hh4
5 files changed, 45 insertions, 109 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index a9cd24ba3..180e0ac52 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -164,7 +164,7 @@ def x86IOAddress(port):
IO_address_space_base = 0x8000000000000000
return IO_address_space_base + port;
-def makeX86System(mem_mode, mdesc = None, self = None):
+def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
if self == None:
self = X86System()
@@ -203,17 +203,19 @@ def makeX86System(mem_mode, mdesc = None, self = None):
self.smbios_table.structures = structures
# Set up the Intel MP table
- bp = X86IntelMPProcessor(
- local_apic_id = 0,
- local_apic_version = 0x14,
- enable = True,
- bootstrap = True)
- self.intel_mp_table.add_entry(bp)
+ for i in xrange(numCPUs):
+ bp = X86IntelMPProcessor(
+ local_apic_id = i,
+ local_apic_version = 0x14,
+ enable = True,
+ bootstrap = (i == 0))
+ self.intel_mp_table.add_entry(bp)
io_apic = X86IntelMPIOAPIC(
- id = 1,
+ id = numCPUs,
version = 0x11,
enable = True,
address = 0xfec00000)
+ self.pc.south_bridge.io_apic.apic_id = io_apic.id
self.intel_mp_table.add_entry(io_apic)
isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
self.intel_mp_table.add_entry(isa_bus)
@@ -231,103 +233,36 @@ def makeX86System(mem_mode, mdesc = None, self = None):
dest_io_apic_id = io_apic.id,
dest_io_apic_intin = 16)
self.intel_mp_table.add_entry(pci_dev4_inta);
- assign_8259_0_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- self.intel_mp_table.add_entry(assign_8259_0_to_apic)
- assign_0_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 0,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 2)
- self.intel_mp_table.add_entry(assign_0_to_apic)
- assign_8259_1_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 1,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- self.intel_mp_table.add_entry(assign_8259_1_to_apic)
- assign_1_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 1,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 1)
- self.intel_mp_table.add_entry(assign_1_to_apic)
- assign_8259_4_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 4,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- self.intel_mp_table.add_entry(assign_8259_4_to_apic)
- assign_4_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 4,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 4)
- self.intel_mp_table.add_entry(assign_4_to_apic)
- assign_8259_12_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 12,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- self.intel_mp_table.add_entry(assign_8259_12_to_apic)
- assign_12_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 12,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 12)
- self.intel_mp_table.add_entry(assign_12_to_apic)
- assign_8259_14_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'ExtInt',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 14,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 0)
- self.intel_mp_table.add_entry(assign_8259_14_to_apic)
- assign_14_to_apic = X86IntelMPIOIntAssignment(
- interrupt_type = 'INT',
- polarity = 'ConformPolarity',
- trigger = 'ConformTrigger',
- source_bus_id = 0,
- source_bus_irq = 14,
- dest_io_apic_id = io_apic.id,
- dest_io_apic_intin = 14)
- self.intel_mp_table.add_entry(assign_14_to_apic)
-
-
-def makeLinuxX86System(mem_mode, mdesc = None):
+ def assignISAInt(irq, apicPin):
+ assign_8259_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'ExtInt',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = 0)
+ self.intel_mp_table.add_entry(assign_8259_to_apic)
+ assign_to_apic = X86IntelMPIOIntAssignment(
+ interrupt_type = 'INT',
+ polarity = 'ConformPolarity',
+ trigger = 'ConformTrigger',
+ source_bus_id = 0,
+ source_bus_irq = irq,
+ dest_io_apic_id = io_apic.id,
+ dest_io_apic_intin = apicPin)
+ self.intel_mp_table.add_entry(assign_to_apic)
+ assignISAInt(0, 2)
+ assignISAInt(1, 1)
+ for i in range(3, 15):
+ assignISAInt(i, i)
+
+
+def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
self = LinuxX86System()
# Build up a generic x86 system and then specialize it for Linux
- makeX86System(mem_mode, mdesc, self)
+ makeX86System(mem_mode, numCPUs, mdesc, self)
# We assume below that there's at least 1MB of memory. We'll require 2
# just to avoid corner cases.
diff --git a/configs/example/fs.py b/configs/example/fs.py
index c013a97ae..b5be79a08 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -96,6 +96,8 @@ else:
else:
bm = [SysConfig()]
+np = options.num_cpus
+
if m5.build_env['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "mips":
@@ -103,7 +105,7 @@ elif m5.build_env['TARGET_ISA'] == "mips":
elif m5.build_env['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "x86":
- test_sys = makeLinuxX86System(test_mem_mode, bm[0])
+ test_sys = makeLinuxX86System(test_mem_mode, np, bm[0])
else:
m5.fatal("incapable of building non-alpha or non-sparc full system!")
@@ -113,8 +115,6 @@ if options.kernel is not None:
if options.script is not None:
test_sys.readfile = options.script
-np = options.num_cpus
-
if options.l2cache:
test_sys.l2 = L2Cache(size = '2MB')
test_sys.tol2bus = Bus()
@@ -153,7 +153,7 @@ if len(bm) == 2:
elif m5.build_env['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif m5.build.env['TARGET_ISA'] == 'x86':
- drive_sys = makeX86System(drive_mem_mode, bm[1])
+ drive_sys = makeX86System(drive_mem_mode, np, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
if options.fastmem:
diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index 9d57beed1..5476becc6 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -34,6 +34,7 @@ from X86IntPin import X86IntSinkPin
class I82094AA(BasicPioDevice):
type = 'I82094AA'
cxx_class = 'X86ISA::I82094AA'
+ apic_id = Param.Int(1, 'APIC id for this IO APIC')
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
pio_addr = Param.Addr("Device address")
int_port = Port("Port for sending and receiving interrupt messages")
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index 2656a21f9..21332c3ae 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -40,7 +40,7 @@ X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
extIntPic(p->external_int_pic)
{
// This assumes there's only one I/O APIC in the system
- id = sys->numContexts();
+ id = p->apic_id;
assert(id <= 0xf);
arbId = id;
regSel = 0;
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index b11e2bcb1..598e218f8 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -103,8 +103,8 @@ class I82094AA : public PioDevice, public IntDev
void getIntAddrRange(AddrRangeList &range_list)
{
range_list.clear();
- range_list.push_back(RangeEx(x86InterruptAddress(1, 0),
- x86InterruptAddress(1, 0) + PhysAddrAPICRangeSize));
+ range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
+ x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
}
void writeReg(uint8_t offset, uint32_t value);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 21:50:16 +0000