diff options
39 files changed, 322 insertions, 412 deletions
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 2d59180c4..4f293e22f 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -38,12 +38,12 @@ if env['TARGET_ISA'] == 'alpha': Source('miscregfile.cc') Source('regfile.cc') Source('remote_gdb.cc') + Source('utility.cc') if env['FULL_SYSTEM']: SimObject('AlphaSystem.py') SimObject('AlphaTLB.py') - Source('arguments.cc') Source('ev5.cc') Source('idle_event.cc') Source('ipr.cc') diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index af1a91a62..2177e8c4f 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -714,7 +714,7 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(R0); - }}, IsSerializeAfter, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); // Write uniq reg with value from ABI arg register (r16) diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index f93cdfbad..102598716 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -40,7 +40,6 @@ * up boot time. */ -#include "arch/arguments.hh" #include "arch/vtophys.hh" #include "arch/alpha/idle_event.hh" #include "arch/alpha/linux/system.hh" @@ -54,6 +53,7 @@ #include "kern/linux/events.hh" #include "mem/physical.hh" #include "mem/port.hh" +#include "sim/arguments.hh" #include "sim/byteswap.hh" using namespace std; diff --git a/src/arch/sparc/arguments.cc b/src/arch/alpha/utility.cc index 44adf4a15..f1864203b 100644 --- a/src/arch/sparc/arguments.cc +++ b/src/arch/alpha/utility.cc @@ -26,48 +26,40 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Nathan Binkert + * Ali Saidi */ -#include "arch/sparc/arguments.hh" -#include "arch/sparc/vtophys.hh" -#include "cpu/thread_context.hh" -#include "mem/vport.hh" - -using namespace SparcISA; +#include "arch/alpha/utility.hh" -Arguments::Data::~Data() -{ - while (!data.empty()) { - delete [] data.front(); - data.pop_front(); - } -} +#if FULL_SYSTEM +#include "arch/alpha/vtophys.hh" +#include "mem/vport.hh" +#endif -char * -Arguments::Data::alloc(size_t size) +namespace AlphaISA { - char *buf = new char[size]; - data.push_back(buf); - return buf; -} -uint64_t -Arguments::getArg(bool fp) +uint64_t getArgument(ThreadContext *tc, int number, bool fp) { - //The caller uses %o0-%05 for the first 6 arguments even if their floating - //point. Double precision floating point values take two registers/args. - //Quads, structs, and unions are passed as pointers. All arguments beyond - //the sixth are passed on the stack past the 16 word window save area, - //space for the struct/union return pointer, and space reserved for the - //first 6 arguments which the caller may use but doesn't have to. - if (number < 6) { - return tc->readIntReg(8 + number); +#if FULL_SYSTEM + if (number < NumArgumentRegs) { + if (fp) + return tc->readFloatRegBits(ArgumentReg[number]); + else + return tc->readIntReg(ArgumentReg[number]); } else { - Addr sp = tc->readIntReg(14); + Addr sp = tc->readIntReg(StackPointerReg); VirtualPort *vp = tc->getVirtPort(tc); - uint64_t arg = vp->read<uint64_t>(sp + 92 + (number-6) * sizeof(uint64_t)); + uint64_t arg = vp->read<uint64_t>(sp + + (number-NumArgumentRegs) * sizeof(uint64_t)); tc->delVirtPort(vp); return arg; } +#else + panic("getArgument() is Full system only\n"); + M5_DUMMY_RETURN +#endif } +} // namespace AlphaISA + diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index c20394a92..5d461a0f9 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -42,6 +42,8 @@ namespace AlphaISA { + uint64_t getArgument(ThreadContext *tc, int number, bool fp); + static inline bool inUserMode(ThreadContext *tc) { diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index de209348a..658710389 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -34,8 +34,9 @@ Import('*') if env['TARGET_ISA'] == 'mips': Source('faults.cc') - Source('isa_traits.cc') + Source('regfile/int_regfile.cc') Source('regfile/misc_regfile.cc') + Source('regfile/regfile.cc') Source('utility.cc') Source('dsp.cc') diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index e55d2e070..40ea223f6 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 0x4: syscall({{ xc->syscall(R2); }}, - IsSerializeAfter, IsNonSpeculative); + IsSerializeAfter, IsNonSpeculative, + IsSyscall); 0x7: sync({{ ; }}, IsMemBarrier); } diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index 0e0cf44eb..0ce807a24 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -72,6 +72,7 @@ output exec {{ #include "arch/mips/dsp.hh" #include "arch/mips/pra_constants.hh" #include "arch/mips/dt_constants.hh" +#include "arch/mips/mt.hh" #include "arch/mips/mt_constants.hh" #include <math.h> diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh index 0f6978433..57306d237 100755 --- a/src/arch/mips/mt_constants.hh +++ b/src/arch/mips/mt_constants.hh @@ -31,7 +31,6 @@ #ifndef __ARCH_MIPS_MT_CONSTANTS_HH__ #define __ARCH_MIPS_MT_CONSTANTS_HH__ -#include "arch/mips/types.hh" //#include "config/full_system.hh" namespace MipsISA diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index 71be3adf9..02e9c92bb 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -30,13 +30,13 @@ #include "base/bitfield.hh" -#include "arch/mips/regfile/misc_regfile.hh" -#include "arch/mips/mt_constants.hh" #include "arch/mips/faults.hh" +#include "arch/mips/mt.hh" +#include "arch/mips/mt_constants.hh" +#include "arch/mips/regfile/misc_regfile.hh" -#include "cpu/thread_context.hh" #include "cpu/base.hh" -#include "cpu/exetrace.hh" +#include "cpu/thread_context.hh" //#include "cpu/mixie/cpu.hh" using namespace std; diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 54b086a8b..0846378bb 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -33,14 +33,12 @@ #include "arch/mips/isa_traits.hh" #include "arch/mips/types.hh" -#include "arch/mips/mt.hh" -#include "arch/mips/mt_constants.hh" -#include "base/bitfield.hh" -#include "cpu/base.hh" +#include "sim/eventq.hh" #include "sim/faults.hh" #include <queue> class ThreadContext; +class BaseCPU; namespace MipsISA { @@ -76,7 +74,10 @@ namespace MipsISA void expandForMultithreading(unsigned num_threads, unsigned num_vpes); - void copyMiscRegs(ThreadContext *tc); + void copyMiscRegs(ThreadContext *tc) + { + panic("Copy Misc. Regs Not Implemented Yet\n"); + } inline unsigned getVPENum(unsigned tid); diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index f13653132..b83bb576b 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -32,8 +32,6 @@ #define __ARCH_MIPS_REGFILE_REGFILE_HH__ #include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" -#include "arch/mips/mt.hh" #include "arch/mips/regfile/int_regfile.hh" #include "arch/mips/regfile/float_regfile.hh" #include "arch/mips/regfile/misc_regfile.hh" @@ -189,9 +187,11 @@ namespace MipsISA return reg; } - void copyRegs(ThreadContext *src, ThreadContext *dest); + void + copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + void + copyMiscRegs(ThreadContext *src, ThreadContext *dest); } // namespace MipsISA diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index e3fd9daa8..300761c93 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -48,6 +48,10 @@ class ThreadContext; namespace MipsISA { + uint64_t getArgument(ThreadContext *tc, bool fp) { + panic("getArgument() not implemented for MIPS\n"); + } + //Floating Point Utility Functions uint64_t fpConvert(ConvertType cvt_type, double fp_val); double roundFP(double val, int digits); @@ -70,8 +74,6 @@ namespace MipsISA { void startupCPU(ThreadContext *tc, int cpuId); - void copyRegs(ThreadContext *src, ThreadContext *dest); - // Instruction address compression hooks static inline Addr realPCToFetchPC(const Addr &addr) { return addr; diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index c9dbb8cf2..0552c282b 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -39,12 +39,12 @@ if env['TARGET_ISA'] == 'sparc': Source('miscregfile.cc') Source('regfile.cc') Source('remote_gdb.cc') + Source('utility.cc') if env['FULL_SYSTEM']: SimObject('SparcSystem.py') SimObject('SparcTLB.py') - Source('arguments.cc') Source('pagetable.cc') Source('stacktrace.cc') Source('system.cc') diff --git a/src/arch/sparc/arguments.hh b/src/arch/sparc/arguments.hh deleted file mode 100644 index 5596f7408..000000000 --- a/src/arch/sparc/arguments.hh +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ARCH_SPARC_ARGUMENTS_HH__ -#define __ARCH_SPARC_ARGUMENTS_HH__ - -#include <assert.h> - -#include "base/refcnt.hh" -#include "sim/host.hh" -#include "mem/vport.hh" - -class ThreadContext; - -namespace SparcISA { - -class Arguments -{ - protected: - ThreadContext *tc; - int number; - uint64_t getArg(bool fp = false); - - protected: - class Data : public RefCounted - { - public: - Data(){} - ~Data(); - - private: - std::list<char *> data; - - public: - char *alloc(size_t size); - }; - - RefCountingPtr<Data> data; - - public: - Arguments(ThreadContext *ctx, int n = 0) - : tc(ctx), number(n), data(NULL) - { assert(number >= 0); data = new Data;} - Arguments(const Arguments &args) - : tc(args.tc), number(args.number), data(args.data) {} - ~Arguments() {} - - ThreadContext *getThreadContext() const { return tc; } - - const Arguments &operator=(const Arguments &args) { - tc = args.tc; - number = args.number; - data = args.data; - return *this; - } - - Arguments &operator++() { - ++number; - assert(number >= 0); - return *this; - } - - Arguments operator++(int) { - Arguments args = *this; - ++number; - assert(number >= 0); - return args; - } - - Arguments &operator--() { - --number; - assert(number >= 0); - return *this; - } - - Arguments operator--(int) { - Arguments args = *this; - --number; - assert(number >= 0); - return args; - } - - const Arguments &operator+=(int index) { - number += index; - assert(number >= 0); - return *this; - } - - const Arguments &operator-=(int index) { - number -= index; - assert(number >= 0); - return *this; - } - - Arguments operator[](int index) { - return Arguments(tc, index); - } - - template <class T> - operator T() { - assert(sizeof(T) <= sizeof(uint64_t)); - T data = static_cast<T>(getArg()); - return data; - } - - template <class T> - operator T *() { - T *buf = (T *)data->alloc(sizeof(T)); - CopyData(tc, buf, getArg(), sizeof(T)); - return buf; - } - - operator char *() { - char *buf = data->alloc(2048); - CopyStringOut(tc, buf, getArg(), 2048); - return buf; - } -}; - -}; // namespace SparcISA - -#endif // __ARCH_SPARC_ARGUMENTS_HH__ diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 68b2183ad..14c652606 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1230,7 +1230,7 @@ decode OP default Unknown::unknown() DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); } - }}, IsSerializeAfter, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 0x2: Trap::tccx({{ if(passesCondition(Ccr<7:4>, COND2)) { @@ -1238,7 +1238,7 @@ decode OP default Unknown::unknown() DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); } - }}, IsSerializeAfter, IsNonSpeculative); + }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); } 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, MemWriteOp); diff --git a/src/arch/mips/isa_traits.cc b/src/arch/sparc/utility.cc index 0c84ce2b2..6d4358603 100644 --- a/src/arch/mips/isa_traits.cc +++ b/src/arch/sparc/utility.cc @@ -26,75 +26,39 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Gabe Black - * Korey Sewell + * Ali Saidi */ -#include "arch/mips/isa_traits.hh" -#include "arch/mips/regfile/regfile.hh" -#include "sim/serialize.hh" -#include "base/bitfield.hh" +#include "arch/sparc/utility.hh" +#if FULL_SYSTEM +#include "arch/sparc/vtophys.hh" +#include "mem/vport.hh" +#endif -using namespace MipsISA; -using namespace std; +namespace SparcISA { -void -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Regs Not Implemented Yet\n"); -} - -void -MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - -void -MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc) -{ - panic("Copy Misc. Regs Not Implemented Yet\n"); -} - -void -IntRegFile::serialize(std::ostream &os) -{ - SERIALIZE_ARRAY(regs, NumIntRegs); -} -void -IntRegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - UNSERIALIZE_ARRAY(regs, NumIntRegs); +//The caller uses %o0-%05 for the first 6 arguments even if their floating +//point. Double precision floating point values take two registers/args. +//Quads, structs, and unions are passed as pointers. All arguments beyond +//the sixth are passed on the stack past the 16 word window save area, +//space for the struct/union return pointer, and space reserved for the +//first 6 arguments which the caller may use but doesn't have to. +uint64_t getArgument(ThreadContext *tc, int number, bool fp) { +#if FULL_SYSTEM + if (number < NumArgumentRegs) { + return tc->readIntReg(ArgumentReg[number]); + } else { + Addr sp = tc->readIntReg(StackPointerReg); + VirtualPort *vp = tc->getVirtPort(tc); + uint64_t arg = vp->read<uint64_t>(sp + 92 + + (number-NumArgumentRegs) * sizeof(uint64_t)); + tc->delVirtPort(vp); + return arg; + } +#else + panic("getArgument() only implemented for FULL_SYSTEM\n"); + M5_DUMMY_RETURN +#endif } - -void -RegFile::serialize(std::ostream &os) -{ - intRegFile.serialize(os); - //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); - //SERIALZE_ARRAY(miscRegFile); - //SERIALIZE_SCALAR(miscRegs.fpcr); - //SERIALIZE_SCALAR(miscRegs.lock_flag); - //SERIALIZE_SCALAR(miscRegs.lock_addr); - SERIALIZE_SCALAR(pc); - SERIALIZE_SCALAR(npc); - SERIALIZE_SCALAR(nnpc); -} - - -void -RegFile::unserialize(Checkpoint *cp, const std::string §ion) -{ - intRegFile.unserialize(cp, section); - //UNSERIALIZE_ARRAY(floatRegFile); - //UNSERIALZE_ARRAY(miscRegFile); - //UNSERIALIZE_SCALAR(miscRegs.fpcr); - //UNSERIALIZE_SCALAR(miscRegs.lock_flag); - //UNSERIALIZE_SCALAR(miscRegs.lock_addr); - UNSERIALIZE_SCALAR(pc); - UNSERIALIZE_SCALAR(npc); - UNSERIALIZE_SCALAR(nnpc); - -} - - +} //namespace SPARC_ISA diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 1458231f2..9a84a82b3 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -41,6 +41,9 @@ namespace SparcISA { + + uint64_t getArgument(ThreadContext *tc, int number, bool fp); + static inline bool inUserMode(ThreadContext *tc) { diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index a8c4e7062..e8307c6e6 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -70,7 +70,7 @@ #if FULL_SYSTEM 0x05: syscall(); #else - 0x05: SyscallInst::syscall('xc->syscall(rax)'); + 0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall); #endif 0x06: clts(); //sandpile.org says (AMD) after sysret, so I might want to check diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa index f16647fe5..bab687acd 100644 --- a/src/arch/x86/isa/decoder/x87.isa +++ b/src/arch/x86/isa/decoder/x87.isa @@ -103,7 +103,7 @@ 0x5: fldln2(); 0x6: fldz(); } - default: fldcw(); + default: fldcw_Mw(); } 0x6: decode MODRM_MOD { 0x3: decode MODRM_RM { @@ -129,7 +129,7 @@ 0x6: fsin(); 0x7: fcos(); } - default: fnstcw(); + default: fnstcw_Mw(); } } //0x2: esc2(); diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 18cbc6082..b8cddb09b 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -170,7 +170,7 @@ def template MicroLoadCompleteAcc {{ %(op_rd)s; Mem = pkt->get<typeof(Mem)>(); - int offset = pkt->flags; + int offset = pkt->req->getFlags(); Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8); %(code)s; diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 036805612..17904cb33 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -412,11 +412,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); - //Set up the thread context to start running the process - //Because of the peculiarities of how syscall works, I believe - //a process starts with r11 containing the value of eflags or maybe r11 - //from before the call to execve. Empirically this value is 0x200. - threadContexts[0]->setIntReg(INTREG_R11, 0x200); //Set the stack pointer register threadContexts[0]->setIntReg(StackPointerReg, stack_min); diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index a55c1e3c0..362babeff 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -498,6 +498,7 @@ class BaseDynInst : public FastAlloc, public RefCounted bool isQuiesce() const { return staticInst->isQuiesce(); } bool isIprAccess() const { return staticInst->isIprAccess(); } bool isUnverifiable() const { return staticInst->isUnverifiable(); } + bool isSyscall() const { return staticInst->isSyscall(); } bool isMacroop() const { return staticInst->isMacroop(); } bool isMicroop() const { return staticInst->isMicroop(); } bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index 90a0e1a62..fe524e245 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -60,119 +60,122 @@ NativeTrace::NativeTrace(const std::string & _name) : InstTracer(_name) } ccprintf(cerr, "Listening for native process on port %d\n", port); fd = native_listener.accept(); + checkRcx = true; + checkR11 = true; } bool -NativeTraceRecord::checkIntReg(const char * regName, int index, int size) +NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal) { - uint64_t regVal; - int res = read(parent->fd, ®Val, size); - if(res < 0) - panic("Read call failed! %s\n", strerror(errno)); - regVal = TheISA::gtoh(regVal); - uint64_t realRegVal = thread->readIntReg(index); - if(regVal != realRegVal) - { - DPRINTFN("Register %s should be %#x but is %#x.\n", - regName, regVal, realRegVal); - return false; - } + if(!checkRcx) + checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal); + if(checkRcx) + return checkReg(name, mVal, nVal); return true; } -bool NativeTraceRecord::checkPC(const char * regName, int size) +bool +NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal) { - uint64_t regVal; - int res = read(parent->fd, ®Val, size); - if(res < 0) - panic("Read call failed! %s\n", strerror(errno)); - regVal = TheISA::gtoh(regVal); - uint64_t realRegVal = thread->readNextPC(); - if(regVal != realRegVal) - { - DPRINTFN("%s should be %#x but is %#x.\n", - regName, regVal, realRegVal); - return false; - } + if(!checkR11) + checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val); + if(checkR11) + return checkReg(name, mVal, nVal); return true; } void Trace::NativeTraceRecord::dump() { -// ostream &outs = Trace::output(); - //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. if(!staticInst->isMicroop() || staticInst->isLastMicroop()) + parent->check(thread, staticInst->isSyscall()); +} + +void +Trace::NativeTrace::check(ThreadContext * tc, bool isSyscall) +{ +// ostream &outs = Trace::output(); + nState.update(fd); + mState.update(tc); + + if(isSyscall) { - checkIntReg("rax", INTREG_RAX, sizeof(uint64_t)); - checkIntReg("rcx", INTREG_RCX, sizeof(uint64_t)); - checkIntReg("rdx", INTREG_RDX, sizeof(uint64_t)); - checkIntReg("rbx", INTREG_RBX, sizeof(uint64_t)); - checkIntReg("rsp", INTREG_RSP, sizeof(uint64_t)); - checkIntReg("rbp", INTREG_RBP, sizeof(uint64_t)); - checkIntReg("rsi", INTREG_RSI, sizeof(uint64_t)); - checkIntReg("rdi", INTREG_RDI, sizeof(uint64_t)); - checkIntReg("r8", INTREG_R8, sizeof(uint64_t)); - checkIntReg("r9", INTREG_R9, sizeof(uint64_t)); - checkIntReg("r10", INTREG_R10, sizeof(uint64_t)); - checkIntReg("r11", INTREG_R11, sizeof(uint64_t)); - checkIntReg("r12", INTREG_R12, sizeof(uint64_t)); - checkIntReg("r13", INTREG_R13, sizeof(uint64_t)); - checkIntReg("r14", INTREG_R14, sizeof(uint64_t)); - checkIntReg("r15", INTREG_R15, sizeof(uint64_t)); - checkPC("rip", sizeof(uint64_t)); + checkRcx = false; + checkR11 = false; + oldRcxVal = mState.rcx; + oldRealRcxVal = nState.rcx; + oldR11Val = mState.r11; + oldRealR11Val = nState.r11; + } + + checkReg("rax", mState.rax, nState.rax); + checkRcxReg("rcx", mState.rcx, nState.rcx); + checkReg("rdx", mState.rdx, nState.rdx); + checkReg("rbx", mState.rbx, nState.rbx); + checkReg("rsp", mState.rsp, nState.rsp); + checkReg("rbp", mState.rbp, nState.rbp); + checkReg("rsi", mState.rsi, nState.rsi); + checkReg("rdi", mState.rdi, nState.rdi); + checkReg("r8", mState.r8, nState.r8); + checkReg("r9", mState.r9, nState.r9); + checkReg("r10", mState.r10, nState.r10); + checkR11Reg("r11", mState.r11, nState.r11); + checkReg("r12", mState.r12, nState.r12); + checkReg("r13", mState.r13, nState.r13); + checkReg("r14", mState.r14, nState.r14); + checkReg("r15", mState.r15, nState.r15); + checkReg("rip", mState.rip, nState.rip); #if THE_ISA == SPARC_ISA - /*for(int f = 0; f <= 62; f+=2) - { - uint64_t regVal; - int res = read(fd, ®Val, sizeof(regVal)); - if(res < 0) - panic("First read call failed! %s\n", strerror(errno)); - regVal = TheISA::gtoh(regVal); - uint64_t realRegVal = thread->readFloatRegBits(f, 64); - if(regVal != realRegVal) - { - DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal); - } - }*/ + /*for(int f = 0; f <= 62; f+=2) + { uint64_t regVal; int res = read(fd, ®Val, sizeof(regVal)); if(res < 0) panic("First read call failed! %s\n", strerror(errno)); regVal = TheISA::gtoh(regVal); - uint64_t realRegVal = thread->readNextPC(); - if(regVal != realRegVal) - { - DPRINTF(ExecRegDelta, - "Register pc should be %#x but is %#x.\n", - regVal, realRegVal); - } - res = read(fd, ®Val, sizeof(regVal)); - if(res < 0) - panic("First read call failed! %s\n", strerror(errno)); - regVal = TheISA::gtoh(regVal); - realRegVal = thread->readNextNPC(); + uint64_t realRegVal = thread->readFloatRegBits(f, 64); if(regVal != realRegVal) { - DPRINTF(ExecRegDelta, - "Register npc should be %#x but is %#x.\n", - regVal, realRegVal); - } - res = read(fd, ®Val, sizeof(regVal)); - if(res < 0) - panic("First read call failed! %s\n", strerror(errno)); - regVal = TheISA::gtoh(regVal); - realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); - if((regVal & 0xF) != (realRegVal & 0xF)) - { - DPRINTF(ExecRegDelta, - "Register ccr should be %#x but is %#x.\n", - regVal, realRegVal); + DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal); } -#endif + }*/ + uint64_t regVal; + int res = read(fd, ®Val, sizeof(regVal)); + if(res < 0) + panic("First read call failed! %s\n", strerror(errno)); + regVal = TheISA::gtoh(regVal); + uint64_t realRegVal = thread->readNextPC(); + if(regVal != realRegVal) + { + DPRINTF(ExecRegDelta, + "Register pc should be %#x but is %#x.\n", + regVal, realRegVal); } + res = read(fd, ®Val, sizeof(regVal)); + if(res < 0) + panic("First read call failed! %s\n", strerror(errno)); + regVal = TheISA::gtoh(regVal); + realRegVal = thread->readNextNPC(); + if(regVal != realRegVal) + { + DPRINTF(ExecRegDelta, + "Register npc should be %#x but is %#x.\n", + regVal, realRegVal); + } + res = read(fd, ®Val, sizeof(regVal)); + if(res < 0) + panic("First read call failed! %s\n", strerror(errno)); + regVal = TheISA::gtoh(regVal); + realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); + if((regVal & 0xF) != (realRegVal & 0xF)) + { + DPRINTF(ExecRegDelta, + "Register ccr should be %#x but is %#x.\n", + regVal, realRegVal); + } +#endif } /* namespace Trace */ } diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index 48395792d..126077581 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -36,6 +36,7 @@ #include "cpu/static_inst.hh" #include "sim/host.hh" #include "sim/insttracer.hh" +#include "arch/x86/intregs.hh" class ThreadContext; @@ -49,12 +50,6 @@ class NativeTraceRecord : public InstRecord protected: NativeTrace * parent; - bool - checkIntReg(const char * regName, int index, int size); - - bool - checkPC(const char * regName, int size); - public: NativeTraceRecord(NativeTrace * _parent, Tick _when, ThreadContext *_thread, @@ -73,8 +68,109 @@ class NativeTrace : public InstTracer ListenSocket native_listener; + bool checkRcx; + bool checkR11; + uint64_t oldRcxVal, oldR11Val; + uint64_t oldRealRcxVal, oldRealR11Val; + + struct ThreadState { + uint64_t rax; + uint64_t rcx; + uint64_t rdx; + uint64_t rbx; + uint64_t rsp; + uint64_t rbp; + uint64_t rsi; + uint64_t rdi; + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + uint64_t rip; + + void update(int fd) + { + int bytesLeft = sizeof(ThreadState); + int bytesRead = 0; + do + { + int res = read(fd, ((char *)this) + bytesRead, bytesLeft); + if(res < 0) + panic("Read call failed! %s\n", strerror(errno)); + bytesLeft -= res; + bytesRead += res; + } while(bytesLeft); + rax = TheISA::gtoh(rax); + rcx = TheISA::gtoh(rcx); + rdx = TheISA::gtoh(rdx); + rbx = TheISA::gtoh(rbx); + rsp = TheISA::gtoh(rsp); + rbp = TheISA::gtoh(rbp); + rsi = TheISA::gtoh(rsi); + rdi = TheISA::gtoh(rdi); + r8 = TheISA::gtoh(r8); + r9 = TheISA::gtoh(r9); + r10 = TheISA::gtoh(r10); + r11 = TheISA::gtoh(r11); + r12 = TheISA::gtoh(r12); + r13 = TheISA::gtoh(r13); + r14 = TheISA::gtoh(r14); + r15 = TheISA::gtoh(r15); + rip = TheISA::gtoh(rip); + } + + void update(ThreadContext * tc) + { + rax = tc->readIntReg(X86ISA::INTREG_RAX); + rcx = tc->readIntReg(X86ISA::INTREG_RCX); + rdx = tc->readIntReg(X86ISA::INTREG_RDX); + rbx = tc->readIntReg(X86ISA::INTREG_RBX); + rsp = tc->readIntReg(X86ISA::INTREG_RSP); + rbp = tc->readIntReg(X86ISA::INTREG_RBP); + rsi = tc->readIntReg(X86ISA::INTREG_RSI); + rdi = tc->readIntReg(X86ISA::INTREG_RDI); + r8 = tc->readIntReg(X86ISA::INTREG_R8); + r9 = tc->readIntReg(X86ISA::INTREG_R9); + r10 = tc->readIntReg(X86ISA::INTREG_R10); + r11 = tc->readIntReg(X86ISA::INTREG_R11); + r12 = tc->readIntReg(X86ISA::INTREG_R12); + r13 = tc->readIntReg(X86ISA::INTREG_R13); + r14 = tc->readIntReg(X86ISA::INTREG_R14); + r15 = tc->readIntReg(X86ISA::INTREG_R15); + rip = tc->readNextPC(); + } + + }; + + ThreadState nState; + ThreadState mState; + + public: + template<class T> + bool + checkReg(const char * regName, T &val, T &realVal) + { + if(val != realVal) + { + DPRINTFN("Register %s should be %#x but is %#x.\n", + regName, realVal, val); + return false; + } + return true; + } + + bool + checkRcxReg(const char * regName, uint64_t &, uint64_t &); + + bool + checkR11Reg(const char * regName, uint64_t &, uint64_t &); + NativeTrace(const std::string & name); NativeTraceRecord * @@ -88,6 +184,9 @@ class NativeTrace : public InstTracer staticInst, pc, tc->misspeculating()); } + void + check(ThreadContext *, bool syscall); + friend class NativeTraceRecord; }; diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index b0a19c151..f32b61ee5 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -143,6 +143,9 @@ class StaticInstBase : public RefCounted IsIprAccess, ///< Accesses IPRs IsUnverifiable, ///< Can't be verified by a checker + IsSyscall, ///< Causes a system call to be emulated in syscall + /// emulation mode. + //Flags for microcode IsMacroop, ///< Is a macroop containing microops IsMicroop, ///< Is a microop @@ -243,6 +246,7 @@ class StaticInstBase : public RefCounted bool isQuiesce() const { return flags[IsQuiesce]; } bool isIprAccess() const { return flags[IsIprAccess]; } bool isUnverifiable() const { return flags[IsUnverifiable]; } + bool isSyscall() const { return flags[IsSyscall]; } bool isMacroop() const { return flags[IsMacroop]; } bool isMicroop() const { return flags[IsMicroop]; } bool isDelayedCommit() const { return flags[IsDelayedCommit]; } diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc index 42fa63a27..bfff816ca 100644 --- a/src/kern/linux/events.cc +++ b/src/kern/linux/events.cc @@ -29,7 +29,7 @@ * Ali Saidi */ -#include "arch/arguments.hh" +#include "sim/arguments.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" #include "kern/linux/events.hh" @@ -46,7 +46,7 @@ DebugPrintkEvent::process(ThreadContext *tc) { if (DTRACE(DebugPrintf)) { std::stringstream ss; - TheISA::Arguments args(tc); + Arguments args(tc); Printk(ss, args); StringWrap name(tc->getSystemPtr()->name() + ".dprintk"); DPRINTFN("%s", ss.str()); diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc index 866353e31..24e28e666 100644 --- a/src/kern/linux/printk.cc +++ b/src/kern/linux/printk.cc @@ -32,7 +32,7 @@ #include <sys/types.h> #include <algorithm> -#include "arch/arguments.hh" +#include "sim/arguments.hh" #include "base/trace.hh" #include "kern/linux/printk.hh" @@ -40,7 +40,7 @@ using namespace std; void -Printk(stringstream &out, TheISA::Arguments args) +Printk(stringstream &out, Arguments args) { char *p = (char *)args++; diff --git a/src/kern/linux/printk.hh b/src/kern/linux/printk.hh index 20dfb430f..da9564b7e 100644 --- a/src/kern/linux/printk.hh +++ b/src/kern/linux/printk.hh @@ -36,8 +36,8 @@ #include <sstream> -class TheISA::Arguments; +class Arguments; -void Printk(std::stringstream &out, TheISA::Arguments args); +void Printk(std::stringstream &out, Arguments args); #endif // __PRINTK_HH__ diff --git a/src/kern/tru64/dump_mbuf.cc b/src/kern/tru64/dump_mbuf.cc index 5ccfbca5d..e6bfc06d9 100644 --- a/src/kern/tru64/dump_mbuf.cc +++ b/src/kern/tru64/dump_mbuf.cc @@ -38,7 +38,7 @@ #include "kern/tru64/mbuf.hh" #include "sim/host.hh" #include "sim/system.hh" -#include "arch/arguments.hh" +#include "sim/arguments.hh" #include "arch/isa_traits.hh" #include "arch/vtophys.hh" diff --git a/src/kern/tru64/dump_mbuf.hh b/src/kern/tru64/dump_mbuf.hh index 30b1102b9..2f71fc61d 100644 --- a/src/kern/tru64/dump_mbuf.hh +++ b/src/kern/tru64/dump_mbuf.hh @@ -31,10 +31,10 @@ #ifndef __DUMP_MBUF_HH__ #define __DUMP_MBUF_HH__ -#include "arch/arguments.hh" +#include "sim/arguments.hh" namespace tru64 { - void DumpMbuf(TheISA::Arguments args); + void DumpMbuf(Arguments args); } #endif // __DUMP_MBUF_HH__ diff --git a/src/kern/tru64/printf.cc b/src/kern/tru64/printf.cc index 4245ac6d0..ce77efa83 100644 --- a/src/kern/tru64/printf.cc +++ b/src/kern/tru64/printf.cc @@ -31,18 +31,18 @@ #include <sys/types.h> #include <algorithm> +#include "arch/vtophys.hh" #include "base/cprintf.hh" #include "base/trace.hh" #include "sim/host.hh" -#include "arch/arguments.hh" -#include "arch/vtophys.hh" +#include "sim/arguments.hh" using namespace std; namespace tru64 { void -Printf(TheISA::Arguments args) +Printf(Arguments args) { std::ostream &out = Trace::output(); diff --git a/src/kern/tru64/printf.hh b/src/kern/tru64/printf.hh index ff453b1c1..5036694c0 100644 --- a/src/kern/tru64/printf.hh +++ b/src/kern/tru64/printf.hh @@ -31,10 +31,10 @@ #ifndef __PRINTF_HH__ #define __PRINTF_HH__ -#include "arch/arguments.hh" +#include "sim/arguments.hh" namespace tru64 { - void Printf(TheISA::Arguments args); + void Printf(Arguments args); } #endif // __PRINTF_HH__ diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc index c84b25dab..c798c3ced 100644 --- a/src/kern/tru64/tru64_events.cc +++ b/src/kern/tru64/tru64_events.cc @@ -29,15 +29,15 @@ * Lisa Hsu */ +#include "arch/alpha/ev5.hh" +#include "arch/isa_traits.hh" #include "cpu/thread_context.hh" #include "cpu/base.hh" #include "kern/system_events.hh" #include "kern/tru64/tru64_events.hh" #include "kern/tru64/dump_mbuf.hh" #include "kern/tru64/printf.hh" -#include "arch/alpha/ev5.hh" -#include "arch/arguments.hh" -#include "arch/isa_traits.hh" +#include "sim/arguments.hh" #include "sim/system.hh" using namespace TheISA; diff --git a/src/sim/SConscript b/src/sim/SConscript index 6bd53e205..bfa0c9a0c 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -50,6 +50,7 @@ Source('stat_control.cc') Source('system.cc') if env['FULL_SYSTEM']: + Source('arguments.cc') Source('pseudo_inst.cc') else: SimObject('Process.py') diff --git a/src/arch/alpha/arguments.cc b/src/sim/arguments.cc index e89bd70b0..5aa57755a 100644 --- a/src/arch/alpha/arguments.cc +++ b/src/sim/arguments.cc @@ -28,12 +28,11 @@ * Authors: Nathan Binkert */ -#include "arch/alpha/arguments.hh" -#include "arch/alpha/vtophys.hh" +#include "sim/arguments.hh" +#include "arch/utility.hh" #include "cpu/thread_context.hh" -#include "mem/vport.hh" -using namespace AlphaISA; +using namespace TheISA; Arguments::Data::~Data() { @@ -54,17 +53,6 @@ Arguments::Data::alloc(size_t size) uint64_t Arguments::getArg(bool fp) { - if (number < 6) { - if (fp) - return tc->readFloatRegBits(16 + number); - else - return tc->readIntReg(16 + number); - } else { - Addr sp = tc->readIntReg(30); - VirtualPort *vp = tc->getVirtPort(tc); - uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t)); - tc->delVirtPort(vp); - return arg; - } + return TheISA::getArgument(tc, number, fp); } diff --git a/src/arch/alpha/arguments.hh b/src/sim/arguments.hh index 4dba4901f..14c9e1f8a 100644 --- a/src/arch/alpha/arguments.hh +++ b/src/sim/arguments.hh @@ -28,20 +28,18 @@ * Authors: Nathan Binkert */ -#ifndef __ARCH_ALPHA_ARGUMENTS_HH__ -#define __ARCH_ALPHA_ARGUMENTS_HH__ +#ifndef __SIM_ARGUMENTS_HH__ +#define __SIM_ARGUMENTS_HH__ #include <assert.h> -#include "arch/alpha/vtophys.hh" +#include "arch/vtophys.hh" #include "base/refcnt.hh" #include "mem/vport.hh" #include "sim/host.hh" class ThreadContext; -namespace AlphaISA { - class Arguments { protected: @@ -82,6 +80,11 @@ class Arguments return *this; } + // for checking if an argument is NULL + bool operator!() { + return getArg() == 0; + } + Arguments &operator++() { ++number; assert(number >= 0); @@ -145,6 +148,4 @@ class Arguments } }; -}; // namespace AlphaISA - -#endif // __ARCH_ALPHA_ARGUMENTS_HH__ +#endif // __SIM_ARGUMENTS_HH__ diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh index ebeae1fe9..82b86ca84 100644 --- a/src/sim/insttracer.hh +++ b/src/sim/insttracer.hh @@ -32,6 +32,7 @@ #ifndef __INSTRECORD_HH__ #define __INSTRECORD_HH__ +#include "base/bigint.hh" #include "base/trace.hh" #include "cpu/inst_seq.hh" // for InstSeqNum #include "cpu/static_inst.hh" diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py index b2a2dc0b6..85b106eb4 100644 --- a/tests/long/70.twolf/test.py +++ b/tests/long/70.twolf/test.py @@ -32,7 +32,7 @@ import os workload = twolf(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() -cwd = root.system.cpu.workload.cwd +cwd = root.system.cpu.workload[0].cwd #Remove two files who's presence or absence affects execution sav_file = os.path.join(cwd, workload.input_set + '.sav') |