diff options
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 4 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 | ||||
| -rw-r--r-- | src/mem/request.hh | 4 |
5 files changed, 10 insertions, 8 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index f2a80a111..5742f84ab 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -671,7 +671,8 @@ let {{ exec_output += PredOpExecute.subst(setendIop) clrexCode = ''' - unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; + unsigned memAccessFlags = Request::CLEAR_LL | + ArmISA::TLB::AlignWord | Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); ''' clrexIop = InstObjParams("clrex", "Clrex","PredOp", diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 46af3f5b1..f8dac05f8 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -367,7 +367,8 @@ def template ClrexInitiateAcc {{ if (%(predicate_test)s) { if (fault == NoFault) { - unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; + unsigned memAccessFlags = Request::CLEAR_LL | + ArmISA::TLB::AlignWord | Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); } } else { diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 4e98aaf7b..c0ebb52b2 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -376,10 +376,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, // If this is a clrex instruction, provide a PA of 0 with no fault // This will force the monitor to set the tracked address to 0 // a bit of a hack but this effectively clrears this processors monitor - if (flags & Request::CLREX){ + if (flags & Request::CLEAR_LL){ req->setPaddr(0); req->setFlags(Request::UNCACHEABLE); - req->setFlags(Request::CLREX); + req->setFlags(Request::CLEAR_LL); return NoFault; } if ((req->isInstFetch() && (!sctlr.i)) || diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 86bf79b7b..7d19ff7a1 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -306,7 +306,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, int &lat, PacketList &writebacks) { if (pkt->req->isUncacheable()) { - if (pkt->req->isClrex()) { + if (pkt->req->isClearLL()) { tags->clearLocks(); } else { blk = tags->findBlock(pkt->getAddr()); @@ -449,7 +449,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt) } if (pkt->req->isUncacheable()) { - if (pkt->req->isClrex()) { + if (pkt->req->isClearLL()) { tags->clearLocks(); } else { BlkType *blk = tags->findBlock(pkt->getAddr()); diff --git a/src/mem/request.hh b/src/mem/request.hh index 7149f3199..45551dd03 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -72,7 +72,7 @@ class Request : public FastAlloc /** This request is to a memory mapped register. */ static const FlagsType MMAPED_IPR = 0x00002000; /** This request is a clear exclusive. */ - static const FlagsType CLREX = 0x00004000; + static const FlagsType CLEAR_LL = 0x00004000; /** The request should ignore unaligned access faults */ static const FlagsType NO_ALIGN_FAULT = 0x00020000; @@ -458,7 +458,7 @@ class Request : public FastAlloc bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); } - bool isClrex() const { return _flags.isSet(CLREX); } + bool isClearLL() const { return _flags.isSet(CLEAR_LL); } bool isMisaligned() const |