142 files changed, 1409 insertions, 817 deletions

diff --git a/SConscript b/SConscript
index 059ce0ca1..bb50f1872 100644
--- a/SConscript
+++ b/SConscript
@@ -45,7 +45,7 @@ Import('env')
 # Base sources used by all configurations.
 base_sources = Split('''
 	arch/alpha/decoder.cc
-        arch/alpha/alpha_full_cpu_exec.cc
+        arch/alpha/alpha_o3_exec.cc
 	arch/alpha/fast_cpu_exec.cc
 	arch/alpha/simple_cpu_exec.cc
 	arch/alpha/full_cpu_exec.cc
@@ -89,78 +89,80 @@ base_sources = Split('''
 	base/stats/visit.cc
 	base/stats/text.cc
 
-	cpu/base_cpu.cc
+	cpu/base.cc
         cpu/base_dyn_inst.cc
 	cpu/exec_context.cc
 	cpu/exetrace.cc
 	cpu/pc_event.cc
 	cpu/static_inst.cc
-        cpu/beta_cpu/2bit_local_pred.cc
-        cpu/beta_cpu/alpha_dyn_inst.cc
-        cpu/beta_cpu/alpha_full_cpu.cc
-        cpu/beta_cpu/alpha_full_cpu_builder.cc
-        cpu/beta_cpu/bpred_unit.cc
-        cpu/beta_cpu/btb.cc
-        cpu/beta_cpu/commit.cc
-        cpu/beta_cpu/decode.cc
-        cpu/beta_cpu/fetch.cc
-        cpu/beta_cpu/free_list.cc
-        cpu/beta_cpu/full_cpu.cc
-        cpu/beta_cpu/iew.cc
-        cpu/beta_cpu/inst_queue.cc
-        cpu/beta_cpu/ldstq.cc
-        cpu/beta_cpu/mem_dep_unit.cc
-        cpu/beta_cpu/ras.cc
-        cpu/beta_cpu/rename.cc
-        cpu/beta_cpu/rename_map.cc
-        cpu/beta_cpu/rob.cc
-        cpu/beta_cpu/sat_counter.cc
-        cpu/beta_cpu/store_set.cc
-        cpu/beta_cpu/tournament_pred.cc
-	cpu/fast_cpu/fast_cpu.cc
-	cpu/full_cpu/bpred.cc
-	cpu/full_cpu/commit.cc
-	cpu/full_cpu/create_vector.cc
-	cpu/full_cpu/cv_spec_state.cc
-	cpu/full_cpu/dd_queue.cc
-	cpu/full_cpu/dep_link.cc
-	cpu/full_cpu/dispatch.cc
-	cpu/full_cpu/dyn_inst.cc
-	cpu/full_cpu/execute.cc
-	cpu/full_cpu/fetch.cc
-	cpu/full_cpu/floss_reasons.cc
-	cpu/full_cpu/fu_pool.cc
-	cpu/full_cpu/full_cpu.cc
-	cpu/full_cpu/inst_fifo.cc
-	cpu/full_cpu/instpipe.cc
-	cpu/full_cpu/issue.cc
-	cpu/full_cpu/ls_queue.cc
-	cpu/full_cpu/machine_queue.cc
-        cpu/full_cpu/pc_sample_profile.cc
-        cpu/full_cpu/pipetrace.cc
-        cpu/full_cpu/readyq.cc
-        cpu/full_cpu/reg_info.cc
-        cpu/full_cpu/rob_station.cc
-        cpu/full_cpu/spec_memory.cc
-        cpu/full_cpu/spec_state.cc
-        cpu/full_cpu/storebuffer.cc
-        cpu/full_cpu/writeback.cc
-        cpu/full_cpu/iq/iq_station.cc
-        cpu/full_cpu/iq/iqueue.cc
-        cpu/full_cpu/iq/segmented/chain_info.cc
-        cpu/full_cpu/iq/segmented/chain_wire.cc
-        cpu/full_cpu/iq/segmented/iq_seg.cc
-        cpu/full_cpu/iq/segmented/iq_segmented.cc
-        cpu/full_cpu/iq/segmented/seg_chain.cc
-        cpu/full_cpu/iq/seznec/iq_seznec.cc
-        cpu/full_cpu/iq/standard/iq_standard.cc
-        cpu/sampling_cpu/sampling_cpu.cc
-        cpu/simple_cpu/simple_cpu.cc
+        cpu/o3/2bit_local_pred.cc
+        cpu/o3/alpha_dyn_inst.cc
+        cpu/o3/alpha_cpu.cc
+        cpu/o3/alpha_cpu_builder.cc
+        cpu/o3/bpred_unit.cc
+        cpu/o3/btb.cc
+        cpu/o3/commit.cc
+        cpu/o3/decode.cc
+        cpu/o3/fetch.cc
+        cpu/o3/free_list.cc
+        cpu/o3/cpu.cc
+        cpu/o3/iew.cc
+        cpu/o3/inst_queue.cc
+        cpu/o3/ldstq.cc
+        cpu/o3/mem_dep_unit.cc
+        cpu/o3/ras.cc
+        cpu/o3/rename.cc
+        cpu/o3/rename_map.cc
+        cpu/o3/rob.cc
+        cpu/o3/sat_counter.cc
+        cpu/o3/store_set.cc
+        cpu/o3/tournament_pred.cc
+	cpu/fast/cpu.cc
+        cpu/sampler/sampler.cc
+        cpu/simple/cpu.cc
         cpu/trace/reader/mem_trace_reader.cc
         cpu/trace/reader/ibm_reader.cc
         cpu/trace/reader/itx_reader.cc
         cpu/trace/reader/m5_reader.cc
 
+	encumbered/cpu/full/bpred.cc
+	encumbered/cpu/full/commit.cc
+	encumbered/cpu/full/cpu.cc
+	encumbered/cpu/full/create_vector.cc
+	encumbered/cpu/full/cv_spec_state.cc
+	encumbered/cpu/full/dd_queue.cc
+	encumbered/cpu/full/dep_link.cc
+	encumbered/cpu/full/dispatch.cc
+	encumbered/cpu/full/dyn_inst.cc
+	encumbered/cpu/full/execute.cc
+	encumbered/cpu/full/fetch.cc
+	encumbered/cpu/full/floss_reasons.cc
+	encumbered/cpu/full/fu_pool.cc
+	encumbered/cpu/full/inst_fifo.cc
+	encumbered/cpu/full/instpipe.cc
+	encumbered/cpu/full/issue.cc
+	encumbered/cpu/full/ls_queue.cc
+	encumbered/cpu/full/machine_queue.cc
+        encumbered/cpu/full/pc_sample_profile.cc
+        encumbered/cpu/full/pipetrace.cc
+        encumbered/cpu/full/readyq.cc
+        encumbered/cpu/full/reg_info.cc
+        encumbered/cpu/full/rob_station.cc
+        encumbered/cpu/full/spec_memory.cc
+        encumbered/cpu/full/spec_state.cc
+        encumbered/cpu/full/storebuffer.cc
+        encumbered/cpu/full/writeback.cc
+        encumbered/cpu/full/iq/iq_station.cc
+        encumbered/cpu/full/iq/iqueue.cc
+        encumbered/cpu/full/iq/segmented/chain_info.cc
+        encumbered/cpu/full/iq/segmented/chain_wire.cc
+        encumbered/cpu/full/iq/segmented/iq_seg.cc
+        encumbered/cpu/full/iq/segmented/iq_segmented.cc
+        encumbered/cpu/full/iq/segmented/seg_chain.cc
+        encumbered/cpu/full/iq/seznec/iq_seznec.cc
+        encumbered/cpu/full/iq/standard/iq_standard.cc
+	encumbered/mem/functional/main.cc
+
 	mem/base_hier.cc
 	mem/base_mem.cc
 	mem/hier_params.cc
@@ -202,11 +204,10 @@ base_sources = Split('''
 	mem/cache/tags/split_lru.cc
 	mem/cache/tags/repl/gen.cc
 	mem/cache/tags/repl/repl.cc
-	mem/functional_mem/functional_memory.cc
-	mem/functional_mem/main_memory.cc
-	mem/timing_mem/base_memory.cc
-	mem/timing_mem/memory_builder.cc
-	mem/timing_mem/simple_mem_bank.cc
+	mem/functional/functional.cc
+	mem/timing/base_memory.cc
+	mem/timing/memory_builder.cc
+	mem/timing/simple_mem_bank.cc
         mem/trace/itx_writer.cc
 	mem/trace/mem_trace_writer.cc
 	mem/trace/m5_writer.cc
@@ -257,7 +258,6 @@ full_system_sources = Split('''
 	dev/baddev.cc
         dev/simconsole.cc
 	dev/disk_image.cc
-	dev/dma.cc
 	dev/etherbus.cc
 	dev/etherdump.cc
 	dev/etherint.cc
@@ -268,31 +268,36 @@ full_system_sources = Split('''
 	dev/ide_disk.cc
 	dev/io_device.cc
 	dev/ns_gige.cc
-	dev/etherdev.cc
 	dev/pciconfigall.cc
 	dev/pcidev.cc
 	dev/pktfifo.cc
-	dev/scsi.cc
-	dev/scsi_ctrl.cc
-	dev/scsi_disk.cc
-	dev/scsi_none.cc
+        dev/platform.cc
 	dev/sinic.cc
 	dev/simple_disk.cc
-	dev/tlaser_clock.cc
-	dev/tlaser_ipi.cc
-	dev/tlaser_mbox.cc
-	dev/tlaser_mc146818.cc
-	dev/tlaser_node.cc
-	dev/tlaser_pcia.cc
-	dev/tlaser_pcidev.cc
-	dev/tlaser_serial.cc
-	dev/turbolaser.cc
 	dev/tsunami.cc
 	dev/tsunami_cchip.cc
 	dev/tsunami_fake.cc
 	dev/tsunami_io.cc
 	dev/tsunami_pchip.cc
 	dev/uart.cc
+	dev/uart8530.cc
+	dev/uart8250.cc
+
+	encumbered/dev/dma.cc
+	encumbered/dev/etherdev.cc
+	encumbered/dev/scsi.cc
+	encumbered/dev/scsi_ctrl.cc
+	encumbered/dev/scsi_disk.cc
+	encumbered/dev/scsi_none.cc
+	encumbered/dev/tlaser_clock.cc
+	encumbered/dev/tlaser_ipi.cc
+	encumbered/dev/tlaser_mbox.cc
+	encumbered/dev/tlaser_mc146818.cc
+	encumbered/dev/tlaser_node.cc
+	encumbered/dev/tlaser_pcia.cc
+	encumbered/dev/tlaser_pcidev.cc
+	encumbered/dev/tlaser_serial.cc
+	encumbered/dev/turbolaser.cc
 
 	kern/kernel_binning.cc
 	kern/kernel_stats.cc
@@ -307,9 +312,8 @@ full_system_sources = Split('''
 	kern/tru64/tru64_syscalls.cc
 	kern/tru64/tru64_system.cc
 
-	mem/functional_mem/memory_control.cc
-	mem/functional_mem/physical_memory.cc
-        dev/platform.cc
+	mem/functional/memory_control.cc
+	mem/functional/physical.cc
 
 	sim/system.cc
         ''')
@@ -391,7 +395,7 @@ env.Command(Split('base/traceflags.hh base/traceflags.cc'),
 # several files are generated from arch/$TARGET_ISA/isa_desc.
 env.Command(Split('''arch/alpha/decoder.cc
 		     arch/alpha/decoder.hh
-                     arch/alpha/alpha_full_cpu_exec.cc
+                     arch/alpha/alpha_o3_exec.cc
 		     arch/alpha/fast_cpu_exec.cc
                      arch/alpha/simple_cpu_exec.cc
                      arch/alpha/full_cpu_exec.cc'''),
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc
index 07bd5e800..09039db90 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/alpha_linux_process.cc
@@ -34,9 +34,9 @@
 #include <sys/types.h>
 #include <unistd.h>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "sim/fake_syscall.hh"
 #include "sim/host.hh"
 #include "sim/process.hh"
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/alpha_tru64_process.cc
index 4d73e711f..ab8558182 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/alpha_tru64_process.cc
@@ -44,9 +44,9 @@
 #include "arch/alpha/alpha_common_syscall_emul.hh"
 #include "arch/alpha/alpha_tru64_process.hh"
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "sim/fake_syscall.hh"
 #include "sim/host.hh"
 #include "sim/process.hh"
diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index 905d6b9ae..392f842fe 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -29,7 +29,7 @@
 #include "arch/alpha/arguments.hh"
 #include "arch/alpha/vtophys.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 
 AlphaArguments::Data::~Data()
 {
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index d75f4a865..9dcc9cab1 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -6,9 +6,9 @@
 #include "base/kgdb.h"
 #include "base/remote_gdb.hh"
 #include "base/stats/events.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/fast_cpu/fast_cpu.hh"
+#include "cpu/fast/cpu.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/debug.hh"
 #include "sim/sim_events.hh"
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 0e07400d3..02b9bfa09 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -41,7 +41,7 @@ output exec {{
 #ifdef FULL_SYSTEM
 #include "arch/alpha/pseudo_inst.hh"
 #endif
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
 }};
diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
index a4af891af..ff34aa19d 100644
--- a/arch/alpha/pseudo_inst.cc
+++ b/arch/alpha/pseudo_inst.cc
@@ -35,8 +35,8 @@
 
 #include "arch/alpha/pseudo_inst.hh"
 #include "arch/alpha/vtophys.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/base.hh"
+#include "cpu/sampler/sampler.hh"
 #include "cpu/exec_context.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/param.hh"
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index e26721aab..b87842f49 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -31,7 +31,7 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 
 using namespace std;
 
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 0d1320ccc..d5cdd348b 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -628,16 +628,16 @@ class CpuModel:
 # CPU-model-specific information in this file.  Note that the ISA
 # description itself should have *no* CPU-model-specific content.
 CpuModel('SimpleCPU', 'simple_cpu_exec.cc',
-         '#include "cpu/simple_cpu/simple_cpu.hh"',
+         '#include "cpu/simple/cpu.hh"',
          { 'CPU_exec_context': 'SimpleCPU' })
 CpuModel('FastCPU', 'fast_cpu_exec.cc',
-         '#include "cpu/fast_cpu/fast_cpu.hh"',
+         '#include "cpu/fast/cpu.hh"',
          { 'CPU_exec_context': 'FastCPU' })
 CpuModel('FullCPU', 'full_cpu_exec.cc',
-         '#include "cpu/full_cpu/dyn_inst.hh"',
+         '#include "encumbered/cpu/full/dyn_inst.hh"',
          { 'CPU_exec_context': 'DynInst' })
-CpuModel('AlphaFullCPU', 'alpha_full_cpu_exec.cc',
-         '#include "cpu/beta_cpu/alpha_dyn_inst.hh"',
+CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
+         '#include "cpu/o3/alpha_dyn_inst.hh"',
          { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
 
 # Expand template with CPU-specific references into a dictionary with
diff --git a/base/loader/aout_object.cc b/base/loader/aout_object.cc
index 42a376ed1..c1e49bff6 100644
--- a/base/loader/aout_object.cc
+++ b/base/loader/aout_object.cc
@@ -30,7 +30,7 @@
 
 #include "base/loader/aout_object.hh"
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF
diff --git a/base/loader/ecoff_object.cc b/base/loader/ecoff_object.cc
index 714f1d7b8..bc80ffb96 100644
--- a/base/loader/ecoff_object.cc
+++ b/base/loader/ecoff_object.cc
@@ -30,7 +30,7 @@
 
 #include "base/loader/ecoff_object.hh"
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF
diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc
index d434d199d..cec18d2f7 100644
--- a/base/loader/elf_object.cc
+++ b/base/loader/elf_object.cc
@@ -43,7 +43,7 @@
 
 #include "base/loader/elf_object.hh"
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "base/loader/symtab.hh"
 
 #include "base/trace.hh"	// for DPRINTF
diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc
index 484a01944..c3590920a 100644
--- a/base/remote_gdb.cc
+++ b/base/remote_gdb.cc
@@ -116,22 +116,20 @@
 
 #include <sys/signal.h>
 
-#include <unistd.h>
-
 #include <cstdio>
 #include <string>
+#include <unistd.h>
 
-#include "cpu/exec_context.hh"
 #include "base/intmath.hh"
 #include "base/kgdb.h"
-
-#include "mem/functional_mem/physical_memory.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
 #include "base/trace.hh"
-#include "targetarch/vtophys.hh"
-#include "sim/system.hh"
+#include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
+#include "mem/functional/physical.hh"
+#include "sim/system.hh"
+#include "targetarch/vtophys.hh"
 
 using namespace std;
 
diff --git a/cpu/base_cpu.cc b/cpu/base.cc
index fd91749f7..91ddc165e 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base.cc
@@ -34,9 +34,9 @@
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
 #include "base/output.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "sim/param.hh"
 #include "sim/sim_events.hh"
 
diff --git a/cpu/base_cpu.hh b/cpu/base.hh
index f38a6c939..0cb81e93b 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base.hh
@@ -26,13 +26,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __BASE_CPU_HH__
-#define __BASE_CPU_HH__
+#ifndef __CPU_BASE_HH__
+#define __CPU_BASE_HH__
 
 #include <vector>
 
 #include "base/statistics.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "targetarch/isa_traits.hh"
@@ -216,4 +216,4 @@ class BaseCPU : public SimObject
     Stats::Scalar<> numCycles;
 };
 
-#endif // __BASE_CPU_HH__
+#endif // __CPU_BASE_HH__
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 98a4d5b6d..5ad990c72 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -41,8 +41,8 @@
 #include "mem/mem_req.hh"
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu.hh"
 
 using namespace std;
 
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index a54e53255..2a5e07894 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -34,16 +34,15 @@
 
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
-
-#include "cpu/beta_cpu/comm.hh"
 #include "cpu/exetrace.hh"
-#include "cpu/full_cpu/bpred_update.hh"
-#include "cpu/full_cpu/op_class.hh"
-#include "cpu/full_cpu/spec_memory.hh"
-#include "cpu/full_cpu/spec_state.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/static_inst.hh"
-#include "mem/functional_mem/main_memory.hh"
+#include "encumbered/cpu/full/bpred_update.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "encumbered/cpu/full/spec_memory.hh"
+#include "encumbered/cpu/full/spec_state.hh"
+#include "encumbered/mem/functional/main.hh"
 
 /**
  * @file
diff --git a/cpu/beta_cpu/rob.cc b/cpu/beta_cpu/rob.cc
deleted file mode 100644
index ad45c022f..000000000
--- a/cpu/beta_cpu/rob.cc
+++ /dev/null
@@ -1,7 +0,0 @@
-
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/rob_impl.hh"
-
-// Force instantiation of InstructionQueue.
-template class ROB<AlphaSimpleImpl>;
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 1cb33f13e..87b064dbc 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -28,7 +28,7 @@
 
 #include <string>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 
 #ifdef FULL_SYSTEM
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index d6140d52f..3e55cb5c6 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -26,12 +26,12 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __EXEC_CONTEXT_HH__
-#define __EXEC_CONTEXT_HH__
+#ifndef __CPU_EXEC_CONTEXT_HH__
+#define __CPU_EXEC_CONTEXT_HH__
 
-#include "sim/host.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "targetarch/byte_swap.hh"
 
@@ -467,4 +467,4 @@ ExecContext::misspeculating()
     return false;
 }
 
-#endif // __EXEC_CONTEXT_HH__
+#endif // __CPU_EXEC_CONTEXT_HH__
diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc
index 048a7d283..953e1ff06 100644
--- a/cpu/exetrace.cc
+++ b/cpu/exetrace.cc
@@ -30,13 +30,13 @@
 #include <iomanip>
 
 #include "sim/param.hh"
-#include "cpu/full_cpu/dyn_inst.hh"
-#include "cpu/full_cpu/spec_state.hh"
-#include "cpu/full_cpu/issue.hh"
+#include "encumbered/cpu/full/dyn_inst.hh"
+#include "encumbered/cpu/full/spec_state.hh"
+#include "encumbered/cpu/full/issue.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/exec_context.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/static_inst.hh"
 
 using namespace std;
diff --git a/cpu/intr_control.cc b/cpu/intr_control.cc
index 53de9d288..fac0926bf 100644
--- a/cpu/intr_control.cc
+++ b/cpu/intr_control.cc
@@ -29,7 +29,7 @@
 #include <string>
 #include <vector>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/sim_object.hh"
diff --git a/cpu/intr_control.hh b/cpu/intr_control.hh
index 8cdc6b61b..6a43cd933 100644
--- a/cpu/intr_control.hh
+++ b/cpu/intr_control.hh
@@ -31,7 +31,7 @@
 
 #include <vector>
 #include "base/misc.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 #include "cpu/exec_context.hh"
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 86d03e162..728e29ff1 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -39,7 +39,6 @@
 #include "cpu/exec_context.hh"
 #include "cpu/memtest/memtest.hh"
 #include "mem/cache/base_cache.hh"
-#include "mem/functional_mem/main_memory.hh"
 #include "sim/builder.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index ed25cf374..feb50ad9b 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -32,7 +32,7 @@
 #include <set>
 
 #include "base/statistics.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_interface.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"
diff --git a/cpu/beta_cpu/2bit_local_pred.cc b/cpu/o3/2bit_local_pred.cc
index e753cbcf3..d9744eec7 100644
--- a/cpu/beta_cpu/2bit_local_pred.cc
+++ b/cpu/o3/2bit_local_pred.cc
@@ -27,7 +27,7 @@
  */
 
 #include "base/trace.hh"
-#include "cpu/beta_cpu/2bit_local_pred.hh"
+#include "cpu/o3/2bit_local_pred.hh"
 
 DefaultBP::DefaultBP(unsigned _localPredictorSize,
                      unsigned _localCtrBits,
diff --git a/cpu/beta_cpu/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index 945584e04..856407f56 100644
--- a/cpu/beta_cpu/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -31,7 +31,7 @@
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 class DefaultBP
 {
diff --git a/cpu/beta_cpu/alpha_full_cpu.cc b/cpu/o3/alpha_cpu.cc
index 862a8cc3f..7bc90dae6 100644
--- a/cpu/beta_cpu/alpha_full_cpu.cc
+++ b/cpu/o3/alpha_cpu.cc
@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu_impl.hh"
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 // Force instantiation of AlphaFullCPU for all the implemntations that are
 // needed.  Consider merging this and alpha_dyn_inst.cc, and maybe all
diff --git a/cpu/beta_cpu/alpha_full_cpu.hh b/cpu/o3/alpha_cpu.hh
index 4213979d5..386c60b0c 100644
--- a/cpu/beta_cpu/alpha_full_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -32,7 +32,7 @@
 #ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
 #define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
 
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 
 template <class Impl>
 class AlphaFullCPU : public FullBetaCPU<Impl>
diff --git a/cpu/beta_cpu/alpha_full_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index f56c9f6c3..6f4e4f0be 100644
--- a/cpu/beta_cpu/alpha_full_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -26,18 +26,16 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-
-#include "mem/cache/base_cache.hh"
-
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
 #include "mem/base_mem.hh"
+#include "mem/cache/base_cache.hh"
 #include "mem/mem_interface.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
@@ -49,16 +47,14 @@
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "dev/alpha_access.h"
-#include "dev/pciareg.h"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
 #include "targetarch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "eio/eio.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
 
 class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
diff --git a/cpu/beta_cpu/alpha_full_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 8132ec859..822d58f1f 100644
--- a/cpu/beta_cpu/alpha_full_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -8,9 +8,9 @@
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-#include "cpu/beta_cpu/alpha_params.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/comm.hh"
 
 #ifdef FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
diff --git a/cpu/beta_cpu/alpha_dyn_inst.cc b/cpu/o3/alpha_dyn_inst.cc
index 39759dd88..72ac77d95 100644
--- a/cpu/beta_cpu/alpha_dyn_inst.cc
+++ b/cpu/o3/alpha_dyn_inst.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst_impl.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_dyn_inst_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
 
 // Force instantiation of AlphaDynInst for all the implementations that
 // are needed.
diff --git a/cpu/beta_cpu/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index e4a790119..0b6b62f35 100644
--- a/cpu/beta_cpu/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -30,8 +30,8 @@
 #define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
 #include "cpu/inst_seq.hh"
 
 /**
diff --git a/cpu/beta_cpu/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 66a2cc316..437b113e4 100644
--- a/cpu/beta_cpu/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
diff --git a/cpu/beta_cpu/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 173f3b8f7..eb3c07dd3 100644
--- a/cpu/beta_cpu/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -31,8 +31,8 @@
 
 #include "arch/alpha/isa_traits.hh"
 
-#include "cpu/beta_cpu/alpha_params.hh"
-#include "cpu/beta_cpu/cpu_policy.hh"
+#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/cpu_policy.hh"
 
 // Forward declarations.
 template <class Impl>
diff --git a/cpu/beta_cpu/alpha_params.hh b/cpu/o3/alpha_params.hh
index c0379a4d9..5c8f61f3b 100644
--- a/cpu/beta_cpu/alpha_params.hh
+++ b/cpu/o3/alpha_params.hh
@@ -29,7 +29,7 @@
 #ifndef __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
 #define __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
 
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 
 //Forward declarations
 class System;
diff --git a/cpu/beta_cpu/bpred_unit.cc b/cpu/o3/bpred_unit.cc
index edf2df65a..85bd6f0a6 100644
--- a/cpu/beta_cpu/bpred_unit.cc
+++ b/cpu/o3/bpred_unit.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/bpred_unit_impl.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/bpred_unit_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 template class TwobitBPredUnit<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 960ed500c..0a77b83dc 100644
--- a/cpu/beta_cpu/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -34,10 +34,10 @@
 #include "base/statistics.hh"
 #include "cpu/inst_seq.hh"
 
-#include "cpu/beta_cpu/2bit_local_pred.hh"
-#include "cpu/beta_cpu/tournament_pred.hh"
-#include "cpu/beta_cpu/btb.hh"
-#include "cpu/beta_cpu/ras.hh"
+#include "cpu/o3/2bit_local_pred.hh"
+#include "cpu/o3/tournament_pred.hh"
+#include "cpu/o3/btb.hh"
+#include "cpu/o3/ras.hh"
 
 #include <list>
 
diff --git a/cpu/beta_cpu/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index d88c0b391..9cb2e0490 100644
--- a/cpu/beta_cpu/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -28,7 +28,7 @@
 
 #include "base/trace.hh"
 #include "base/traceflags.hh"
-#include "cpu/beta_cpu/bpred_unit.hh"
+#include "cpu/o3/bpred_unit.hh"
 
 template<class Impl>
 TwobitBPredUnit<Impl>::TwobitBPredUnit(Params &params)
diff --git a/cpu/beta_cpu/btb.cc b/cpu/o3/btb.cc
index 92864dbaa..c2bca34ae 100644
--- a/cpu/beta_cpu/btb.cc
+++ b/cpu/o3/btb.cc
@@ -28,7 +28,7 @@
 
 #include "base/intmath.hh"
 #include "base/trace.hh"
-#include "cpu/beta_cpu/btb.hh"
+#include "cpu/o3/btb.hh"
 
 DefaultBTB::DefaultBTB(unsigned _numEntries,
                        unsigned _tagBits,
diff --git a/cpu/beta_cpu/btb.hh b/cpu/o3/btb.hh
index 66ae931e4..66ae931e4 100644
--- a/cpu/beta_cpu/btb.hh
+++ b/cpu/o3/btb.hh
diff --git a/cpu/beta_cpu/comm.hh b/cpu/o3/comm.hh
index 475ab8df8..475ab8df8 100644
--- a/cpu/beta_cpu/comm.hh
+++ b/cpu/o3/comm.hh
diff --git a/cpu/beta_cpu/commit.cc b/cpu/o3/commit.cc
index 3912be07a..cf33d7f8b 100644
--- a/cpu/beta_cpu/commit.cc
+++ b/cpu/o3/commit.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/commit_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/commit_impl.hh"
 
 template class SimpleCommit<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/commit.hh b/cpu/o3/commit.hh
index 60afe1fd4..60afe1fd4 100644
--- a/cpu/beta_cpu/commit.hh
+++ b/cpu/o3/commit.hh
diff --git a/cpu/beta_cpu/commit_impl.hh b/cpu/o3/commit_impl.hh
index 22ec22c70..ac3d83174 100644
--- a/cpu/beta_cpu/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -27,7 +27,7 @@
  */
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/commit.hh"
+#include "cpu/o3/commit.hh"
 #include "cpu/exetrace.hh"
 
 template <class Impl>
diff --git a/cpu/beta_cpu/full_cpu.cc b/cpu/o3/cpu.cc
index 8eedc3769..a91c36679 100644
--- a/cpu/beta_cpu/full_cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -33,9 +33,9 @@
 #endif
 #include "sim/root.hh"
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/cpu.hh"
 #include "cpu/exec_context.hh"
 
 using namespace std;
diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/o3/cpu.hh
index 4ca8ae9ff..df86308a8 100644
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -42,9 +42,9 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/beta_cpu/comm.hh"
-#include "cpu/beta_cpu/cpu_policy.hh"
+#include "cpu/base.hh"
+#include "cpu/o3/comm.hh"
+#include "cpu/o3/cpu_policy.hh"
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
diff --git a/cpu/beta_cpu/cpu_policy.hh b/cpu/o3/cpu_policy.hh
index 88e6dca5f..2b53b436d 100644
--- a/cpu/beta_cpu/cpu_policy.hh
+++ b/cpu/o3/cpu_policy.hh
@@ -29,23 +29,23 @@
 #ifndef __CPU_BETA_CPU_CPU_POLICY_HH__
 #define __CPU_BETA_CPU_CPU_POLICY_HH__
 
-#include "cpu/beta_cpu/bpred_unit.hh"
-#include "cpu/beta_cpu/free_list.hh"
-#include "cpu/beta_cpu/inst_queue.hh"
-#include "cpu/beta_cpu/ldstq.hh"
-#include "cpu/beta_cpu/mem_dep_unit.hh"
-#include "cpu/beta_cpu/regfile.hh"
-#include "cpu/beta_cpu/rename_map.hh"
-#include "cpu/beta_cpu/rob.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/bpred_unit.hh"
+#include "cpu/o3/free_list.hh"
+#include "cpu/o3/inst_queue.hh"
+#include "cpu/o3/ldstq.hh"
+#include "cpu/o3/mem_dep_unit.hh"
+#include "cpu/o3/regfile.hh"
+#include "cpu/o3/rename_map.hh"
+#include "cpu/o3/rob.hh"
+#include "cpu/o3/store_set.hh"
 
-#include "cpu/beta_cpu/commit.hh"
-#include "cpu/beta_cpu/decode.hh"
-#include "cpu/beta_cpu/fetch.hh"
-#include "cpu/beta_cpu/iew.hh"
-#include "cpu/beta_cpu/rename.hh"
+#include "cpu/o3/commit.hh"
+#include "cpu/o3/decode.hh"
+#include "cpu/o3/fetch.hh"
+#include "cpu/o3/iew.hh"
+#include "cpu/o3/rename.hh"
 
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 template<class Impl>
 struct SimpleCPUPolicy
diff --git a/cpu/beta_cpu/decode.cc b/cpu/o3/decode.cc
index 7e57cd833..290648318 100644
--- a/cpu/beta_cpu/decode.cc
+++ b/cpu/o3/decode.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/decode_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/decode_impl.hh"
 
 template class SimpleDecode<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/decode.hh b/cpu/o3/decode.hh
index 7b89bf288..7b89bf288 100644
--- a/cpu/beta_cpu/decode.hh
+++ b/cpu/o3/decode.hh
diff --git a/cpu/beta_cpu/decode_impl.hh b/cpu/o3/decode_impl.hh
index af848341d..463f0ddac 100644
--- a/cpu/beta_cpu/decode_impl.hh
+++ b/cpu/o3/decode_impl.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/decode.hh"
+#include "cpu/o3/decode.hh"
 
 template<class Impl>
 SimpleDecode<Impl>::SimpleDecode(Params &params)
diff --git a/cpu/beta_cpu/fetch.cc b/cpu/o3/fetch.cc
index 595ab9f8e..8ad5e6565 100644
--- a/cpu/beta_cpu/fetch.cc
+++ b/cpu/o3/fetch.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/fetch_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/fetch_impl.hh"
 
 template class SimpleFetch<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/fetch.hh b/cpu/o3/fetch.hh
index ad0453ed5..ad0453ed5 100644
--- a/cpu/beta_cpu/fetch.hh
+++ b/cpu/o3/fetch.hh
diff --git a/cpu/beta_cpu/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index b49064565..83d7a02e5 100644
--- a/cpu/beta_cpu/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -35,7 +35,7 @@
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
 #include "mem/mem_req.hh"
-#include "cpu/beta_cpu/fetch.hh"
+#include "cpu/o3/fetch.hh"
 
 #include "sim/root.hh"
 
diff --git a/cpu/beta_cpu/free_list.cc b/cpu/o3/free_list.cc
index a670e4af2..6f0b4be1e 100644
--- a/cpu/beta_cpu/free_list.cc
+++ b/cpu/o3/free_list.cc
@@ -28,7 +28,7 @@
 
 #include "base/trace.hh"
 
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
 
 SimpleFreeList::SimpleFreeList(unsigned _numLogicalIntRegs,
                                unsigned _numPhysicalIntRegs,
diff --git a/cpu/beta_cpu/free_list.hh b/cpu/o3/free_list.hh
index e148acaf2..09d7557a3 100644
--- a/cpu/beta_cpu/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 /**
  * FreeList class that simply holds the list of free integer and floating
diff --git a/cpu/beta_cpu/iew.cc b/cpu/o3/iew.cc
index 42436ff20..45b5610e7 100644
--- a/cpu/beta_cpu/iew.cc
+++ b/cpu/o3/iew.cc
@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/iew_impl.hh"
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/iew_impl.hh"
+#include "cpu/o3/inst_queue.hh"
 
 template class SimpleIEW<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/iew.hh b/cpu/o3/iew.hh
index 3e5fbe78c..10979801c 100644
--- a/cpu/beta_cpu/iew.hh
+++ b/cpu/o3/iew.hh
@@ -37,7 +37,7 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 template<class Impl>
 class SimpleIEW
diff --git a/cpu/beta_cpu/iew_impl.hh b/cpu/o3/iew_impl.hh
index 39c854833..5f0d7b647 100644
--- a/cpu/beta_cpu/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -34,7 +34,7 @@
 #include <queue>
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/iew.hh"
+#include "cpu/o3/iew.hh"
 
 template<class Impl>
 SimpleIEW<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst,
diff --git a/cpu/beta_cpu/inst_queue.cc b/cpu/o3/inst_queue.cc
index 2362fe252..2ff2282b4 100644
--- a/cpu/beta_cpu/inst_queue.cc
+++ b/cpu/o3/inst_queue.cc
@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/inst_queue_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/inst_queue_impl.hh"
 
 // Force instantiation of InstructionQueue.
 template class InstructionQueue<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/inst_queue.hh b/cpu/o3/inst_queue.hh
index 02dc1222d..02dc1222d 100644
--- a/cpu/beta_cpu/inst_queue.hh
+++ b/cpu/o3/inst_queue.hh
diff --git a/cpu/beta_cpu/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh
index 51504347a..2221ba456 100644
--- a/cpu/beta_cpu/inst_queue_impl.hh
+++ b/cpu/o3/inst_queue_impl.hh
@@ -38,7 +38,7 @@
 
 #include "sim/root.hh"
 
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/inst_queue.hh"
 
 // Either compile error or max int due to sign extension.
 // Hack to avoid compile warnings.
diff --git a/cpu/beta_cpu/mem_dep_unit.cc b/cpu/o3/mem_dep_unit.cc
index 9f8831c35..9c1e7f9d8 100644
--- a/cpu/beta_cpu/mem_dep_unit.cc
+++ b/cpu/o3/mem_dep_unit.cc
@@ -26,10 +26,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/store_set.hh"
-#include "cpu/beta_cpu/mem_dep_unit_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/store_set.hh"
+#include "cpu/o3/mem_dep_unit_impl.hh"
 
 // Force instantation of memory dependency unit using store sets and
 // AlphaSimpleImpl.
diff --git a/cpu/beta_cpu/mem_dep_unit.hh b/cpu/o3/mem_dep_unit.hh
index f2bb8923a..f2bb8923a 100644
--- a/cpu/beta_cpu/mem_dep_unit.hh
+++ b/cpu/o3/mem_dep_unit.hh
diff --git a/cpu/beta_cpu/mem_dep_unit_impl.hh b/cpu/o3/mem_dep_unit_impl.hh
index e8cd88ba7..296db4c4e 100644
--- a/cpu/beta_cpu/mem_dep_unit_impl.hh
+++ b/cpu/o3/mem_dep_unit_impl.hh
@@ -28,7 +28,7 @@
 
 #include <map>
 
-#include "cpu/beta_cpu/mem_dep_unit.hh"
+#include "cpu/o3/mem_dep_unit.hh"
 
 template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)
diff --git a/cpu/beta_cpu/ras.cc b/cpu/o3/ras.cc
index 6b7bf8a09..0a7d6ca63 100644
--- a/cpu/beta_cpu/ras.cc
+++ b/cpu/o3/ras.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/ras.hh"
+#include "cpu/o3/ras.hh"
 
 ReturnAddrStack::ReturnAddrStack(unsigned _numEntries)
     : numEntries(_numEntries), usedEntries(0),
diff --git a/cpu/beta_cpu/ras.hh b/cpu/o3/ras.hh
index d0891a7fb..d0891a7fb 100644
--- a/cpu/beta_cpu/ras.hh
+++ b/cpu/o3/ras.hh
diff --git a/cpu/beta_cpu/regfile.hh b/cpu/o3/regfile.hh
index a41f68e8c..e07944e67 100644
--- a/cpu/beta_cpu/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -33,7 +33,7 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 #ifdef FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
diff --git a/cpu/beta_cpu/rename.cc b/cpu/o3/rename.cc
index 7f1ba73b6..6e9ee23da 100644
--- a/cpu/beta_cpu/rename.cc
+++ b/cpu/o3/rename.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/rename_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/rename_impl.hh"
 
 template class SimpleRename<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/rename.hh b/cpu/o3/rename.hh
index 163177d87..163177d87 100644
--- a/cpu/beta_cpu/rename.hh
+++ b/cpu/o3/rename.hh
diff --git a/cpu/beta_cpu/rename_impl.hh b/cpu/o3/rename_impl.hh
index a57f92c78..5fd62e911 100644
--- a/cpu/beta_cpu/rename_impl.hh
+++ b/cpu/o3/rename_impl.hh
@@ -28,7 +28,7 @@
 
 #include <list>
 
-#include "cpu/beta_cpu/rename.hh"
+#include "cpu/o3/rename.hh"
 
 template <class Impl>
 SimpleRename<Impl>::SimpleRename(Params &params)
diff --git a/cpu/beta_cpu/rename_map.cc b/cpu/o3/rename_map.cc
index a8ca88da9..10963f7de 100644
--- a/cpu/beta_cpu/rename_map.cc
+++ b/cpu/o3/rename_map.cc
@@ -28,7 +28,7 @@
 
 #include <vector>
 
-#include "cpu/beta_cpu/rename_map.hh"
+#include "cpu/o3/rename_map.hh"
 
 using namespace std;
 
diff --git a/cpu/beta_cpu/rename_map.hh b/cpu/o3/rename_map.hh
index 46087bae0..48bb3db19 100644
--- a/cpu/beta_cpu/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -37,7 +37,7 @@
 #include <utility>
 #include <vector>
 
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
 
 class SimpleRenameMap
 {
diff --git a/cpu/o3/rob.cc b/cpu/o3/rob.cc
new file mode 100644
index 000000000..7b590a6fe
--- /dev/null
+++ b/cpu/o3/rob.cc
@@ -0,0 +1,7 @@
+
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/rob_impl.hh"
+
+// Force instantiation of InstructionQueue.
+template class ROB<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/rob.hh b/cpu/o3/rob.hh
index b283e33ca..b283e33ca 100644
--- a/cpu/beta_cpu/rob.hh
+++ b/cpu/o3/rob.hh
diff --git a/cpu/beta_cpu/rob_impl.hh b/cpu/o3/rob_impl.hh
index dd3ffe7e6..6dea46dfc 100644
--- a/cpu/beta_cpu/rob_impl.hh
+++ b/cpu/o3/rob_impl.hh
@@ -29,7 +29,7 @@
 #ifndef __CPU_BETA_CPU_ROB_IMPL_HH__
 #define __CPU_BETA_CPU_ROB_IMPL_HH__
 
-#include "cpu/beta_cpu/rob.hh"
+#include "cpu/o3/rob.hh"
 
 template <class Impl>
 ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth)
diff --git a/cpu/beta_cpu/sat_counter.cc b/cpu/o3/sat_counter.cc
index 826234703..22fe77e3c 100644
--- a/cpu/beta_cpu/sat_counter.cc
+++ b/cpu/o3/sat_counter.cc
@@ -27,7 +27,7 @@
  */
 
 #include "base/misc.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 SatCounter::SatCounter()
     : maxVal(0), counter(0)
diff --git a/cpu/beta_cpu/sat_counter.hh b/cpu/o3/sat_counter.hh
index 5455ca56a..5455ca56a 100644
--- a/cpu/beta_cpu/sat_counter.hh
+++ b/cpu/o3/sat_counter.hh
diff --git a/cpu/beta_cpu/store_set.cc b/cpu/o3/store_set.cc
index 8b9a20c02..11023f4a8 100644
--- a/cpu/beta_cpu/store_set.cc
+++ b/cpu/o3/store_set.cc
@@ -27,7 +27,7 @@
  */
 
 #include "base/trace.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/store_set.hh"
 
 StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
     : SSIT_size(_SSIT_size), LFST_size(_LFST_size)
diff --git a/cpu/beta_cpu/store_set.hh b/cpu/o3/store_set.hh
index 98a92791a..98a92791a 100644
--- a/cpu/beta_cpu/store_set.hh
+++ b/cpu/o3/store_set.hh
diff --git a/cpu/beta_cpu/tournament_pred.cc b/cpu/o3/tournament_pred.cc
index 1b85aee51..3fb580510 100644
--- a/cpu/beta_cpu/tournament_pred.cc
+++ b/cpu/o3/tournament_pred.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/tournament_pred.hh"
+#include "cpu/o3/tournament_pred.hh"
 
 TournamentBP::TournamentBP(unsigned _local_predictor_size,
                            unsigned _local_ctr_bits,
diff --git a/cpu/beta_cpu/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index d9a14e5c8..feaede369 100644
--- a/cpu/beta_cpu/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -31,7 +31,7 @@
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 class TournamentBP
 {
diff --git a/cpu/ooo_cpu/ooo_cpu.cc b/cpu/ozone/cpu.cc
index 255070de4..255070de4 100644
--- a/cpu/ooo_cpu/ooo_cpu.cc
+++ b/cpu/ozone/cpu.cc
diff --git a/cpu/ooo_cpu/ooo_cpu.hh b/cpu/ozone/cpu.hh
index ddbc3b061..058279af1 100644
--- a/cpu/ooo_cpu/ooo_cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -30,9 +30,9 @@
 #define __CPU_OOO_CPU_OOO_CPU_HH__
 
 #include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/full_cpu/fu_pool.hh"
+#include "encumbered/cpu/full/fu_pool.hh"
 #include "cpu/ooo_cpu/ea_list.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/static_inst.hh"
diff --git a/cpu/ooo_cpu/ooo_impl.hh b/cpu/ozone/cpu_impl.hh
index 9e6df9214..9e6df9214 100644
--- a/cpu/ooo_cpu/ooo_impl.hh
+++ b/cpu/ozone/cpu_impl.hh
diff --git a/cpu/ooo_cpu/ea_list.cc b/cpu/ozone/ea_list.cc
index 4142e7f5e..4142e7f5e 100644
--- a/cpu/ooo_cpu/ea_list.cc
+++ b/cpu/ozone/ea_list.cc
diff --git a/cpu/ooo_cpu/ea_list.hh b/cpu/ozone/ea_list.hh
index bc099d7f3..bc099d7f3 100644
--- a/cpu/ooo_cpu/ea_list.hh
+++ b/cpu/ozone/ea_list.hh
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index f30e2a332..7d1e35eba 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -32,7 +32,7 @@
 #include <utility>
 
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
 #include "sim/debug.hh"
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple/cpu.cc
index f20b537f2..306398ac2 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -41,14 +41,14 @@
 #include "base/misc.hh"
 #include "base/pollevent.hh"
 #include "base/range.hh"
-#include "base/trace.hh"
 #include "base/stats/events.hh"
-#include "cpu/base_cpu.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
-#include "cpu/full_cpu/smt.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
-#include "cpu/simple_cpu/simple_cpu.hh"
+#include "cpu/sampler/sampler.hh"
+#include "cpu/simple/cpu.hh"
+#include "cpu/smt.hh"
 #include "cpu/static_inst.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
@@ -61,16 +61,14 @@
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "dev/alpha_access.h"
-#include "dev/pciareg.h"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
 #include "targetarch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "eio/eio.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
 
 using namespace std;
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple/cpu.hh
index 2056ff707..9a0c2952a 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -30,10 +30,10 @@
 #define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
 
 #include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "cpu/static_inst.hh"
 #include "sim/eventq.hh"
 
diff --git a/cpu/full_cpu/smt.hh b/cpu/smt.hh
index 6a4151ffd..6a4151ffd 100644
--- a/cpu/full_cpu/smt.hh
+++ b/cpu/smt.hh
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 4bbe8b636..e80a12960 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -32,11 +32,10 @@
 #include <bitset>
 #include <string>
 
-#include "sim/host.hh"
 #include "base/hashmap.hh"
 #include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
 #include "targetarch/isa_traits.hh"
 
 // forward declarations
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 01ce17dd5..90430268e 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
- * System Console Definition
+/** @file
+ * Alpha Console Definition
  */
 
 #include <cstddef>
@@ -37,16 +37,16 @@
 #include "base/inifile.hh"
 #include "base/str.hh"	// for to_number()
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "dev/alpha_console.hh"
 #include "dev/simconsole.hh"
 #include "dev/simple_disk.hh"
-#include "dev/tlaser_clock.hh"
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 #include "dev/tsunami_io.hh"
diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index 5685d7342..1794469f2 100644
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * System Console Interface
  */
 
@@ -44,7 +44,7 @@ class SimConsole;
 class System;
 class SimpleDisk;
 
-/*
+/**
  * Memory mapped interface to the system console. This device
  * represents a shared data region between the OS Kernel and the
  * System Console.
diff --git a/dev/baddev.cc b/dev/baddev.cc
index bb1d289ab..1d4428f7f 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * BadDevice implemenation
  */
 
@@ -41,7 +41,7 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
diff --git a/dev/baddev.hh b/dev/baddev.hh
index a9e904c62..e4aa28b37 100644
--- a/dev/baddev.hh
+++ b/dev/baddev.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * This devices just panics when touched. For example if you have a
  * kernel that touches the frame buffer which isn't allowed.
  */
diff --git a/dev/disk_image.cc b/dev/disk_image.cc
index 20e693d0d..e5bae7e59 100644
--- a/dev/disk_image.cc
+++ b/dev/disk_image.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Disk Image Definitions
  */
 
diff --git a/dev/disk_image.hh b/dev/disk_image.hh
index b21978058..1c40f27a3 100644
--- a/dev/disk_image.hh
+++ b/dev/disk_image.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Disk Image Interfaces
  */
 
@@ -40,7 +40,7 @@
 
 #define SectorSize (512)
 
-/*
+/**
  * Basic interface for accessing a disk image.
  */
 class DiskImage : public SimObject
@@ -58,7 +58,7 @@ class DiskImage : public SimObject
     virtual off_t write(const uint8_t *data, off_t offset) = 0;
 };
 
-/*
+/**
  * Specialization for accessing a raw disk image
  */
 class RawDiskImage : public DiskImage
@@ -83,7 +83,7 @@ class RawDiskImage : public DiskImage
     virtual off_t write(const uint8_t *data, off_t offset);
 };
 
-/*
+/**
  * Specialization for accessing a copy-on-write disk image layer.
  * A copy-on-write(COW) layer must be stacked on top of another disk
  * image layer this layer can be another CowDiskImage, or a
diff --git a/dev/ide_atareg.h b/dev/ide_atareg.h
new file mode 100644
index 000000000..a3a2bd604
--- /dev/null
+++ b/dev/ide_atareg.h
@@ -0,0 +1,269 @@
+/*	$OpenBSD: atareg.h,v 1.12 2004/09/24 07:15:22 grange Exp $	*/
+/*	$NetBSD: atareg.h,v 1.5 1999/01/18 20:06:24 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 1998, 2001 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_ATA_ATAREG_H_
+#define _DEV_ATA_ATAREG_H_
+
+#define ATA_BYTE_ORDER LITTLE_ENDIAN
+/*
+ * Drive parameter structure for ATA/ATAPI.
+ * Bit fields: WDC_* : common to ATA/ATAPI
+ *             ATA_* : ATA only
+ *             ATAPI_* : ATAPI only.
+ */
+struct ataparams {
+    /* drive info */
+    uint16_t	atap_config;		/* 0: general configuration */
+#define WDC_CFG_ATAPI_MASK		0xc000
+#define WDC_CFG_ATAPI			0x8000
+#define ATA_CFG_REMOVABLE		0x0080
+#define ATA_CFG_FIXED			0x0040
+#define ATAPI_CFG_TYPE_MASK		0x1f00
+#define ATAPI_CFG_TYPE(x)		(((x) & ATAPI_CFG_TYPE_MASK) >> 8)
+#define ATAPI_CFG_TYPE_DIRECT		0x00
+#define ATAPI_CFG_TYPE_SEQUENTIAL	0x01
+#define ATAPI_CFG_TYPE_CDROM		0x05
+#define ATAPI_CFG_TYPE_OPTICAL		0x07
+#define ATAPI_CFG_TYPE_NODEVICE		0x1F
+#define ATAPI_CFG_REMOV			0x0080
+#define ATAPI_CFG_DRQ_MASK		0x0060
+#define ATAPI_CFG_STD_DRQ		0x0000
+#define ATAPI_CFG_IRQ_DRQ		0x0020
+#define ATAPI_CFG_ACCEL_DRQ		0x0040
+#define ATAPI_CFG_CMD_MASK		0x0003
+#define ATAPI_CFG_CMD_12		0x0000
+#define ATAPI_CFG_CMD_16		0x0001
+/* words 1-9 are ATA only */
+    uint16_t	atap_cylinders;		/* 1: # of non-removable cylinders */
+    uint16_t	__reserved1;
+    uint16_t	atap_heads;		/* 3: # of heads */
+    uint16_t	__retired1[2];		/* 4-5: # of unform. bytes/track */
+    uint16_t	atap_sectors;		/* 6: # of sectors */
+    uint16_t	__retired2[3];
+
+    uint8_t	atap_serial[20];	/* 10-19: serial number */
+    uint16_t	__retired3[2];
+    uint16_t	__obsolete1;
+    uint8_t	atap_revision[8];	/* 23-26: firmware revision */
+    uint8_t	atap_model[40];		/* 27-46: model number */
+    uint16_t	atap_multi;		/* 47: maximum sectors per irq (ATA) */
+    uint16_t	__reserved2;
+    uint8_t	atap_vendor;	        /* 49: vendor  */
+    uint8_t	atap_capabilities1;	/* 49: capability flags */
+#define WDC_CAP_IORDY	0x0800
+#define WDC_CAP_IORDY_DSBL 0x0400
+#define WDC_CAP_LBA	0x0200
+#define WDC_CAP_DMA	0x0100
+#define ATA_CAP_STBY	0x2000
+#define ATAPI_CAP_INTERL_DMA	0x8000
+#define ATAPI_CAP_CMD_QUEUE	0x4000
+#define ATAPI_CAP_OVERLP	0x2000
+#define ATAPI_CAP_ATA_RST	0x1000
+    uint16_t	atap_capabilities2;	/* 50: capability flags (ATA) */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+    uint8_t	__junk2;
+    uint8_t	atap_oldpiotiming;	/* 51: old PIO timing mode */
+    uint8_t	__junk3;
+    uint8_t	atap_olddmatiming;	/* 52: old DMA timing mode (ATA) */
+#else
+    uint8_t	atap_oldpiotiming;	/* 51: old PIO timing mode */
+    uint8_t	__junk2;
+    uint8_t	atap_olddmatiming;	/* 52: old DMA timing mode (ATA) */
+    uint8_t	__junk3;
+#endif
+    uint16_t	atap_extensions;	/* 53: extensions supported */
+#define WDC_EXT_UDMA_MODES	0x0004
+#define WDC_EXT_MODES		0x0002
+#define WDC_EXT_GEOM		0x0001
+/* words 54-62 are ATA only */
+    uint16_t	atap_curcylinders;	/* 54: current logical cylinders */
+    uint16_t	atap_curheads;		/* 55: current logical heads */
+    uint16_t	atap_cursectors;	/* 56: current logical sectors/tracks */
+    uint16_t	atap_curcapacity[2];	/* 57-58: current capacity */
+    uint8_t	atap_curmulti;		/* 59: current multi-sector setting */
+    uint8_t	atap_curmulti_valid;	/* 59: current multi-sector setting */
+#define WDC_MULTI_VALID 0x0100
+#define WDC_MULTI_MASK  0x00ff
+    uint32_t	atap_capacity;	/* 60-61: total capacity (LBA only) */
+    uint16_t	__retired4;
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+    uint8_t	atap_dmamode_supp;	/* 63: multiword DMA mode supported */
+    uint8_t	atap_dmamode_act;	/*     multiword DMA mode active */
+    uint8_t	atap_piomode_supp;	/* 64: PIO mode supported */
+    uint8_t	__junk4;
+#else
+    uint8_t	atap_dmamode_act;	/*     multiword DMA mode active */
+    uint8_t	atap_dmamode_supp;	/* 63: multiword DMA mode supported */
+    uint8_t	__junk4;
+    uint8_t	atap_piomode_supp;	/* 64: PIO mode supported */
+#endif
+    uint16_t	atap_dmatiming_mimi;	/* 65: minimum DMA cycle time */
+    uint16_t	atap_dmatiming_recom;	/* 66: recommended DMA cycle time */
+    uint16_t	atap_piotiming;		/* 67: mini PIO cycle time without FC */
+    uint16_t	atap_piotiming_iordy;	/* 68: mini PIO cycle time with IORDY FC */
+    uint16_t	__reserved3[2];
+/* words 71-72 are ATAPI only */
+    uint16_t	atap_pkt_br;		/* 71: time (ns) to bus release */
+    uint16_t	atap_pkt_bsyclr;	/* 72: tme to clear BSY after service */
+    uint16_t	__reserved4[2];
+    uint16_t	atap_queuedepth;	/* 75: */
+#define WDC_QUEUE_DEPTH_MASK 0x1f
+    uint16_t	atap_sata_caps;		/* 76: SATA capabilities */
+#define SATA_SIGNAL_GEN1	0x0002	/* SATA Gen-1 signaling speed */
+#define SATA_SIGNAL_GEN2	0x0004	/* SATA Gen-2 signaling speed */
+#define SATA_NATIVE_CMDQ	0x0100	/* native command queuing */
+#define SATA_HOST_PWR_MGMT	0x0200	/* power management (host) */
+    uint16_t	atap_sata_reserved;	/* 77: reserved */
+    uint16_t	atap_sata_features_supp;/* 78: SATA features supported */
+#define SATA_NONZERO_OFFSETS	0x0002	/* non-zero buffer offsets */
+#define SATA_DMA_SETUP_AUTO	0x0004	/* DMA setup auto-activate */
+#define SATA_DRIVE_PWR_MGMT	0x0008	/* power management (device) */
+    uint16_t	atap_sata_features_en;	/* 79: SATA features enabled */
+    uint16_t	atap_ata_major;		/* 80: Major version number */
+#define WDC_VER_ATA1	0x0002
+#define WDC_VER_ATA2	0x0004
+#define WDC_VER_ATA3	0x0008
+#define WDC_VER_ATA4	0x0010
+#define WDC_VER_ATA5	0x0020
+#define WDC_VER_ATA6	0x0040
+#define WDC_VER_ATA7	0x0080
+#define WDC_VER_ATA8	0x0100
+#define WDC_VER_ATA9	0x0200
+#define WDC_VER_ATA10	0x0400
+#define WDC_VER_ATA11	0x0800
+#define WDC_VER_ATA12	0x1000
+#define WDC_VER_ATA13	0x2000
+#define WDC_VER_ATA14	0x4000
+    uint16_t	atap_ata_minor;		/* 81: Minor version number */
+    uint16_t	atap_cmd_set1;		/* 82: command set supported */
+#define WDC_CMD1_NOP	0x4000
+#define WDC_CMD1_RB	0x2000
+#define WDC_CMD1_WB	0x1000
+#define WDC_CMD1_HPA	0x0400
+#define WDC_CMD1_DVRST	0x0200
+#define WDC_CMD1_SRV	0x0100
+#define WDC_CMD1_RLSE	0x0080
+#define WDC_CMD1_AHEAD	0x0040
+#define WDC_CMD1_CACHE	0x0020
+#define WDC_CMD1_PKT	0x0010
+#define WDC_CMD1_PM	0x0008
+#define WDC_CMD1_REMOV	0x0004
+#define WDC_CMD1_SEC	0x0002
+#define WDC_CMD1_SMART	0x0001
+    uint16_t	atap_cmd_set2;		/* 83: command set supported */
+#define ATAPI_CMD2_FCE	0x2000 /* Flush Cache Ext supported */
+#define ATAPI_CMD2_FC	0x1000 /* Flush Cache supported */
+#define ATAPI_CMD2_DCO	0x0800 /* Device Configuration Overlay supported */
+#define ATAPI_CMD2_48AD	0x0400 /* 48bit address supported */
+#define ATAPI_CMD2_AAM	0x0200 /* Automatic Acoustic Management supported */
+#define ATAPI_CMD2_SM	0x0100 /* Set Max security extension supported */
+#define ATAPI_CMD2_SF	0x0040 /* Set Features subcommand required */
+#define ATAPI_CMD2_PUIS	0x0020 /* Power up in standby supported */
+#define WDC_CMD2_RMSN	0x0010
+#define ATA_CMD2_APM	0x0008
+#define ATA_CMD2_CFA	0x0004
+#define ATA_CMD2_RWQ	0x0002
+#define WDC_CMD2_DM	0x0001 /* Download Microcode supported */
+    uint16_t	atap_cmd_ext;		/* 84: command/features supp. ext. */
+#define ATAPI_CMDE_MSER	0x0004 /* Media serial number supported */
+#define ATAPI_CMDE_TEST	0x0002 /* SMART self-test supported */
+#define ATAPI_CMDE_SLOG	0x0001 /* SMART error logging supported */
+    uint16_t	atap_cmd1_en;		/* 85: cmd/features enabled */
+/* bits are the same as atap_cmd_set1 */
+    uint16_t	atap_cmd2_en;		/* 86: cmd/features enabled */
+/* bits are the same as atap_cmd_set2 */
+    uint16_t	atap_cmd_def;		/* 87: cmd/features default */
+/* bits are NOT the same as atap_cmd_ext */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+    uint8_t	atap_udmamode_supp;	/* 88: Ultra-DMA mode supported */
+    uint8_t	atap_udmamode_act;	/*     Ultra-DMA mode active */
+#else
+    uint8_t	atap_udmamode_act;	/*     Ultra-DMA mode active */
+    uint8_t	atap_udmamode_supp;	/* 88: Ultra-DMA mode supported */
+#endif
+/* 89-92 are ATA-only */
+    uint16_t	atap_seu_time;		/* 89: Sec. Erase Unit compl. time */
+    uint16_t	atap_eseu_time;		/* 90: Enhanced SEU compl. time */
+    uint16_t	atap_apm_val;		/* 91: current APM value */
+    uint16_t	atap_mpasswd_rev;	/* 92: Master Password revision */
+    uint16_t	atap_hwreset_res;	/* 93: Hardware reset value */
+#define ATA_HWRES_CBLID    0x2000  /* CBLID above Vih */
+#define ATA_HWRES_D1_PDIAG 0x0800  /* Device 1 PDIAG detect OK */
+#define ATA_HWRES_D1_CSEL  0x0400  /* Device 1 used CSEL for address */
+#define ATA_HWRES_D1_JUMP  0x0200  /* Device 1 jumpered to address */
+#define ATA_HWRES_D0_SEL   0x0040  /* Device 0 responds when Dev 1 selected */
+#define ATA_HWRES_D0_DASP  0x0020  /* Device 0 DASP detect OK */
+#define ATA_HWRES_D0_PDIAG 0x0010  /* Device 0 PDIAG detect OK */
+#define ATA_HWRES_D0_DIAG  0x0008  /* Device 0 diag OK */
+#define ATA_HWRES_D0_CSEL  0x0004  /* Device 0 used CSEL for address */
+#define ATA_HWRES_D0_JUMP  0x0002  /* Device 0 jumpered to address */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+    uint8_t	atap_acoustic_val;	/* 94: Current acoustic level */
+    uint8_t	atap_acoustic_def;	/*     recommended level */
+#else
+    uint8_t	atap_acoustic_def;	/*     recommended level */
+    uint8_t	atap_acoustic_val;	/* 94: Current acoustic level */
+#endif
+    uint16_t	__reserved6[5];		/* 95-99: reserved */
+    uint16_t	atap_max_lba[4];	/* 100-103: Max. user LBA add */
+    uint16_t	__reserved7[23];	/* 104-126: reserved */
+    uint16_t	atap_rmsn_supp;		/* 127: remov. media status notif. */
+#define WDC_RMSN_SUPP_MASK 0x0003
+#define WDC_RMSN_SUPP 0x0001
+    uint16_t	atap_sec_st;		/* 128: security status */
+#define WDC_SEC_LEV_MAX	0x0100
+#define WDC_SEC_ESE_SUPP 0x0020
+#define WDC_SEC_EXP	0x0010
+#define WDC_SEC_FROZEN	0x0008
+#define WDC_SEC_LOCKED	0x0004
+#define WDC_SEC_EN	0x0002
+#define WDC_SEC_SUPP	0x0001
+    uint16_t	__reserved8[31];	/* 129-159: vendor specific */
+    uint16_t	atap_cfa_power;		/* 160: CFA powermode */
+#define ATAPI_CFA_MAX_MASK  0x0FFF
+#define ATAPI_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */
+#define ATAPI_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */
+#define ATAPI_CFA_WORD160   0x8000 /* Word 160 supported */
+    uint16_t	__reserved9[15];	/* 161-175: reserved for CFA */
+    uint8_t	atap_media_serial[60];	/* 176-205: media serial number */
+    uint16_t	__reserved10[49];	/* 206-254: reserved */
+#if ATA_BYTE_ORDER == LITTLE_ENDIAN
+    uint8_t	atap_signature;		/* 255: Signature */
+    uint8_t	atap_checksum;		/*      Checksum */
+#else
+    uint8_t	atap_checksum;		/*      Checksum */
+    uint8_t	atap_signature;		/* 255: Signature */
+#endif
+};
+
+#undef ATA_BYTE_ORDER
+#endif	/* !_DEV_ATA_ATAREG_H_ */
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 35d9020db..f4b27db3c 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -33,7 +33,6 @@
 
 #include "base/trace.hh"
 #include "cpu/intr_control.hh"
-#include "dev/dma.hh"
 #include "dev/ide_ctrl.hh"
 #include "dev/ide_disk.hh"
 #include "dev/pciconfigall.hh"
@@ -43,8 +42,8 @@
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/sim_object.hh"
 
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index 28f7b634a..3825b02d1 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -42,7 +42,7 @@
 #include "dev/ide_ctrl.hh"
 #include "dev/tsunami.hh"
 #include "dev/tsunami_pchip.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 #include "mem/bus/bus.hh"
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
@@ -65,7 +65,7 @@ IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
     reset(id);
 
     // fill out the drive ID structure
-    memset(&driveID, 0, sizeof(struct hd_driveid));
+    memset(&driveID, 0, sizeof(struct ataparams));
 
     // Calculate LBA and C/H/S values
     uint16_t cylinders;
@@ -92,30 +92,30 @@ IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
     }
 
     // Setup the model name
-    sprintf((char *)driveID.model, "5MI EDD si k");
+    sprintf((char *)driveID.atap_model, "5MI EDD si k");
     // Set the maximum multisector transfer size
-    driveID.max_multsect = MAX_MULTSECT;
+    driveID.atap_multi = MAX_MULTSECT;
     // IORDY supported, IORDY disabled, LBA enabled, DMA enabled
-    driveID.capability = 0x7;
+    driveID.atap_capabilities1 = 0x7;
     // UDMA support, EIDE support
-    driveID.field_valid = 0x6;
+    driveID.atap_extensions = 0x6;
     // Setup default C/H/S settings
-    driveID.cyls = cylinders;
-    driveID.sectors = sectors;
-    driveID.heads = heads;
+    driveID.atap_cylinders = cylinders;
+    driveID.atap_sectors = sectors;
+    driveID.atap_heads = heads;
     // Setup the current multisector transfer size
-    driveID.multsect = MAX_MULTSECT;
-    driveID.multsect_valid = 0x1;
+    driveID.atap_curmulti = MAX_MULTSECT;
+    driveID.atap_curmulti_valid = 0x1;
     // Number of sectors on disk
-    driveID.lba_capacity = lba_size;
+    driveID.atap_capacity = lba_size;
     // Multiword DMA mode 2 and below supported
-    driveID.dma_mword = 0x400;
+    driveID.atap_dmamode_supp = 0x400;
     // Set PIO mode 4 and 3 supported
-    driveID.eide_pio_modes = 0x3;
+    driveID.atap_piomode_supp = 0x3;
     // Set DMA mode 4 and below supported
-    driveID.dma_ultra = 0x10;
+    driveID.atap_udmamode_supp = 0x10;
     // Statically set hardware config word
-    driveID.hw_config = 0x4001;
+    driveID.atap_hwreset_res = 0x4001;
 }
 
 IdeDisk::~IdeDisk()
@@ -632,7 +632,7 @@ IdeDisk::startCommand()
     // Decode commands
     switch (cmdReg.command) {
         // Supported non-data commands
-      case WIN_READ_NATIVE_MAX:
+      case WDSF_READ_NATIVE_MAX:
         size = image->size() - 1;
         cmdReg.sec_num = (size & 0xff);
         cmdReg.cyl_low = ((size & 0xff00) >> 8);
@@ -643,27 +643,27 @@ IdeDisk::startCommand()
         action = ACT_CMD_COMPLETE;
         break;
 
-      case WIN_RECAL:
-      case WIN_SPECIFY:
-      case WIN_STANDBYNOW1:
-      case WIN_FLUSH_CACHE:
-      case WIN_VERIFY:
-      case WIN_SEEK:
-      case WIN_SETFEATURES:
-      case WIN_SETMULT:
+      case WDCC_RECAL:
+      case WDCC_IDP:
+      case WDCC_STANDBY_IMMED:
+      case WDCC_FLUSHCACHE:
+      case WDSF_VERIFY:
+      case WDSF_SEEK:
+      case SET_FEATURES:
+      case WDCC_SETMULTI:
         devState = Command_Execution;
         action = ACT_CMD_COMPLETE;
         break;
 
         // Supported PIO data-in commands
-      case WIN_IDENTIFY:
-        cmdBytes = cmdBytesLeft = sizeof(struct hd_driveid);
+      case WDCC_IDENTIFY:
+        cmdBytes = cmdBytesLeft = sizeof(struct ataparams);
         devState = Prepare_Data_In;
         action = ACT_DATA_READY;
         break;
 
-      case WIN_MULTREAD:
-      case WIN_READ:
+      case WDCC_READMULTI:
+      case WDCC_READ:
         if (!(cmdReg.drive & DRIVE_LBA_BIT))
             panic("Attempt to perform CHS access, only supports LBA\n");
 
@@ -680,8 +680,8 @@ IdeDisk::startCommand()
         break;
 
         // Supported PIO data-out commands
-      case WIN_MULTWRITE:
-      case WIN_WRITE:
+      case WDCC_WRITEMULTI:
+      case WDCC_WRITE:
         if (!(cmdReg.drive & DRIVE_LBA_BIT))
             panic("Attempt to perform CHS access, only supports LBA\n");
 
@@ -697,9 +697,9 @@ IdeDisk::startCommand()
         break;
 
         // Supported DMA commands
-      case WIN_WRITEDMA:
+      case WDCC_WRITEDMA:
         dmaRead = true;  // a write to the disk is a DMA read from memory
-      case WIN_READDMA:
+      case WDCC_READDMA:
         if (!(cmdReg.drive & DRIVE_LBA_BIT))
             panic("Attempt to perform CHS access, only supports LBA\n");
 
@@ -850,12 +850,12 @@ IdeDisk::updateState(DevAction_t action)
             status |= STATUS_DRQ_BIT;
 
             // copy the data into the data buffer
-            if (cmdReg.command == WIN_IDENTIFY) {
+            if (cmdReg.command == WDCC_IDENTIFY) {
                 // Reset the drqBytes for this block
-                drqBytesLeft = sizeof(struct hd_driveid);
+                drqBytesLeft = sizeof(struct ataparams);
 
                 memcpy((void *)dataBuffer, (void *)&driveID,
-                       sizeof(struct hd_driveid));
+                       sizeof(struct ataparams));
             } else {
                 // Reset the drqBytes for this block
                 drqBytesLeft = SectorSize;
diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh
index 703625595..f9a413e1e 100644
--- a/dev/ide_disk.hh
+++ b/dev/ide_disk.hh
@@ -33,8 +33,9 @@
 #ifndef __IDE_DISK_HH__
 #define __IDE_DISK_HH__
 
-#include "dev/ide.hh"
 #include "dev/disk_image.hh"
+#include "dev/ide_atareg.h"
+#include "dev/ide_wdcreg.h"
 #include "dev/io_device.hh"
 #include "sim/eventq.hh"
 
@@ -204,7 +205,7 @@ class IdeDisk : public SimObject
 
   private:
     /** Drive identification structure for this disk */
-    struct hd_driveid driveID;
+    struct ataparams driveID;
     /** Data buffer for transfers */
     uint8_t *dataBuffer;
     /** Number of bytes in command data transfer */
diff --git a/dev/ide_wdcreg.h b/dev/ide_wdcreg.h
new file mode 100644
index 000000000..ed7475ec8
--- /dev/null
+++ b/dev/ide_wdcreg.h
@@ -0,0 +1,197 @@
+/*      $OpenBSD: wdcreg.h,v 1.13 2004/09/24 07:05:44 grange Exp $     */
+/*	$NetBSD: wdcreg.h,v 1.22 1999/03/07 14:02:54 bouyer Exp $	*/
+
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)wdreg.h	7.1 (Berkeley) 5/9/91
+ */
+
+#ifndef _DEV_IC_WDCREG_H_
+#define _DEV_IC_WDCREG_H_
+
+/*
+ * Controller register (wdr_ctlr)
+ */
+#define WDCTL_4BIT	0x08	/* use four head bits (wd1003) */
+#define WDCTL_RST	0x04	/* reset the controller */
+#define WDCTL_IDS	0x02	/* disable controller interrupts */
+
+/*
+ * Status bits.
+ */
+#define WDCS_BSY	0x80	/* busy */
+#define WDCS_DRDY	0x40	/* drive ready */
+#define WDCS_DWF	0x20	/* drive write fault */
+#define WDCS_DSC	0x10	/* drive seek complete */
+#define WDCS_DRQ	0x08	/* data request */
+#define WDCS_CORR	0x04	/* corrected data */
+#define WDCS_IDX	0x02	/* index */
+#define WDCS_ERR	0x01	/* error */
+#define WDCS_BITS	"\020\010BSY\007DRDY\006DWF\005DSC\004DRQ\003CORR\002IDX\001ERR"
+
+/*
+ * Error bits.
+ */
+#define WDCE_BBK	0x80	/* bad block detected */
+#define WDCE_CRC	0x80	/* CRC error (Ultra-DMA only) */
+#define WDCE_UNC	0x40	/* uncorrectable data error */
+#define WDCE_MC		0x20	/* media changed */
+#define WDCE_IDNF	0x10	/* id not found */
+#define WDCE_MCR	0x08	/* media change requested */
+#define WDCE_ABRT	0x04	/* aborted command */
+#define WDCE_TK0NF	0x02	/* track 0 not found */
+#define WDCE_AMNF	0x01	/* address mark not found */
+
+/*
+ * Commands for Disk Controller.
+ */
+#define WDCC_NOP	0x00	/* NOP - Always fail with "aborted command" */
+#define WDCC_RECAL	0x10	/* disk restore code -- resets cntlr */
+
+#define WDCC_READ	0x20	/* disk read code */
+#define WDCC_WRITE	0x30	/* disk write code */
+#define WDCC__LONG	0x02	/* modifier -- access ecc bytes */
+#define WDCC__NORETRY	0x01	/* modifier -- no retrys */
+
+#define WDCC_FORMAT	0x50	/* disk format code */
+#define WDCC_DIAGNOSE	0x90	/* controller diagnostic */
+#define WDCC_IDP	0x91	/* initialize drive parameters */
+
+#define WDCC_READMULTI	0xc4	/* read multiple */
+#define WDCC_WRITEMULTI	0xc5	/* write multiple */
+#define WDCC_SETMULTI	0xc6	/* set multiple mode */
+
+#define WDCC_READDMA	0xc8	/* read with DMA */
+#define WDCC_WRITEDMA	0xca	/* write with DMA */
+
+#define WDCC_ACKMC	0xdb	/* acknowledge media change */
+#define WDCC_LOCK	0xde	/* lock drawer */
+#define WDCC_UNLOCK	0xdf	/* unlock drawer */
+
+#define WDCC_FLUSHCACHE	0xe7	/* Flush cache */
+#define WDCC_IDENTIFY	0xec	/* read parameters from controller */
+#define SET_FEATURES	0xef	/* set features */
+
+#define WDCC_IDLE	0xe3	/* set idle timer & enter idle mode */
+#define WDCC_IDLE_IMMED	0xe1	/* enter idle mode */
+#define WDCC_SLEEP	0xe6	/* enter sleep mode */
+#define WDCC_STANDBY	0xe2	/* set standby timer & enter standby mode */
+#define WDCC_STANDBY_IMMED 0xe0	/* enter standby mode */
+#define WDCC_CHECK_PWR	0xe5	/* check power mode */
+
+#define WDCC_READ_EXT		0x24 /* read 48-bit addressing */
+#define WDCC_WRITE_EXT		0x34 /* write 48-bit addressing */
+
+#define WDCC_READMULTI_EXT	0x29 /* read multiple 48-bit addressing */
+#define WDCC_WRITEMULTI_EXT	0x39 /* write multiple 48-bit addressing */
+
+#define WDCC_READDMA_EXT	0x25 /* read 48-bit addressing with DMA */
+#define WDCC_WRITEDMA_EXT	0x35 /* write 48-bit addressing with DMA */
+
+#define WDCC_FLUSHCACHE_EXT	0xea /* 48-bit addressing flush cache */
+
+/* Subcommands for SET_FEATURES (features register ) */
+#define WDSF_8BIT_PIO_EN	0x01 /* Enable 8bit PIO (CFA featureset) */
+#define WDSF_EN_WR_CACHE	0x02
+#define WDSF_SET_MODE		0x03
+#define WDSF_REASSIGN_EN	0x04 /* Obsolete in ATA-6 */
+#define WDSF_APM_EN		0x05 /* Enable Adv. Power Management */
+#define WDSF_PUIS_EN		0x06 /* Enable Power-Up In Standby */
+#define WDSF_PUIS_SPINUP	0x07 /* Power-Up In Standby spin-up */
+#define WDSF_CFA_MODE1_EN	0x0A /* Enable CFA power mode 1 */
+#define WDSF_RMSN_DS		0x31 /* Disable Removable Media Status */
+#define WDSF_RETRY_DS		0x33 /* Obsolete in ATA-6 */
+#define WDSF_AAM_EN		0x42 /* Enable Autom. Acoustic Management */
+#define WDSF_SET_CACHE_SGMT	0x54 /* Obsolete in ATA-6 */
+#define WDSF_READAHEAD_DS	0x55 /* Disable read look-ahead */
+#define WDSF_RLSE_EN		0x5D /* Enable release interrupt */
+#define WDSF_SRV_EN		0x5E /* Enable SERVICE interrupt */
+#define WDSF_POD_DS		0x66
+#define WDSF_ECC_DS		0x77
+#define WDSF_8BIT_PIO_DS	0x81 /* Disable 8bit PIO (CFA featureset) */
+#define WDSF_WRITE_CACHE_DS	0x82
+#define WDSF_REASSIGN_DS	0x84
+#define WDSF_APM_DS		0x85 /* Disable Adv. Power Management */
+#define WDSF_PUIS_DS		0x86 /* Disable Power-Up In Standby */
+#define WDSF_ECC_EN		0x88
+#define WDSF_CFA_MODE1_DS	0x8A /* Disable CFA power mode 1 */
+#define WDSF_RMSN_EN		0x95 /* Enable Removable Media Status */
+#define WDSF_RETRY_EN		0x99 /* Obsolete in ATA-6 */
+#define WDSF_SET_CURRENT	0x9A /* Obsolete in ATA-6 */
+#define WDSF_READAHEAD_EN	0xAA
+#define WDSF_PREFETCH_SET	0xAB /* Obsolete in ATA-6 */
+#define WDSF_AAM_DS		0xC2 /* Disable Autom. Acoustic Management */
+#define WDSF_POD_EN		0xCC
+#define WDSF_RLSE_DS		0xDD /* Disable release interrupt */
+#define WDSF_SRV_DS		0xDE /* Disable SERVICE interrupt */
+#define WDSF_READ_NATIVE_MAX    0xF8
+#define WDSF_SEEK               0x70
+#define WDSF_VERIFY             0x40
+
+/* parameters uploaded to device/heads register */
+#define WDSD_IBM	0xa0	/* forced to 512 byte sector, ecc */
+#define WDSD_CHS	0x00	/* cylinder/head/sector addressing */
+#define WDSD_LBA	0x40	/* logical block addressing */
+
+/* Commands for ATAPI devices */
+#define ATAPI_CHECK_POWER_MODE	0xe5
+#define ATAPI_EXEC_DRIVE_DIAGS	0x90
+#define ATAPI_IDLE_IMMEDIATE	0xe1
+#define ATAPI_NOP		0x00
+#define ATAPI_PKT_CMD		0xa0
+#define ATAPI_IDENTIFY_DEVICE	0xa1
+#define ATAPI_SOFT_RESET	0x08
+#define ATAPI_DEVICE_RESET	0x08 /* ATA/ATAPI-5 name for soft reset */
+#define ATAPI_SLEEP		0xe6
+#define ATAPI_STANDBY_IMMEDIATE	0xe0
+#define ATAPI_SMART		0xB0 /* SMART operations */
+#define ATAPI_SETMAX		0xF9 /* Set Max Address */
+#define ATAPI_WRITEEXT		0x34 /* Write sectors Ext */
+#define ATAPI_SETMAXEXT		0x37 /* Set Max Address Ext */
+#define ATAPI_WRITEMULTIEXT	0x39 /* Write Multi Ext */
+
+/* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */
+#define ATAPI_PKT_CMD_FTRE_DMA	0x01
+#define ATAPI_PKT_CMD_FTRE_OVL	0x02
+
+/* ireason */
+#define WDCI_CMD	0x01 /* command(1) or data(0) */
+#define WDCI_IN		0x02 /* transfer to(1) or from(0) the host */
+#define WDCI_RELEASE	0x04 /* bus released until completion */
+
+#define PHASE_CMDOUT	(WDCS_DRQ | WDCI_CMD)
+#define PHASE_DATAIN	(WDCS_DRQ | WDCI_IN)
+#define PHASE_DATAOUT	WDCS_DRQ
+#define PHASE_COMPLETED	(WDCI_IN | WDCI_CMD)
+#define PHASE_ABORTED	0
+
+#endif	/* !_DEV_IC_WDCREG_H_ */
diff --git a/dev/io_device.hh b/dev/io_device.hh
index 649706956..8ab88e6ff 100644
--- a/dev/io_device.hh
+++ b/dev/io_device.hh
@@ -29,7 +29,7 @@
 #ifndef __DEV_IO_DEVICE_HH__
 #define __DEV_IO_DEVICE_HH__
 
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 
 class BaseInterface;
 class Bus;
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 637cd7825..0526c2779 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Device module for modelling the National Semiconductor
  * DP83820 ethernet controller.  Does not support priority queueing
  */
@@ -36,7 +36,6 @@
 
 #include "base/inet.hh"
 #include "cpu/exec_context.hh"
-#include "dev/dma.hh"
 #include "dev/etherlink.hh"
 #include "dev/ns_gige.hh"
 #include "dev/pciconfigall.hh"
@@ -44,8 +43,8 @@
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 302aa5a89..a1e90a375 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Device module for modelling the National Semiconductor
  * DP83820 ethernet controller
  */
diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h
index d73a6c6b2..be53149e7 100644
--- a/dev/ns_gige_reg.h
+++ b/dev/ns_gige_reg.h
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Ethernet device register definitions for the National
  * Semiconductor DP83820 Ethernet controller
  */
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index fd0732d50..c7af8b1d1 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -42,7 +42,7 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 850635d49..9d568e6cc 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -39,11 +39,10 @@
 #include "base/misc.hh"
 #include "base/str.hh"	// for to_number
 #include "base/trace.hh"
-#include "dev/pciareg.h"
 #include "dev/pcidev.hh"
 #include "dev/pciconfigall.hh"
 #include "mem/bus/bus.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/param.hh"
 #include "sim/root.hh"
diff --git a/dev/simconsole.cc b/dev/simconsole.cc
index 94fd9ec1f..1d04e1f95 100644
--- a/dev/simconsole.cc
+++ b/dev/simconsole.cc
@@ -49,7 +49,7 @@
 #include "dev/platform.hh"
 #include "dev/simconsole.hh"
 #include "dev/uart.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 
 using namespace std;
diff --git a/dev/simple_disk.cc b/dev/simple_disk.cc
index 19e8683df..a33b4fe1b 100644
--- a/dev/simple_disk.cc
+++ b/dev/simple_disk.cc
@@ -42,7 +42,7 @@
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
 #include "dev/simple_disk.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 
 using namespace std;
diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh
index 3031cdb8b..633acba0d 100644
--- a/dev/simple_disk.hh
+++ b/dev/simple_disk.hh
@@ -30,13 +30,14 @@
  * Simple disk interface for the system console
  */
 
-#ifndef __SIMPLE_DISK_HH__
-#define __SIMPLE_DISK_HH__
+#ifndef __DEV_SIMPLE_DISK_HH__
+#define __DEV_SIMPLE_DISK_HH__
 
-#include "mem/functional_mem/physical_memory.hh"
 #include "sim/sim_object.hh"
+#include "targetarch/isa_traits.hh"
 
 class DiskImage;
+class PhysicalMemory;
 
 /*
  * Trivial interface to a disk image used by the System Console
@@ -57,4 +58,5 @@ public:
   void read(Addr addr, baddr_t block, int count) const;
   void write(Addr addr, baddr_t block, int count);
 };
-#endif // __SIMPLE_DISK_HH__
+
+#endif // __DEV_SIMPLE_DISK_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 5125a1d68..e5cd877a0 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -33,7 +33,6 @@
 #include "base/inet.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/intr_control.hh"
-#include "dev/dma.hh"
 #include "dev/etherlink.hh"
 #include "dev/sinic.hh"
 #include "dev/pciconfigall.hh"
@@ -41,8 +40,8 @@
 #include "mem/bus/dma_interface.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/eventq.hh"
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index 55a2c5ea6..2f8d9b804 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -26,15 +26,16 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+/** @file Implementation of Tsunami platform.
+ */
+
 #include <deque>
 #include <string>
 #include <vector>
 
 #include "cpu/intr_control.hh"
 #include "dev/simconsole.hh"
-#include "dev/etherdev.hh"
 #include "dev/ide_ctrl.hh"
-#include "dev/tlaser_clock.hh"
 #include "dev/tsunami_cchip.hh"
 #include "dev/tsunami_pchip.hh"
 #include "dev/tsunami_io.hh"
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index a10dba082..2294a0bcf 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Emulation of the Tsunami CChip CSRs
  */
 
@@ -41,7 +41,7 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index 05fafa782..d33905bc0 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Emulation of the Tsunami CChip CSRs
  */
 
@@ -37,8 +37,9 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 
-/*
- * Tsunami CChip
+/**
+ * Tsunami CChip CSR Emulation. This device includes all the interrupt
+ * handling code for the chipset.
  */
 class TsunamiCChip : public PioDevice
 {
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 2e12b41ea..da1062237 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Tsunami I/O including PIC, PIT, RTC, DMA
  */
 
@@ -46,7 +46,7 @@
 #include "dev/tsunami_cchip.hh"
 #include "dev/tsunamireg.h"
 #include "dev/rtcreg.h"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 
 using namespace std;
 
diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh
index 9d74ccdef..704eb11f3 100644
--- a/dev/tsunami_io.hh
+++ b/dev/tsunami_io.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
- * Tsunami Fake I/O Space mapping including RTC/timer interrupts
+/** @file
+ * Tsunami I/O Space mapping including RTC/timer interrupts
  */
 
 #ifndef __DEV_TSUNAMI_IO_HH__
@@ -38,7 +38,7 @@
 #include "dev/tsunami.hh"
 #include "sim/eventq.hh"
 
-/*
+/**
  * Tsunami I/O device is a catch all for all the south bridge stuff we care
  * to implement.
  */
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index f8bec77c0..40bec1f68 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Tsunami PChip (pci)
  */
 
@@ -41,8 +41,8 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh
index f88098d58..5a50cb548 100644
--- a/dev/tsunami_pchip.hh
+++ b/dev/tsunami_pchip.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
- * Tsunami PChip
+/** @file
+ * Tsunami PCI interface CSRs
  */
 
 #ifndef __TSUNAMI_PCHIP_HH__
@@ -37,8 +37,8 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 
-/*
- * Tsunami PChip
+/**
+ * A very simple implementation of the Tsunami PCI interface chips.
  */
 class TsunamiPChip : public PioDevice
 {
diff --git a/dev/tsunamireg.h b/dev/tsunamireg.h
index 290f21a5b..df10ce29d 100644
--- a/dev/tsunamireg.h
+++ b/dev/tsunamireg.h
@@ -26,6 +26,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+/** @file
+ * List of Tsunami CSRs
+ */
+
 #ifndef __TSUNAMIREG_H__
 #define __TSUNAMIREG_H__
 
diff --git a/dev/uart.cc b/dev/uart.cc
index c04a5d066..3daf195d3 100644
--- a/dev/uart.cc
+++ b/dev/uart.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
+/** @file
  * Implements a 8250 UART
  */
 
@@ -42,65 +42,14 @@
 #include "mem/bus/bus.hh"
 #include "mem/bus/pio_interface.hh"
 #include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 
 using namespace std;
 
-Uart::IntrEvent::IntrEvent(Uart *u, int bit)
-    : Event(&mainEventQueue), uart(u)
-{
-    DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
-    intrBit = bit;
-}
-
-const char *
-Uart::IntrEvent::description()
-{
-    return "uart interrupt delay event";
-}
-
-void
-Uart::IntrEvent::process()
-{
-    if (intrBit & uart->IER) {
-       DPRINTF(Uart, "UART InterEvent, interrupting\n");
-       uart->platform->postConsoleInt();
-       uart->status |= intrBit;
-    }
-    else
-       DPRINTF(Uart, "UART InterEvent, not interrupting\n");
-
-}
-
-/* The linux serial driver (8250.c about line 1182) loops reading from
- * the device until the device reports it has no more data to
- * read. After a maximum of 255 iterations the code prints "serial8250
- * too much work for irq X," and breaks out of the loop. Since the
- * simulated system is so much slower than the actual system, if a
- * user is typing on the keyboard it is very easy for them to provide
- * input at a fast enough rate to not allow the loop to exit and thus
- * the error to be printed. This magic number provides a delay between
- * the time the UART receives a character to send to the simulated
- * system and the time it actually notifies the system it has a
- * character to send to alleviate this problem. --Ali
- */
-void
-Uart::IntrEvent::scheduleIntr()
-{
-    static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
-    DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
-            curTick + interval);
-    if (!scheduled())
-        schedule(curTick + interval);
-    else
-        reschedule(curTick + interval);
-}
-
 Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
            Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
-    : PioDevice(name, p), addr(a), size(s), cons(c),
-      txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
+    : PioDevice(name, p), addr(a), size(s), cons(c)
 {
     mmu->add_child(this, RangeSize(addr, size));
 
@@ -112,270 +61,11 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
         pioLatency = pio_latency * bus->clockRate;
     }
 
-    readAddr = 0;
-    IER = 0;
-    DLAB = 0;
-    LCR = 0;
-    MCR = 0;
     status = 0;
 
     // set back pointers
     cons->uart = this;
     platform->uart = this;
-
-}
-
-Fault
-Uart::read(MemReqPtr &req, uint8_t *data)
-{
-    Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
-    DPRINTF(Uart, " read register %#x\n", daddr);
-
-
-
-#ifdef ALPHA_TLASER
-
-    switch (req->size) {
-      case sizeof(uint64_t):
-        *(uint64_t *)data = 0;
-        break;
-      case sizeof(uint32_t):
-        *(uint32_t *)data = 0;
-        break;
-      case sizeof(uint16_t):
-        *(uint16_t *)data = 0;
-        break;
-      case sizeof(uint8_t):
-        *(uint8_t *)data = 0;
-        break;
-    }
-
-    switch (daddr) {
-      case 0x80: // Status Register
-        if (readAddr == 3) {
-            readAddr = 0;
-            if (status & TX_INT)
-                *data = (1 << 4);
-             else if (status & RX_INT)
-                *data = (1 << 5);
-             else
-                DPRINTF(Uart, "spurious read\n");
-
-        } else {
-            *data = (1 << 2);
-            if (status & RX_INT)
-                *data |= (1 << 0);
-        }
-        break;
-
-      case 0xc0: // Data register (RX)
-        if (!cons->dataAvailable())
-            panic("No data to read");
-
-        cons->in(*data);
-
-        if (!cons->dataAvailable()) {
-            platform->clearConsoleInt();
-            status &= ~RX_INT;
-        }
-
-        DPRINTF(Uart, "read data register \'%c\' %2x\n",
-                isprint(*data) ? *data : ' ', *data);
-        break;
-    }
-
-
-#else
-
-
-    assert(req->size == 1);
-
-    switch (daddr) {
-        case 0x0:
-            if (!(LCR & 0x80)) { // read byte
-                if (cons->dataAvailable())
-                    cons->in(*data);
-                else {
-                    *(uint8_t*)data = 0;
-                    // A limited amount of these are ok.
-                    DPRINTF(Uart, "empty read of RX register\n");
-                }
-                status &= ~RX_INT;
-                platform->clearConsoleInt();
-
-                if (cons->dataAvailable() && (IER & UART_IER_RDI))
-                    rxIntrEvent.scheduleIntr();
-            } else { // dll divisor latch
-               ;
-            }
-            break;
-        case 0x1:
-            if (!(LCR & 0x80)) { // Intr Enable Register(IER)
-                *(uint8_t*)data = IER;
-            } else { // DLM divisor latch MSB
-                ;
-            }
-            break;
-        case 0x2: // Intr Identification Register (IIR)
-            DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
-            if (status)
-                *(uint8_t*)data = 0;
-            else
-                *(uint8_t*)data = 1;
-            break;
-        case 0x3: // Line Control Register (LCR)
-            *(uint8_t*)data = LCR;
-            break;
-        case 0x4: // Modem Control Register (MCR)
-            break;
-        case 0x5: // Line Status Register (LSR)
-            uint8_t lsr;
-            lsr = 0;
-            // check if there are any bytes to be read
-            if (cons->dataAvailable())
-                lsr = UART_LSR_DR;
-            lsr |= UART_LSR_TEMT | UART_LSR_THRE;
-            *(uint8_t*)data = lsr;
-            break;
-        case 0x6: // Modem Status Register (MSR)
-            *(uint8_t*)data = 0;
-            break;
-        case 0x7: // Scratch Register (SCR)
-            *(uint8_t*)data = 0; // doesn't exist with at 8250.
-            break;
-        default:
-            panic("Tried to access a UART port that doesn't exist\n");
-            break;
-    }
-
-#endif
-    return No_Fault;
-
-}
-
-Fault
-Uart::write(MemReqPtr &req, const uint8_t *data)
-{
-    Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
-
-    DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
-
-#ifdef ALPHA_TLASER
-
-    switch (daddr) {
-      case 0x80:
-        readAddr = *data;
-        switch (*data) {
-          case 0x28: // Ack of TX
-              if ((status & TX_INT) == 0)
-                  panic("Ack of transmit, though there was no interrupt");
-
-              status &= ~TX_INT;
-              platform->clearConsoleInt();
-              break;
-          case 0x00:
-          case 0x01:
-          case 0x03: // going to read RR3
-          case 0x12:
-                break;
-          default:
-                DPRINTF(Uart, "writing status register %#x \n",
-                        *(uint64_t *)data);
-                break;
-        }
-        break;
-
-      case 0xc0: // Data register (TX)
-        cons->out(*(uint64_t *)data);
-        platform->postConsoleInt();
-        status |= TX_INT;
-        break;
-    }
-
-
-#else
-    switch (daddr) {
-        case 0x0:
-            if (!(LCR & 0x80)) { // write byte
-                cons->out(*(uint8_t *)data);
-                platform->clearConsoleInt();
-                status &= ~TX_INT;
-                if (UART_IER_THRI & IER)
-                    txIntrEvent.scheduleIntr();
-            } else { // dll divisor latch
-               ;
-            }
-            break;
-        case 0x1:
-            if (!(LCR & 0x80)) { // Intr Enable Register(IER)
-                IER = *(uint8_t*)data;
-                if (UART_IER_THRI & IER)
-                {
-                    DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
-                    txIntrEvent.scheduleIntr();
-                }
-                else
-                {
-                    DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
-                    if (txIntrEvent.scheduled())
-                        txIntrEvent.deschedule();
-                    if (status & TX_INT)
-                        platform->clearConsoleInt();
-                    status &= ~TX_INT;
-                }
-
-                if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
-                    DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
-                    rxIntrEvent.scheduleIntr();
-                } else {
-                    DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
-                    if (rxIntrEvent.scheduled())
-                        rxIntrEvent.deschedule();
-                    if (status & RX_INT)
-                        platform->clearConsoleInt();
-                    status &= ~RX_INT;
-                }
-             } else { // DLM divisor latch MSB
-                ;
-            }
-            break;
-        case 0x2: // FIFO Control Register (FCR)
-            break;
-        case 0x3: // Line Control Register (LCR)
-            LCR = *(uint8_t*)data;
-            break;
-        case 0x4: // Modem Control Register (MCR)
-            if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
-                    MCR = 0x9A;
-            break;
-        case 0x7: // Scratch Register (SCR)
-            // We are emulating a 8250 so we don't have a scratch reg
-            break;
-        default:
-            panic("Tried to access a UART port that doesn't exist\n");
-            break;
-    }
-#endif
-
-    return No_Fault;
-}
-
-void
-Uart::dataAvailable()
-{
-#ifdef ALPHA_TLASER
-        platform->postConsoleInt();
-        status |= RX_INT;
-#else
-
-    // if the kernel wants an interrupt when we have data
-    if (IER & UART_IER_RDI)
-    {
-        platform->postConsoleInt();
-        status |= RX_INT;
-    }
-
-#endif
 }
 
 Tick
@@ -384,88 +74,5 @@ Uart::cacheAccess(MemReqPtr &req)
     return curTick + pioLatency;
 }
 
-void
-Uart::serialize(ostream &os)
-{
-#ifdef ALPHA_TLASER
-    SERIALIZE_SCALAR(readAddr);
-    SERIALIZE_SCALAR(status);
-#else
-    SERIALIZE_SCALAR(status);
-    SERIALIZE_SCALAR(IER);
-    SERIALIZE_SCALAR(DLAB);
-    SERIALIZE_SCALAR(LCR);
-    SERIALIZE_SCALAR(MCR);
-    Tick rxintrwhen;
-    if (rxIntrEvent.scheduled())
-        rxintrwhen = rxIntrEvent.when();
-    else
-        rxintrwhen = 0;
-    Tick txintrwhen;
-    if (txIntrEvent.scheduled())
-        txintrwhen = txIntrEvent.when();
-    else
-        txintrwhen = 0;
-     SERIALIZE_SCALAR(rxintrwhen);
-     SERIALIZE_SCALAR(txintrwhen);
-#endif
-}
-
-void
-Uart::unserialize(Checkpoint *cp, const std::string &section)
-{
-#ifdef ALPHA_TLASER
-    UNSERIALIZE_SCALAR(readAddr);
-    UNSERIALIZE_SCALAR(status);
-#else
-    UNSERIALIZE_SCALAR(status);
-    UNSERIALIZE_SCALAR(IER);
-    UNSERIALIZE_SCALAR(DLAB);
-    UNSERIALIZE_SCALAR(LCR);
-    UNSERIALIZE_SCALAR(MCR);
-    Tick rxintrwhen;
-    Tick txintrwhen;
-    UNSERIALIZE_SCALAR(rxintrwhen);
-    UNSERIALIZE_SCALAR(txintrwhen);
-    if (rxintrwhen != 0)
-        rxIntrEvent.schedule(rxintrwhen);
-    if (txintrwhen != 0)
-        txIntrEvent.schedule(txintrwhen);
-#endif
-
-}
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart)
-
-    SimObjectParam<SimConsole *> console;
-    SimObjectParam<MemoryController *> mmu;
-    SimObjectParam<Platform *> platform;
-    Param<Addr> addr;
-    Param<Addr> size;
-    SimObjectParam<Bus*> io_bus;
-    Param<Tick> pio_latency;
-    SimObjectParam<HierParams *> hier;
-
-
-END_DECLARE_SIM_OBJECT_PARAMS(Uart)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Uart)
-
-    INIT_PARAM(console, "The console"),
-    INIT_PARAM(mmu, "Memory Controller"),
-    INIT_PARAM(platform, "Pointer to platfrom"),
-    INIT_PARAM(addr, "Device Address"),
-    INIT_PARAM_DFLT(size, "Device size", 0x8),
-    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
-
-END_INIT_SIM_OBJECT_PARAMS(Uart)
-
-CREATE_SIM_OBJECT(Uart)
-{
-    return new Uart(getInstanceName(), console, mmu, addr, size, hier, io_bus,
-                    pio_latency, platform);
-}
+DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
 
-REGISTER_SIM_OBJECT("Uart", Uart)
diff --git a/dev/uart.hh b/dev/uart.hh
index d1f167526..a2be3fb8e 100644
--- a/dev/uart.hh
+++ b/dev/uart.hh
@@ -26,14 +26,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-/* @file
- * Defines a 8250 UART
+/** @file
+ * Base class for UART
  */
 
-#ifndef __TSUNAMI_UART_HH__
-#define __TSUNAMI_UART_HH__
+#ifndef __UART_HH__
+#define __UART_HH__
 
-#include "dev/tsunamireg.h"
 #include "base/range.hh"
 #include "dev/io_device.hh"
 
@@ -47,45 +46,25 @@ const int TX_INT = 0x2;
 class Uart : public PioDevice
 {
 
-  private:
+  protected:
+    int status;
     Addr addr;
     Addr size;
     SimConsole *cons;
 
-
-  protected:
-    int readAddr; // tlaser only
-    uint8_t IER, DLAB, LCR, MCR;
-    int status;
-
-    class IntrEvent : public Event
-    {
-        protected:
-            Uart *uart;
-            int intrBit;
-        public:
-            IntrEvent(Uart *u, int bit);
-            virtual void process();
-            virtual const char *description();
-            void scheduleIntr();
-    };
-
-    IntrEvent txIntrEvent;
-    IntrEvent rxIntrEvent;
-
   public:
     Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
          Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
          Platform *p);
 
-    Fault read(MemReqPtr &req, uint8_t *data);
-    Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
+    virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
 
 
     /**
      * Inform the uart that there is data available.
      */
-    void dataAvailable();
+    virtual void dataAvailable() = 0;
 
 
     /**
@@ -94,9 +73,6 @@ class Uart : public PioDevice
      */
     bool intStatus() { return status ? true : false; }
 
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
     /**
      * Return how long this access will take.
      * @param req the memory request to calcuate
@@ -105,4 +81,4 @@ class Uart : public PioDevice
     Tick cacheAccess(MemReqPtr &req);
 };
 
-#endif // __TSUNAMI_UART_HH__
+#endif // __UART_HH__
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
new file mode 100644
index 000000000..93e153319
--- /dev/null
+++ b/dev/uart8250.cc
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @file
+ * Implements a 8250 UART
+ */
+
+#include <string>
+#include <vector>
+
+#include "base/inifile.hh"
+#include "base/str.hh"        // for to_number
+#include "base/trace.hh"
+#include "dev/simconsole.hh"
+#include "dev/uart8250.hh"
+#include "dev/platform.hh"
+#include "mem/bus/bus.hh"
+#include "mem/bus/pio_interface.hh"
+#include "mem/bus/pio_interface_impl.hh"
+#include "mem/functional_mem/memory_control.hh"
+#include "sim/builder.hh"
+
+using namespace std;
+
+Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
+    : Event(&mainEventQueue), uart(u)
+{
+    DPRINTF(Uart, "UART Interrupt Event Initilizing\n");
+    intrBit = bit;
+}
+
+const char *
+Uart8250::IntrEvent::description()
+{
+    return "uart interrupt delay event";
+}
+
+void
+Uart8250::IntrEvent::process()
+{
+    if (intrBit & uart->IER) {
+       DPRINTF(Uart, "UART InterEvent, interrupting\n");
+       uart->platform->postConsoleInt();
+       uart->status |= intrBit;
+    }
+    else
+       DPRINTF(Uart, "UART InterEvent, not interrupting\n");
+
+}
+
+/* The linux serial driver (8250.c about line 1182) loops reading from
+ * the device until the device reports it has no more data to
+ * read. After a maximum of 255 iterations the code prints "serial8250
+ * too much work for irq X," and breaks out of the loop. Since the
+ * simulated system is so much slower than the actual system, if a
+ * user is typing on the keyboard it is very easy for them to provide
+ * input at a fast enough rate to not allow the loop to exit and thus
+ * the error to be printed. This magic number provides a delay between
+ * the time the UART receives a character to send to the simulated
+ * system and the time it actually notifies the system it has a
+ * character to send to alleviate this problem. --Ali
+ */
+void
+Uart8250::IntrEvent::scheduleIntr()
+{
+    static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
+    DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
+            curTick + interval);
+    if (!scheduled())
+        schedule(curTick + interval);
+    else
+        reschedule(curTick + interval);
+}
+
+
+Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
+           Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
+    : Uart(name, c, mmu, a, s, hier, bus, pio_latency, p),
+      txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
+{
+    IER = 0;
+    DLAB = 0;
+    LCR = 0;
+    MCR = 0;
+
+}
+
+Fault
+Uart8250::read(MemReqPtr &req, uint8_t *data)
+{
+    Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
+    DPRINTF(Uart, " read register %#x\n", daddr);
+
+    assert(req->size == 1);
+
+    switch (daddr) {
+        case 0x0:
+            if (!(LCR & 0x80)) { // read byte
+                if (cons->dataAvailable())
+                    cons->in(*data);
+                else {
+                    *(uint8_t*)data = 0;
+                    // A limited amount of these are ok.
+                    DPRINTF(Uart, "empty read of RX register\n");
+                }
+                status &= ~RX_INT;
+                platform->clearConsoleInt();
+
+                if (cons->dataAvailable() && (IER & UART_IER_RDI))
+                    rxIntrEvent.scheduleIntr();
+            } else { // dll divisor latch
+               ;
+            }
+            break;
+        case 0x1:
+            if (!(LCR & 0x80)) { // Intr Enable Register(IER)
+                *(uint8_t*)data = IER;
+            } else { // DLM divisor latch MSB
+                ;
+            }
+            break;
+        case 0x2: // Intr Identification Register (IIR)
+            DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
+            if (status)
+                *(uint8_t*)data = 0;
+            else
+                *(uint8_t*)data = 1;
+            break;
+        case 0x3: // Line Control Register (LCR)
+            *(uint8_t*)data = LCR;
+            break;
+        case 0x4: // Modem Control Register (MCR)
+            break;
+        case 0x5: // Line Status Register (LSR)
+            uint8_t lsr;
+            lsr = 0;
+            // check if there are any bytes to be read
+            if (cons->dataAvailable())
+                lsr = UART_LSR_DR;
+            lsr |= UART_LSR_TEMT | UART_LSR_THRE;
+            *(uint8_t*)data = lsr;
+            break;
+        case 0x6: // Modem Status Register (MSR)
+            *(uint8_t*)data = 0;
+            break;
+        case 0x7: // Scratch Register (SCR)
+            *(uint8_t*)data = 0; // doesn't exist with at 8250.
+            break;
+        default:
+            panic("Tried to access a UART port that doesn't exist\n");
+            break;
+    }
+
+    return No_Fault;
+
+}
+
+Fault
+Uart8250::write(MemReqPtr &req, const uint8_t *data)
+{
+    Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
+
+    DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
+
+    switch (daddr) {
+        case 0x0:
+            if (!(LCR & 0x80)) { // write byte
+                cons->out(*(uint8_t *)data);
+                platform->clearConsoleInt();
+                status &= ~TX_INT;
+                if (UART_IER_THRI & IER)
+                    txIntrEvent.scheduleIntr();
+            } else { // dll divisor latch
+               ;
+            }
+            break;
+        case 0x1:
+            if (!(LCR & 0x80)) { // Intr Enable Register(IER)
+                IER = *(uint8_t*)data;
+                if (UART_IER_THRI & IER)
+                {
+                    DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
+                    txIntrEvent.scheduleIntr();
+                }
+                else
+                {
+                    DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
+                    if (txIntrEvent.scheduled())
+                        txIntrEvent.deschedule();
+                    if (status & TX_INT)
+                        platform->clearConsoleInt();
+                    status &= ~TX_INT;
+                }
+
+                if ((UART_IER_RDI & IER) && cons->dataAvailable()) {
+                    DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
+                    rxIntrEvent.scheduleIntr();
+                } else {
+                    DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
+                    if (rxIntrEvent.scheduled())
+                        rxIntrEvent.deschedule();
+                    if (status & RX_INT)
+                        platform->clearConsoleInt();
+                    status &= ~RX_INT;
+                }
+             } else { // DLM divisor latch MSB
+                ;
+            }
+            break;
+        case 0x2: // FIFO Control Register (FCR)
+            break;
+        case 0x3: // Line Control Register (LCR)
+            LCR = *(uint8_t*)data;
+            break;
+        case 0x4: // Modem Control Register (MCR)
+            if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
+                    MCR = 0x9A;
+            break;
+        case 0x7: // Scratch Register (SCR)
+            // We are emulating a 8250 so we don't have a scratch reg
+            break;
+        default:
+            panic("Tried to access a UART port that doesn't exist\n");
+            break;
+    }
+    return No_Fault;
+}
+
+void
+Uart8250::dataAvailable()
+{
+    // if the kernel wants an interrupt when we have data
+    if (IER & UART_IER_RDI)
+    {
+        platform->postConsoleInt();
+        status |= RX_INT;
+    }
+
+}
+
+
+
+void
+Uart8250::serialize(ostream &os)
+{
+    SERIALIZE_SCALAR(status);
+    SERIALIZE_SCALAR(IER);
+    SERIALIZE_SCALAR(DLAB);
+    SERIALIZE_SCALAR(LCR);
+    SERIALIZE_SCALAR(MCR);
+    Tick rxintrwhen;
+    if (rxIntrEvent.scheduled())
+        rxintrwhen = rxIntrEvent.when();
+    else
+        rxintrwhen = 0;
+    Tick txintrwhen;
+    if (txIntrEvent.scheduled())
+        txintrwhen = txIntrEvent.when();
+    else
+        txintrwhen = 0;
+     SERIALIZE_SCALAR(rxintrwhen);
+     SERIALIZE_SCALAR(txintrwhen);
+}
+
+void
+Uart8250::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_SCALAR(status);
+    UNSERIALIZE_SCALAR(IER);
+    UNSERIALIZE_SCALAR(DLAB);
+    UNSERIALIZE_SCALAR(LCR);
+    UNSERIALIZE_SCALAR(MCR);
+    Tick rxintrwhen;
+    Tick txintrwhen;
+    UNSERIALIZE_SCALAR(rxintrwhen);
+    UNSERIALIZE_SCALAR(txintrwhen);
+    if (rxintrwhen != 0)
+        rxIntrEvent.schedule(rxintrwhen);
+    if (txintrwhen != 0)
+        txIntrEvent.schedule(txintrwhen);
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
+
+    SimObjectParam<SimConsole *> console;
+    SimObjectParam<MemoryController *> mmu;
+    SimObjectParam<Platform *> platform;
+    Param<Addr> addr;
+    Param<Addr> size;
+    SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
+    SimObjectParam<HierParams *> hier;
+
+
+END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
+
+    INIT_PARAM(console, "The console"),
+    INIT_PARAM(mmu, "Memory Controller"),
+    INIT_PARAM(platform, "Pointer to platfrom"),
+    INIT_PARAM(addr, "Device Address"),
+    INIT_PARAM_DFLT(size, "Device size", 0x8),
+    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
+
+END_INIT_SIM_OBJECT_PARAMS(Uart8250)
+
+CREATE_SIM_OBJECT(Uart8250)
+{
+    return new Uart8250(getInstanceName(), console, mmu, addr, size, hier, io_bus,
+                    pio_latency, platform);
+}
+
+REGISTER_SIM_OBJECT("Uart8250", Uart8250)
diff --git a/dev/uart8250.hh b/dev/uart8250.hh
new file mode 100644
index 000000000..046388fb5
--- /dev/null
+++ b/dev/uart8250.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @file
+ * Defines a 8250 UART
+ */
+
+#ifndef __TSUNAMI_UART_HH__
+#define __TSUNAMI_UART_HH__
+
+#include "dev/tsunamireg.h"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+#include "dev/uart.hh"
+
+class SimConsole;
+class Platform;
+
+class Uart8250 : public Uart
+{
+
+
+  protected:
+    uint8_t IER, DLAB, LCR, MCR;
+
+    class IntrEvent : public Event
+    {
+        protected:
+            Uart8250 *uart;
+            int intrBit;
+        public:
+            IntrEvent(Uart8250 *u, int bit);
+            virtual void process();
+            virtual const char *description();
+            void scheduleIntr();
+    };
+
+    IntrEvent txIntrEvent;
+    IntrEvent rxIntrEvent;
+
+  public:
+    Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
+         Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
+         Platform *p);
+
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+
+
+    /**
+     * Inform the uart that there is data available.
+     */
+    virtual void dataAvailable();
+
+
+    /**
+     * Return if we have an interrupt pending
+     * @return interrupt status
+     */
+    virtual bool intStatus() { return status ? true : false; }
+
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+};
+
+#endif // __TSUNAMI_UART_HH__
diff --git a/cpu/full_cpu/op_class.hh b/encumbered/cpu/full/op_class.hh
index 8e85e8d8a..19b948651 100644
--- a/cpu/full_cpu/op_class.hh
+++ b/encumbered/cpu/full/op_class.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __OP_CLASS_HH__
-#define __OP_CLASS_HH__
+#ifndef __ENCUMBERED_CPU_FULL_OP_CLASS_HH__
+#define __ENCUMBERED_CPU_FULL_OP_CLASS_HH__
 
 /**
  * @file
@@ -61,4 +61,4 @@ enum OpClass {
  */
 extern const char *opClassStrings[];
 
-#endif // __OP_CLASS_HH__
+#endif // __ENCUMBERED_CPU_FULL_OP_CLASS_HH__
diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc
index 5fa72735c..afc9f1d93 100644
--- a/kern/linux/linux_system.cc
+++ b/kern/linux/linux_system.cc
@@ -38,12 +38,12 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "kern/linux/linux_events.hh"
 #include "kern/linux/linux_system.hh"
 #include "kern/system_events.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "dev/platform.hh"
 #include "targetarch/isa_traits.hh"
diff --git a/kern/system_events.cc b/kern/system_events.cc
index 9acf2f65a..eb21afcd1 100644
--- a/kern/system_events.cc
+++ b/kern/system_events.cc
@@ -27,9 +27,9 @@
  */
 
 #include "cpu/exec_context.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/full_cpu/bpred.hh"
-#include "cpu/full_cpu/full_cpu.hh"
+#include "cpu/base.hh"
+#include "encumbered/cpu/full/bpred.hh"
+#include "encumbered/cpu/full/cpu.hh"
 #include "kern/kernel_stats.hh"
 #include "kern/system_events.hh"
 #include "sim/system.hh"
diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc
index f4300116e..247b58558 100644
--- a/kern/tru64/tru64_events.cc
+++ b/kern/tru64/tru64_events.cc
@@ -27,12 +27,12 @@
  */
 
 #include "cpu/exec_context.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "kern/system_events.hh"
 #include "kern/tru64/tru64_events.hh"
 #include "kern/tru64/dump_mbuf.hh"
 #include "kern/tru64/printf.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/functional/memory_control.hh"
 #include "targetarch/arguments.hh"
 #include "targetarch/isa_traits.hh"
 
diff --git a/kern/tru64/tru64_system.cc b/kern/tru64/tru64_system.cc
index e0ec31a43..6914a9c54 100644
--- a/kern/tru64/tru64_system.cc
+++ b/kern/tru64/tru64_system.cc
@@ -28,13 +28,13 @@
 
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "kern/tru64/tru64_events.hh"
 #include "kern/tru64/tru64_system.hh"
 #include "kern/system_events.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/builder.hh"
 #include "targetarch/isa_traits.hh"
 #include "targetarch/vtophys.hh"
diff --git a/python/m5/__init__.py b/python/m5/__init__.py
index 5a3c69caa..cf4ba9a54 100644
--- a/python/m5/__init__.py
+++ b/python/m5/__init__.py
@@ -1,3 +1,29 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
 import sys, os
 
 # define this here so we can use it right away if necessary
diff --git a/python/m5/convert.py b/python/m5/convert.py
index a89303687..2551459bd 100644
--- a/python/m5/convert.py
+++ b/python/m5/convert.py
@@ -1,3 +1,29 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
 # metric prefixes
 exa  = 1.0e18
 peta = 1.0e15
diff --git a/python/m5/multidict.py b/python/m5/multidict.py
index d0c27fa8e..fd40ebbbd 100644
--- a/python/m5/multidict.py
+++ b/python/m5/multidict.py
@@ -1,3 +1,29 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
 __all__ = [ 'multidict' ]
 
 class multidict(object):
diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py
index cfb09acad..57b8b44af 100644
--- a/python/m5/objects/Uart.py
+++ b/python/m5/objects/Uart.py
@@ -3,5 +3,13 @@ from Device import PioDevice
 
 class Uart(PioDevice):
     type = 'Uart'
+    abstract = True
     console = Param.SimConsole(Parent.any, "The console")
     size = Param.Addr(0x8, "Device size")
+
+class Uart8250(Uart):
+    type = 'Uart8250'
+
+class Uart8530(Uart):
+    type = 'Uart8530'
+
diff --git a/python/m5/smartdict.py b/python/m5/smartdict.py
index a2661c279..cd38d7326 100644
--- a/python/m5/smartdict.py
+++ b/python/m5/smartdict.py
@@ -1,3 +1,29 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
 # The SmartDict class fixes a couple of issues with using the content
 # of os.environ or similar dicts of strings as Python variables:
 #
diff --git a/sim/eventq.cc b/sim/eventq.cc
index 50158d06f..1fb8ef98a 100644
--- a/sim/eventq.cc
+++ b/sim/eventq.cc
@@ -33,7 +33,7 @@
 #include <sstream>
 #include <vector>
 
-#include "cpu/full_cpu/smt.hh"
+#include "cpu/smt.hh"
 #include "base/misc.hh"
 
 #include "sim/eventq.hh"
diff --git a/sim/main.cc b/sim/main.cc
index b28cac15b..a6d996d50 100644
--- a/sim/main.cc
+++ b/sim/main.cc
@@ -49,8 +49,8 @@
 #include "base/statistics.hh"
 #include "base/str.hh"
 #include "base/time.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/full_cpu/smt.hh"
+#include "cpu/base.hh"
+#include "cpu/smt.hh"
 #include "python/pyconfig.hh"
 #include "sim/async.hh"
 #include "sim/builder.hh"
diff --git a/sim/process.cc b/sim/process.cc
index 3541fd040..e7a9afa9d 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -37,10 +37,10 @@
 #include "base/loader/symtab.hh"
 #include "base/statistics.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/full_cpu/smt.hh"
-#include "cpu/full_cpu/thread.hh"
+#include "cpu/smt.hh"
 #include "eio/eio.hh"
-#include "mem/functional_mem/main_memory.hh"
+#include "encumbered/cpu/full/thread.hh"
+#include "encumbered/mem/functional/main.hh"
 #include "sim/builder.hh"
 #include "sim/fake_syscall.hh"
 #include "sim/process.hh"
diff --git a/sim/stat_control.cc b/sim/stat_control.cc
index 37664dc65..578073efa 100644
--- a/sim/stat_control.cc
+++ b/sim/stat_control.cc
@@ -39,7 +39,7 @@
 #include "base/str.hh"
 #include "base/time.hh"
 #include "base/stats/output.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "sim/stat_control.hh"
diff --git a/sim/syscall_emul.cc b/sim/syscall_emul.cc
index 13df2b7a2..5abbdfd74 100644
--- a/sim/syscall_emul.cc
+++ b/sim/syscall_emul.cc
@@ -34,7 +34,7 @@
 #include "sim/syscall_emul.hh"
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "sim/process.hh"
 
 #include "sim/sim_events.hh"
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 26d3b873c..417531cc3 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -39,7 +39,7 @@
 #include <string>
 
 #include "base/intmath.hh"	// for RoundUp
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "targetarch/isa_traits.hh"	// for Addr
 
 #include "base/trace.hh"
diff --git a/sim/system.cc b/sim/system.cc
index 8844f13de..70a1b8a32 100644
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -31,8 +31,8 @@
 #include "base/remote_gdb.hh"
 #include "cpu/exec_context.hh"
 #include "kern/kernel_stats.hh"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "targetarch/vtophys.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"