diff options
| -rw-r--r-- | src/cpu/inorder/resource.cc | 6 | ||||
| -rw-r--r-- | src/cpu/inorder/resource.hh | 2 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 5 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/use_def.cc | 13 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/use_def.hh | 2 |
5 files changed, 28 insertions, 0 deletions
diff --git a/src/cpu/inorder/resource.cc b/src/cpu/inorder/resource.cc index 72b45dda8..5a31125c6 100644 --- a/src/cpu/inorder/resource.cc +++ b/src/cpu/inorder/resource.cc @@ -40,6 +40,8 @@ Resource::Resource(string res_name, int res_id, int res_width, : resName(res_name), id(res_id), width(res_width), latency(res_latency), cpu(_cpu) { + reqs.resize(width); + // Use to deny a instruction a resource. deniedReq = new ResourceRequest(this, NULL, 0, 0, 0, 0); } @@ -57,6 +59,10 @@ Resource::init() // Set Up Resource Events to Appropriate Resource BandWidth resourceEvent = new ResourceEvent[width]; + for (int i = 0; i < width; i++) { + reqs[i] = new ResourceRequest(this, NULL, 0, 0, 0, 0); + } + initSlots(); } diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh index bd9ec48ca..7f6cb6642 100644 --- a/src/cpu/inorder/resource.hh +++ b/src/cpu/inorder/resource.hh @@ -224,6 +224,8 @@ class Resource { /** Mapping of slot-numbers to the resource-request pointers */ std::map<int, ResReqPtr> reqMap; + std::vector<ResReqPtr> reqs; + /** A list of all the available execution slots for this resource. * This correlates with the actual resource event idx. */ diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 8cd105493..47fafe45a 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -133,6 +133,11 @@ CacheUnit::getPort(const string &if_name, int idx) void CacheUnit::init() { + for (int i = 0; i < width; i++) { + reqs[i] = new CacheRequest(this, NULL, 0, 0, 0, 0, 0, + MemCmd::Command(0), 0, 0, 0); + } + // Currently Used to Model TLB Latency. Eventually // Switch to Timing TLB translations. resourceEvent = new CacheUnitEvent[width]; diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index 538b20246..dd178403b 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -88,6 +88,19 @@ UseDefUnit::regStats() Resource::regStats(); } +void +UseDefUnit::init() +{ + // Set Up Resource Events to Appropriate Resource BandWidth + resourceEvent = new ResourceEvent[width]; + + for (int i = 0; i < width; i++) { + reqs[i] = new UseDefRequest(this, NULL, 0, 0, 0, 0, 0); + } + + initSlots(); +} + ResReqPtr UseDefUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, unsigned cmd) diff --git a/src/cpu/inorder/resources/use_def.hh b/src/cpu/inorder/resources/use_def.hh index d2cc55315..6db8ed987 100644 --- a/src/cpu/inorder/resources/use_def.hh +++ b/src/cpu/inorder/resources/use_def.hh @@ -56,6 +56,8 @@ class UseDefUnit : public Resource { UseDefUnit(std::string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params); + void init(); + ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, int res_idx, int slot_num, unsigned cmd); |