diff options
| -rw-r--r-- | src/arch/x86/isa/insts/rotate_and_shift/shift.py | 92 |
1 files changed, 69 insertions, 23 deletions
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py index b9c07b0ba..64eab3edc 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py +++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py @@ -74,15 +74,35 @@ def macroop SAL_P_I st t1, ds, [0, t0, t7], disp }; +def macroop SAL_1_R +{ + slli reg, reg, 1 +}; + +def macroop SAL_1_M +{ + ld t1, ds, [scale, index, base], disp + slli t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop SAL_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + slli t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop SAL_R_R { - slli reg, reg, regm + sll reg, reg, regm }; def macroop SAL_M_R { ld t1, ds, [scale, index, base], disp - slli t1, t1, reg + sll t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -90,7 +110,7 @@ def macroop SAL_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - slli t1, t1, reg + sll t1, t1, reg st t1, ds, [0, t0, t7], disp }; @@ -114,15 +134,35 @@ def macroop SHR_P_I st t1, ds, [0, t0, t7], disp }; +def macroop SHR_1_R +{ + srli reg, reg, 1 +}; + +def macroop SHR_1_M +{ + ld t1, ds, [scale, index, base], disp + srli t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop SHR_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + srli t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop SHR_R_R { - srli reg, reg, regm + srl reg, reg, regm }; def macroop SHR_M_R { ld t1, ds, [scale, index, base], disp - srli t1, t1, reg + srl t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -130,7 +170,7 @@ def macroop SHR_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - srli t1, t1, reg + srl t1, t1, reg st t1, ds, [0, t0, t7], disp }; @@ -154,15 +194,35 @@ def macroop SAR_P_I st t1, ds, [0, t0, t7], disp }; +def macroop SAR_1_R +{ + srai reg, reg, 1 +}; + +def macroop SAR_1_M +{ + ld t1, ds, [scale, index, base], disp + srai t1, t1, 1 + st t1, ds, [scale, index, base], disp +}; + +def macroop SAR_1_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + srai t1, t1, 1 + st t1, ds, [0, t0, t7], disp +}; + def macroop SAR_R_R { - srai reg, reg, regm + sra reg, reg, regm }; def macroop SAR_M_R { ld t1, ds, [scale, index, base], disp - srai t1, t1, reg + sra t1, t1, reg st t1, ds, [scale, index, base], disp }; @@ -170,21 +230,7 @@ def macroop SAR_P_R { rdip t7 ld t1, ds, [0, t0, t7], disp - srai t1, t1, reg + sra t1, t1, reg st t1, ds, [0, t0, t7], disp }; ''' -#let {{ -# class SAL(Inst): -# "GenFault ${new UnimpInstFault}" -# class SAR(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHL(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHR(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHLD(Inst): -# "GenFault ${new UnimpInstFault}" -# class SHRD(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; |