summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--SConscript1
-rw-r--r--arch/alpha/tlb.cc109
-rw-r--r--arch/alpha/tlb.hh6
-rw-r--r--arch/mips/isa/bitfields.isa1
-rw-r--r--arch/mips/isa/decoder.isa379
-rw-r--r--arch/mips/isa/formats/branch.isa2
-rw-r--r--arch/mips/isa/formats/int.isa16
-rw-r--r--arch/mips/isa/formats/mem.isa8
-rw-r--r--arch/mips/isa/formats/unimp.isa3
-rw-r--r--arch/mips/isa/formats/unknown.isa28
-rw-r--r--arch/mips/isa/operands.isa2
-rw-r--r--arch/mips/isa_traits.hh20
-rw-r--r--arch/mips/linux_process.cc28
-rw-r--r--cpu/cpu_exec_context.hh18
-rw-r--r--cpu/exec_context.hh12
-rw-r--r--cpu/simple/cpu.cc48
-rw-r--r--cpu/simple/cpu.hh12
-rw-r--r--cpu/static_inst.hh5
-rw-r--r--dev/io_device.cc14
-rw-r--r--mem/page_table.cc11
-rw-r--r--mem/page_table.hh2
-rw-r--r--mem/port.cc6
-rw-r--r--mem/request.hh106
-rw-r--r--sim/syscall_emul.cc12
24 files changed, 628 insertions, 221 deletions
diff --git a/SConscript b/SConscript
index 9c4ce2e72..3693435b6 100644
--- a/SConscript
+++ b/SConscript
@@ -88,6 +88,7 @@ base_sources = Split('''
cpu/static_inst.cc
cpu/sampler/sampler.cc
+ mem/request.cc
mem/connector.cc
mem/mem_object.cc
mem/physical.cc
diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index a1a7c9366..877822c31 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -94,7 +94,7 @@ AlphaTLB::lookup(Addr vpn, uint8_t asn) const
Fault
-AlphaTLB::checkCacheability(CpuRequestPtr &req)
+AlphaTLB::checkCacheability(RequestPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
@@ -109,20 +109,20 @@ AlphaTLB::checkCacheability(CpuRequestPtr &req)
#if ALPHA_TLASER
- if (req->paddr & PAddrUncachedBit39) {
+ if (req->getPaddr() & PAddrUncachedBit39) {
#else
- if (req->paddr & PAddrUncachedBit43) {
+ if (req->getPaddr() & PAddrUncachedBit43) {
#endif
// IPR memory space not implemented
- if (PAddrIprSpace(req->paddr)) {
+ if (PAddrIprSpace(req->getPaddr())) {
return new UnimpFault("IPR memory space not implemented!");
} else {
// mark request as uncacheable
- req->flags |= UNCACHEABLE;
+ req->setFlags(req->getFlags() | UNCACHEABLE);
#if !ALPHA_TLASER
// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
- req->paddr &= PAddrUncachedMask;
+ req->setPaddr(req->getPaddr() & PAddrUncachedMask);
#endif
}
}
@@ -283,22 +283,22 @@ AlphaITB::regStats()
Fault
-AlphaITB::translate(CpuRequestPtr &req, ExecContext *xc) const
+AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
{
- if (AlphaISA::PcPAL(req->vaddr)) {
+ if (AlphaISA::PcPAL(req->getVaddr())) {
// strip off PAL PC marker (lsb is 1)
- req->paddr = (req->vaddr & ~3) & PAddrImplMask;
+ req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
hits++;
return NoFault;
}
- if (req->flags & PHYSICAL) {
- req->paddr = req->vaddr;
+ if (req->getFlags() & PHYSICAL) {
+ req->setPaddr(req->getVaddr());
} else {
// verify that this is a good virtual address
- if (!validVirtualAddress(req->vaddr)) {
+ if (!validVirtualAddress(req->getVaddr())) {
acv++;
- return new ItbAcvFault(req->vaddr);
+ return new ItbAcvFault(req->getVaddr());
}
@@ -306,47 +306,48 @@ AlphaITB::translate(CpuRequestPtr &req, ExecContext *xc) const
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->vaddr) == 2) {
+ VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
- if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
// only valid in kernel mode
if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
AlphaISA::mode_kernel) {
acv++;
- return new ItbAcvFault(req->vaddr);
+ return new ItbAcvFault(req->getVaddr());
}
- req->paddr = req->vaddr & PAddrImplMask;
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
#if !ALPHA_TLASER
// sign extend the physical address properly
- if (req->paddr & PAddrUncachedBit40)
- req->paddr |= ULL(0xf0000000000);
+ if (req->getPaddr() & PAddrUncachedBit40)
+ req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
else
- req->paddr &= ULL(0xffffffffff);
+ req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
#endif
} else {
// not a physical address: need to look up pte
int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
- AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
+ AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
asn);
if (!pte) {
misses++;
- return new ItbPageFault(req->vaddr);
+ return new ItbPageFault(req->getVaddr());
}
- req->paddr = (pte->ppn << AlphaISA::PageShift) +
- (AlphaISA::VAddr(req->vaddr).offset() & ~3);
+ req->setPaddr((pte->ppn << AlphaISA::PageShift) +
+ (AlphaISA::VAddr(req->getVaddr()).offset()
+ & ~3));
// check permissions for this access
if (!(pte->xre &
(1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
// instruction access fault
acv++;
- return new ItbAcvFault(req->vaddr);
+ return new ItbAcvFault(req->getVaddr());
}
hits++;
@@ -354,7 +355,7 @@ AlphaITB::translate(CpuRequestPtr &req, ExecContext *xc) const
}
// check that the physical address is ok (catch bad physical addresses)
- if (req->paddr & ~PAddrImplMask)
+ if (req->getPaddr() & ~PAddrImplMask)
return genMachineCheckFault();
return checkCacheability(req);
@@ -439,7 +440,7 @@ AlphaDTB::regStats()
}
Fault
-AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
+AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
{
Addr pc = xc->readPC();
@@ -450,38 +451,38 @@ AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
/**
* Check for alignment faults
*/
- if (req->vaddr & (req->size - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
- req->size);
+ if (req->getVaddr() & (req->getSize() - 1)) {
+ DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
+ req->getSize());
uint64_t flags = write ? MM_STAT_WR_MASK : 0;
- return new DtbAlignmentFault(req->vaddr, req->flags, flags);
+ return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
}
if (pc & 0x1) {
- mode = (req->flags & ALTMODE) ?
+ mode = (req->getFlags() & ALTMODE) ?
(AlphaISA::mode_type)ALT_MODE_AM(
xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
: AlphaISA::mode_kernel;
}
- if (req->flags & PHYSICAL) {
- req->paddr = req->vaddr;
+ if (req->getFlags() & PHYSICAL) {
+ req->setPaddr(req->getVaddr());
} else {
// verify that this is a good virtual address
- if (!validVirtualAddress(req->vaddr)) {
+ if (!validVirtualAddress(req->getVaddr())) {
if (write) { write_acv++; } else { read_acv++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_BAD_VA_MASK |
MM_STAT_ACV_MASK;
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
// Check for "superpage" mapping
#if ALPHA_TLASER
if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->vaddr) == 2) {
+ VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
- if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
// only valid in kernel mode
@@ -490,17 +491,17 @@ AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
if (write) { write_acv++; } else { read_acv++; }
uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
MM_STAT_ACV_MASK);
- return new DtbAcvFault(req->vaddr, req->flags, flags);
+ return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
}
- req->paddr = req->vaddr & PAddrImplMask;
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
#if !ALPHA_TLASER
// sign extend the physical address properly
- if (req->paddr & PAddrUncachedBit40)
- req->paddr |= ULL(0xf0000000000);
+ if (req->getPaddr() & PAddrUncachedBit40)
+ req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
else
- req->paddr &= ULL(0xffffffffff);
+ req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
#endif
} else {
@@ -512,7 +513,7 @@ AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
// not a physical address: need to look up pte
- AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
+ AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
asn);
if (!pte) {
@@ -520,15 +521,15 @@ AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
if (write) { write_misses++; } else { read_misses++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK;
- return (req->flags & VPTE) ?
- (Fault)(new PDtbMissFault(req->vaddr, req->flags,
+ return (req->getFlags() & VPTE) ?
+ (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
flags)) :
- (Fault)(new NDtbMissFault(req->vaddr, req->flags,
+ (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
flags));
}
- req->paddr = (pte->ppn << AlphaISA::PageShift) +
- AlphaISA::VAddr(req->vaddr).offset();
+ req->setPaddr((pte->ppn << AlphaISA::PageShift) +
+ AlphaISA::VAddr(req->getVaddr()).offset());
if (write) {
if (!(pte->xwe & MODE2MASK(mode))) {
@@ -537,25 +538,25 @@ AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
uint64_t flags = MM_STAT_WR_MASK |
MM_STAT_ACV_MASK |
(pte->fonw ? MM_STAT_FONW_MASK : 0);
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
if (pte->fonw) {
write_acv++;
uint64_t flags = MM_STAT_WR_MASK |
MM_STAT_FONW_MASK;
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
read_acv++;
uint64_t flags = MM_STAT_ACV_MASK |
(pte->fonr ? MM_STAT_FONR_MASK : 0);
- return new DtbAcvFault(req->vaddr, req->flags, flags);
+ return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
}
if (pte->fonr) {
read_acv++;
uint64_t flags = MM_STAT_FONR_MASK;
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
}
}
@@ -567,7 +568,7 @@ AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
}
// check that the physical address is ok (catch bad physical addresses)
- if (req->paddr & ~PAddrImplMask)
+ if (req->getPaddr() & ~PAddrImplMask)
return genMachineCheckFault();
return checkCacheability(req);
diff --git a/arch/alpha/tlb.hh b/arch/alpha/tlb.hh
index 39faffbee..f6256020e 100644
--- a/arch/alpha/tlb.hh
+++ b/arch/alpha/tlb.hh
@@ -73,7 +73,7 @@ class AlphaTLB : public SimObject
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
}
- static Fault checkCacheability(CpuRequestPtr &req);
+ static Fault checkCacheability(RequestPtr &req);
// Checkpointing
virtual void serialize(std::ostream &os);
@@ -92,7 +92,7 @@ class AlphaITB : public AlphaTLB
AlphaITB(const std::string &name, int size);
virtual void regStats();
- Fault translate(CpuRequestPtr &req, ExecContext *xc) const;
+ Fault translate(RequestPtr &req, ExecContext *xc) const;
};
class AlphaDTB : public AlphaTLB
@@ -115,7 +115,7 @@ class AlphaDTB : public AlphaTLB
AlphaDTB(const std::string &name, int size);
virtual void regStats();
- Fault translate(CpuRequestPtr &req, ExecContext *xc, bool write) const;
+ Fault translate(RequestPtr &req, ExecContext *xc, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__
diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa
index 58d487ad2..eb917595c 100644
--- a/arch/mips/isa/bitfields.isa
+++ b/arch/mips/isa/bitfields.isa
@@ -26,6 +26,7 @@ def bitfield RS <25:21>;
def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
+def bitfield RS_SRL <25:22>;
def bitfield RD <15:11>;
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index f5dd3d911..35e5fa75b 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -43,14 +43,30 @@ decode OPCODE_HI default Unknown::unknown() {
}
- 0x2: decode SRL {
- 0: srl({{ Rd = Rt.uw >> SA; }});
+ 0x2: decode RS_SRL {
+ 0x0:decode SRL {
+ 0: srl({{ Rd = Rt.uw >> SA; }});
- //Hardcoded assuming 32-bit ISA, probably need parameter here
- 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
+ //Hardcoded assuming 32-bit ISA, probably need parameter here
+ 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
+ }
}
- 0x3: sra({{ Rd = Rt.sw >> SA; }});
+ 0x3: decode RS {
+ 0x0: sra({{
+ uint32_t temp = Rt >> SA;
+
+ if ( (Rt & 0x80000000) > 0 ) {
+ uint32_t mask = 0x80000000;
+ for(int i=0; i < SA; i++) {
+ temp |= mask;
+ mask = mask >> 1;
+ }
+ }
+
+ Rd = temp;
+ }});
+ }
0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
@@ -61,7 +77,21 @@ decode OPCODE_HI default Unknown::unknown() {
1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
}
- 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
+ 0x7: srav({{
+ int shift_amt = Rs<4:0>;
+
+ uint32_t temp = Rt >> shift_amt;
+
+ if ( (Rt & 0x80000000) > 0 ) {
+ uint32_t mask = 0x80000000;
+ for(int i=0; i < shift_amt; i++) {
+ temp |= mask;
+ mask = mask >> 1;
+ }
+ }
+
+ Rd = temp;
+ }});
}
}
@@ -130,23 +160,27 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
- 0x4: decode FUNCTION_LO {
- format IntOp {
- 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
- 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
- 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
- 0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}});
- 0x4: and({{ Rd = Rs & Rt;}});
- 0x5: or({{ Rd = Rs | Rt;}});
- 0x6: xor({{ Rd = Rs ^ Rt;}});
- 0x7: nor({{ Rd = ~(Rs | Rt);}});
+ 0x4: decode HINT {
+ 0x0: decode FUNCTION_LO {
+ format IntOp {
+ 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
+ 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
+ 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
+ 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
+ 0x4: and({{ Rd = Rs & Rt;}});
+ 0x5: or({{ Rd = Rs | Rt;}});
+ 0x6: xor({{ Rd = Rs ^ Rt;}});
+ 0x7: nor({{ Rd = ~(Rs | Rt);}});
+ }
}
}
- 0x5: decode FUNCTION_LO {
- format IntOp{
- 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
- 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+ 0x5: decode HINT {
+ 0x0: decode FUNCTION_LO {
+ format IntOp{
+ 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
+ 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+ }
}
}
@@ -216,8 +250,13 @@ decode OPCODE_HI default Unknown::unknown() {
format Branch {
0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
- 0x6: blez({{ cond = (Rs.sw <= 0); }});
- 0x7: bgtz({{ cond = (Rs.sw > 0); }});
+ 0x6: decode RT {
+ 0x0: blez({{ cond = (Rs.sw <= 0); }});
+ }
+
+ 0x7: decode RT {
+ 0x0: bgtz({{ cond = (Rs.sw > 0); }});
+ }
}
}
@@ -226,11 +265,14 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
- 0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }});
- 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
- 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
- 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
- 0x7: lui({{ Rt = INTIMM << 16}});
+ 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
+ 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
+ 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
+ 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
+
+ 0x7: decode RS {
+ 0x0: lui({{ Rt = imm << 16}});
+ }
}
}
@@ -352,13 +394,37 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode RS_HI {
0x0: decode RS_LO {
- format FloatOp {
- 0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }});
- 0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}});
- 0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}});
- 0x4: mtc1({{ /*Fs = Rt.uw*/}});
- 0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}});
- 0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}});
+ format WarnUnimpl {
+ 0x0: mfc1();//{{ /*Rt.uw = Fs.ud<31:0>;*/ }}
+ 0x3: mfhc1();// /*Rt.uw = Fs.ud<63:32>*/;
+ 0x4: mtc1();// /*Fs = Rt.uw*/
+ 0x7: mthc1();//{{/*Fs<63:32> = Rt.uw*/}}
+ }
+
+ format System {
+ 0x2: cfc1({{
+ uint32_t fcsr_reg = xc->readMiscReg(FCSR);
+
+ if (Fs == 0){
+ Rt = xc->readMiscReg(FIR);
+ } else if (Fs == 25) {
+ Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23;
+ } else if (Fs == 26) {
+ Rt = 0 | (fcsr_reg & 0x0003F07C);
+ } else if (Fs == 28) {
+ Rt = 0 | (fcsr_reg);
+ } else if (Fs == 31) {
+ Rt = fcsr_reg;
+ } else {
+ panic("FP Control Value (%d) Not Available. Ignoring Access to"
+ "Floating Control Status Register",fcsr_reg);
+ }
+
+ }});
+
+ 0x6: ctc1({{
+ /*xc->setMiscReg(FPCR[Fs],Rt);*/
+ }});
}
}
@@ -830,14 +896,14 @@ decode OPCODE_HI default Unknown::unknown() {
0x7: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
- format WarnUnimpl {
+ format FailUnimpl {
0x1: ext();
0x4: ins();
}
}
0x1: decode FUNCTION_LO {
- format WarnUnimpl {
+ format FailUnimpl {
0x0: fork();
0x1: yield();
}
@@ -847,16 +913,16 @@ decode OPCODE_HI default Unknown::unknown() {
//Table A-10 MIPS32 BSHFL Encoding of sa Field
0x4: decode SA {
- 0x02: WarnUnimpl::wsbh();
+ 0x02: FailUnimpl::wsbh();
format BasicOp {
- 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
- 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
+ 0x10: seb({{ Rd.sw = Rt<7:0>}});
+ 0x18: seh({{ Rd.sw = Rt<15:0>}});
}
}
0x6: decode FUNCTION_LO {
- 0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }});
+ 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }}
}
}
}
@@ -865,11 +931,97 @@ decode OPCODE_HI default Unknown::unknown() {
format LoadMemory {
0x0: lb({{ Rt.sw = Mem.sb; }});
0x1: lh({{ Rt.sw = Mem.sh; }});
- 0x2: lwl({{ uint32_t temp = Mem.uw<31:16> << 16; Rt.uw &= 0x00FF; Rt.uw |= temp;}}, {{ EA = (Rs + disp) & ~3; }});
+
+ 0x2: lwl({{
+ uint32_t mem_word = Mem.uw;
+ uint32_t unalign_addr = Rs + disp;
+ uint32_t offset = unalign_addr & 0x00000003;
+#if BYTE_ORDER == BIG_ENDIAN
+ std::cout << "Big Endian Byte Order\n";
+
+ switch(offset)
+ {
+ case 0:
+ Rt = mem_word;
+ break;
+
+ case 1:
+ Rt &= 0x000F;
+ Rt |= (mem_word << 4);
+ break;
+
+ case 2:
+ Rt &= 0x00FF;
+ Rt |= (mem_word << 8);
+ break;
+
+ case 3:
+ Rt &= 0x0FFF;
+ Rt |= (mem_word << 12);
+ break;
+
+ default:
+ panic("lwl: bad offset");
+ }
+#elif BYTE_ORDER == LITTLE_ENDIAN
+ std::cout << "Little Endian Byte Order\n";
+
+ switch(offset)
+ {
+ case 0:
+ Rt &= 0x0FFF;
+ Rt |= (mem_word << 12);
+ break;
+
+ case 1:
+ Rt &= 0x00FF;
+ Rt |= (mem_word << 8);
+ break;
+
+ case 2:
+ Rt &= 0x000F;
+ Rt |= (mem_word << 4);
+ break;
+
+ case 3:
+ Rt = mem_word;
+ break;
+
+ default:
+ panic("lwl: bad offset");
+ }
+#endif
+ }}, {{ EA = (Rs + disp) & ~3; }});
+
0x3: lw({{ Rt.sw = Mem.sw; }});
0x4: lbu({{ Rt.uw = Mem.ub; }});
0x5: lhu({{ Rt.uw = Mem.uh; }});
- 0x6: lwr({{ uint32_t temp = 0x00FF & Mem.uw<15:0>; Rt.uw &= 0xFF00; Rt.uw |= temp; }}, {{ EA = (Rs + disp) & ~3; }});
+ 0x6: lwr({{
+ uint32_t mem_word = Mem.uw;
+ uint32_t unalign_addr = Rs + disp;
+ uint32_t offset = unalign_addr & 0x00000003;
+
+#if BYTE_ORDER == BIG_ENDIAN
+ switch(offset)
+ {
+ case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break;
+ case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break;
+ case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break;
+ case 3: Rt = mem_word; break;
+ default: panic("lwr: bad offset");
+ }
+#elif BYTE_ORDER == LITTLE_ENDIAN
+ switch(offset)
+ {
+ case 0: Rt = mem_word; break;
+ case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break;
+ case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break;
+ case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break;
+ default: panic("lwr: bad offset");
+ }
+#endif
+ }},
+ {{ EA = (Rs + disp) & ~3; }});
}
0x7: FailUnimpl::reserved();
@@ -879,9 +1031,144 @@ decode OPCODE_HI default Unknown::unknown() {
format StoreMemory {
0x0: sb({{ Mem.ub = Rt<7:0>; }});
0x1: sh({{ Mem.uh = Rt<15:0>; }});
- 0x2: swl({{ Mem.uh = Rt<31:16>; }}, {{ EA = (Rs + disp) & ~3; }});
+ 0x2: swl({{
+ uint32_t mem_word = 0;
+ uint32_t aligned_addr = (Rs + disp) & ~3;
+ uint32_t unalign_addr = Rs + disp;
+ uint32_t offset = unalign_addr & 0x00000003;
+
+ DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x",
+ aligned_addr,unalign_addr,offset);
+
+ fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
+
+#if BYTE_ORDER == BIG_ENDIAN
+ switch(offset)
+ {
+ case 0:
+ Mem = Rt;
+ break;
+
+ case 1:
+ mem_word &= 0xF000;
+ mem_word |= (Rt >> 4);
+ Mem = mem_word;
+ break;
+
+ case 2:
+ mem_word &= 0xFF00;
+ mem_word |= (Rt >> 8);
+ Mem = mem_word;
+ break;
+
+ case 3:
+ mem_word &= 0xFFF0;
+ mem_word |= (Rt >> 12);
+ Mem = mem_word;
+ break;
+
+ default:
+ panic("swl: bad offset");
+ }
+#elif BYTE_ORDER == LITTLE_ENDIAN
+ switch(offset)
+ {
+ case 0:
+ mem_word &= 0xFFF0;
+ mem_word |= (Rt >> 12);
+ Mem = mem_word;
+ break;
+
+ case 1:
+ mem_word &= 0xFF00;
+ mem_word |= (Rt >> 8);
+ Mem = mem_word;
+ break;
+
+ case 2:
+ mem_word &= 0xF000;
+ mem_word |= (Rt >> 4);
+ Mem = mem_word;
+ break;
+
+ case 3:
+ Mem = Rt;
+ break;
+
+ default:
+ panic("swl: bad offset");
+ }
+#endif
+ }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT);
+
0x3: sw({{ Mem.uw = Rt<31:0>; }});
- 0x6: swr({{ Mem.uh = Rt<15:0>; }},{{ EA = ((Rs + disp) & ~3) + 4;}});
+
+ 0x6: swr({{
+ uint32_t mem_word = 0;
+ uint32_t aligned_addr = (Rs + disp) & ~3;
+ uint32_t unalign_addr = Rs + disp;
+ uint32_t offset = unalign_addr & 0x00000003;
+
+ fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
+
+#if BYTE_ORDER == BIG_ENDIAN
+ switch(offset)
+ {
+ case 0:
+ mem_word &= 0x0FFF;
+ mem_word |= (Rt << 12);
+ Mem = mem_word;
+ break;
+
+ case 1:
+ mem_word &= 0x00FF;
+ mem_word |= (Rt << 8);
+ Mem = mem_word;
+ break;
+
+ case 2:
+ mem_word &= 0x000F;
+ mem_word |= (Rt << 4);
+ Mem = mem_word;
+ break;
+
+ case 3:
+ Mem = Rt;
+ break;
+
+ default:
+ panic("swr: bad offset");
+ }
+#elif BYTE_ORDER == LITTLE_ENDIAN
+ switch(offset)
+ {
+ case 0:
+ Mem = Rt;
+ break;
+
+ case 1:
+ mem_word &= 0x000F;
+ mem_word |= (Rt << 4);
+ Mem = mem_word;
+ break;
+
+ case 2:
+ mem_word &= 0x00FF;
+ mem_word |= (Rt << 8);
+ Mem = mem_word;
+ break;
+
+ case 3:
+ mem_word &= 0x0FFF;
+ mem_word |= (Rt << 12);
+ Mem = mem_word;
+ break;
+
+ default:
+ panic("swr: bad offset");
+ }
+#endif
+ }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT);
}
format WarnUnimpl {
@@ -891,7 +1178,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
- 0x0: WarnUnimpl::ll();
+ 0x0: FailUnimpl::ll();
format LoadMemory {
0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
@@ -901,7 +1188,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
- 0x0: WarnUnimpl::sc();
+ 0x0: FailUnimpl::sc();
format StoreMemory {
0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index cb0f4ac9c..39db88c23 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -179,7 +179,7 @@ output decoder {{
ss << ",";
}
- Addr target = pc + 8 + disp;
+ Addr target = pc + 4 + disp;
std::string str;
if (symtab && symtab->findSymbol(target, str))
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index a47844bee..98e58f7f2 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -29,17 +29,19 @@ output header {{
{
protected:
- int32_t imm;
+ int16_t imm;
+ int32_t sextImm;
+ uint32_t zextImm;
/// Constructor
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
+ MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
+ sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
{
//If Bit 15 is 1 then Sign Extend
- int32_t temp = imm & 0x00008000;
-
+ int32_t temp = sextImm & 0x00008000;
if (temp > 0 && mnemonic != "lui") {
- imm |= 0xFFFF0000;
+ sextImm |= 0xFFFF0000;
}
}
@@ -99,9 +101,9 @@ output decoder {{
}
if( mnemonic == "lui")
- ccprintf(ss, "%08p ", imm);
+ ccprintf(ss, "%08p ", sextImm);
else
- ss << (int) imm;
+ ss << (int) sextImm;
return ss.str();
}
diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa
index 404aa1ee1..df1dca4e1 100644
--- a/arch/mips/isa/formats/mem.isa
+++ b/arch/mips/isa/formats/mem.isa
@@ -446,6 +446,14 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
exec_template_base = 'Store')
}};
+def format UnalignedStore(memacc_code, postacc_code,
+ ea_code = {{ EA = Rb + disp; }},
+ mem_flags = [], inst_flags = []) {{
+ (header_output, decoder_output, decode_block, exec_output) = \
+ LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ postacc_code, exec_template_base = 'Store')
+}};
+
//FP loads are offloaded to these formats for now ...
def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
mem_flags = [], inst_flags = []) {{
diff --git a/arch/mips/isa/formats/unimp.isa b/arch/mips/isa/formats/unimp.isa
index 890cf8d1a..475a88752 100644
--- a/arch/mips/isa/formats/unimp.isa
+++ b/arch/mips/isa/formats/unimp.isa
@@ -110,7 +110,8 @@ output exec {{
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
- "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+ inst2string(machInst));
return new UnimplementedOpcodeFault;
}
diff --git a/arch/mips/isa/formats/unknown.isa b/arch/mips/isa/formats/unknown.isa
index 47d166255..ba83c007e 100644
--- a/arch/mips/isa/formats/unknown.isa
+++ b/arch/mips/isa/formats/unknown.isa
@@ -26,12 +26,34 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+output header {{
+ std::string inst2string(MachInst machInst);
+}};
output decoder {{
+
+std::string inst2string(MachInst machInst)
+{
+ string str = "";
+ uint32_t mask = 0x80000000;
+
+ for(int i=0; i < 32; i++) {
+ if ((machInst & mask) == 0) {
+ str += "0";
+ } else {
+ str += "1";
+ }
+
+ mask = mask >> 1;
+ }
+
+ return str;
+}
+
std::string
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
- "unknown", machInst, OPCODE);
+ return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
+ "unknown", machInst, OPCODE, inst2string(machInst));
}
}};
@@ -41,7 +63,7 @@ output exec {{
Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
- "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
+ "(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
return new UnimplementedOpcodeFault;
}
}};
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index 13870337b..5bc32d6e1 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -26,7 +26,7 @@ def operands {{
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
- 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 35c207828..68ccf931d 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -60,7 +60,7 @@ class SyscallReturn {
template <class T>
SyscallReturn(T v, bool s)
{
- retval = (uint64_t)v;
+ retval = (uint32_t)v;
success = s;
}
@@ -68,7 +68,7 @@ class SyscallReturn {
SyscallReturn(T v)
{
success = (v >= 0);
- retval = (uint64_t)v;
+ retval = (uint32_t)v;
}
~SyscallReturn() {}
@@ -138,7 +138,7 @@ namespace MipsISA
const int SyscallNumReg = ReturnValueReg1;
const int SyscallPseudoReturnReg = ReturnValueReg1;
- const int SyscallSuccessReg = ReturnValueReg1;
+ const int SyscallSuccessReg = ArgumentReg3;
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
@@ -732,21 +732,15 @@ extern const Addr PageOffset;
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
- // check for error condition. Alpha syscall convention is to
- // indicate success/failure in reg a3 (r19) and put the
- // return value itself in the standard return value reg (v0).
if (return_value.successful()) {
// no error
- regs->setIntReg(ReturnValueReg1, 0);
- regs->setIntReg(ReturnValueReg2, return_value.value());
+ regs->setIntReg(SyscallSuccessReg, 0);
+ regs->setIntReg(ReturnValueReg1, return_value.value());
} else {
// got an error, return details
- regs->setIntReg(ReturnValueReg1, (IntReg) -1);
- regs->setIntReg(ReturnValueReg2, -return_value.value());
+ regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
+ regs->setIntReg(ReturnValueReg1, -return_value.value());
}
-
- //regs->intRegFile[ReturnValueReg1] = (IntReg)return_value;
- //panic("Returning from syscall\n");
}
// Machine operations
diff --git a/arch/mips/linux_process.cc b/arch/mips/linux_process.cc
index 92a79cfd1..2d02b09e1 100644
--- a/arch/mips/linux_process.cc
+++ b/arch/mips/linux_process.cc
@@ -132,7 +132,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 14 */ SyscallDesc("mknod", unimplementedFunc),
/* 15 */ SyscallDesc("chmod", chmodFunc<Linux>),
/* 16 */ SyscallDesc("lchown", chownFunc),
- /* 17 */ SyscallDesc("break", unimplementedFunc), /*obreak*/
+ /* 17 */ SyscallDesc("break", obreakFunc), /*obreak*/
/* 18 */ SyscallDesc("unused#18", unimplementedFunc),
/* 19 */ SyscallDesc("lseek", lseekFunc),
/* 20 */ SyscallDesc("getpid", getpidFunc),
@@ -160,7 +160,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 42 */ SyscallDesc("pipe", unimplementedFunc),
/* 43 */ SyscallDesc("times", unimplementedFunc),
/* 44 */ SyscallDesc("prof", unimplementedFunc),
- /* 45 */ SyscallDesc("brk", unimplementedFunc),/*openFunc<Linux>*/
+ /* 45 */ SyscallDesc("brk", obreakFunc),/*openFunc<Linux>*/
/* 46 */ SyscallDesc("setgid", unimplementedFunc),
/* 47 */ SyscallDesc("getgid", getgidFunc),
/* 48 */ SyscallDesc("signal", ignoreFunc),
@@ -182,13 +182,13 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 64 */ SyscallDesc("getppid", getpagesizeFunc),
/* 65 */ SyscallDesc("getpgrp", unimplementedFunc),
/* 66 */ SyscallDesc("setsid", unimplementedFunc),
- /* 67 */ SyscallDesc("sigaction", statFunc<Linux>),
- /* 68 */ SyscallDesc("sgetmask", lstatFunc<Linux>),
+ /* 67 */ SyscallDesc("sigaction",unimplementedFunc),
+ /* 68 */ SyscallDesc("sgetmask", unimplementedFunc),
/* 69 */ SyscallDesc("ssetmask", unimplementedFunc),
/* 70 */ SyscallDesc("setreuid", unimplementedFunc),
- /* 71 */ SyscallDesc("setregid", mmapFunc<Linux>),
+ /* 71 */ SyscallDesc("setregid", unimplementedFunc),
/* 72 */ SyscallDesc("sigsuspend", unimplementedFunc),
- /* 73 */ SyscallDesc("sigpending", munmapFunc),
+ /* 73 */ SyscallDesc("sigpending", unimplementedFunc),
/* 74 */ SyscallDesc("sethostname", ignoreFunc),
/* 75 */ SyscallDesc("setrlimit", unimplementedFunc),
/* 76 */ SyscallDesc("getrlimit", unimplementedFunc),
@@ -206,7 +206,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 88 */ SyscallDesc("reboot", unimplementedFunc),
/* 89 */ SyscallDesc("readdir", unimplementedFunc),
/* 90 */ SyscallDesc("mmap", mmapFunc<Linux>),
- /* 91 */ SyscallDesc("munmap",unimplementedFunc),/*fstatFunc<Linux>*/
+ /* 91 */ SyscallDesc("munmap",munmapFunc),
/* 92 */ SyscallDesc("truncate", fcntlFunc),
/* 93 */ SyscallDesc("ftruncate", unimplementedFunc),
/* 94 */ SyscallDesc("fchmod", unimplementedFunc),
@@ -221,9 +221,9 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 103 */ SyscallDesc("syslog", unimplementedFunc),
/* 104 */ SyscallDesc("setitimer", unimplementedFunc),
/* 105 */ SyscallDesc("getitimer", unimplementedFunc),
- /* 106 */ SyscallDesc("stat", unimplementedFunc),
+ /* 106 */ SyscallDesc("stat", statFunc<Linux>),
/* 107 */ SyscallDesc("lstat", unimplementedFunc),
- /* 108 */ SyscallDesc("fstat", unimplementedFunc),
+ /* 108 */ SyscallDesc("fstat", fstatFunc<Linux>),
/* 109 */ SyscallDesc("unused#109", unimplementedFunc),
/* 110 */ SyscallDesc("iopl", unimplementedFunc),
/* 111 */ SyscallDesc("vhangup", unimplementedFunc),
@@ -240,7 +240,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 122 */ SyscallDesc("uname", unameFunc),
/* 123 */ SyscallDesc("modify_ldt", unimplementedFunc),
/* 124 */ SyscallDesc("adjtimex", unimplementedFunc),
- /* 125 */ SyscallDesc("mprotect", unimplementedFunc),
+ /* 125 */ SyscallDesc("mprotect", ignoreFunc),
/* 126 */ SyscallDesc("sigprocmask", unimplementedFunc),
/* 127 */ SyscallDesc("create_module", unimplementedFunc),
/* 128 */ SyscallDesc("init_module", unimplementedFunc),
@@ -329,8 +329,8 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 211 */ SyscallDesc("truncate64", unimplementedFunc),
/* 212 */ SyscallDesc("ftruncate64", unimplementedFunc),
/* 213 */ SyscallDesc("stat64", unimplementedFunc),
- /* 214 */ SyscallDesc("lstat64", unimplementedFunc),
- /* 215 */ SyscallDesc("fstat64", unimplementedFunc),
+ /* 214 */ SyscallDesc("lstat64", lstat64Func<Linux>),
+ /* 215 */ SyscallDesc("fstat64", fstat64Func<Linux>),
/* 216 */ SyscallDesc("pivot_root", unimplementedFunc),
/* 217 */ SyscallDesc("mincore", unimplementedFunc),
/* 218 */ SyscallDesc("madvise", unimplementedFunc),
@@ -361,7 +361,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
/* 243 */ SyscallDesc("io_getevents", unimplementedFunc),
/* 244 */ SyscallDesc("io_submit", unimplementedFunc),
/* 245 */ SyscallDesc("io_cancel", unimplementedFunc),
- /* 246 */ SyscallDesc("exit_group", unimplementedFunc),
+ /* 246 */ SyscallDesc("exit_group", exitFunc),
/* 247 */ SyscallDesc("lookup_dcookie", unimplementedFunc),
/* 248 */ SyscallDesc("epoll_create", unimplementedFunc),
/* 249 */ SyscallDesc("epoll_ctl", unimplementedFunc),
@@ -415,8 +415,6 @@ MipsLinuxProcess::MipsLinuxProcess(const std::string &name,
//init_regs->intRegFile[0] = 0;
}
-
-
SyscallDesc*
MipsLinuxProcess::getDesc(int callnum)
{
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index c74feec68..eb5d712b9 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -241,17 +241,17 @@ class CPUExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{
return itb->translate(req, proxy);
}
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{
return dtb->translate(req, proxy, false);
}
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{
return dtb->translate(req, proxy, true);
}
@@ -273,17 +273,17 @@ class CPUExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
@@ -292,7 +292,7 @@ class CPUExecContext
/*
template <class T>
- Fault read(CpuRequestPtr &req, T &data)
+ Fault read(RequestPtr &req, T &data)
{
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
if (req->flags & LOCKED) {
@@ -308,7 +308,7 @@ class CPUExecContext
}
template <class T>
- Fault write(CpuRequestPtr &req, T &data)
+ Fault write(RequestPtr &req, T &data)
{
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
ExecContext *xc;
@@ -369,7 +369,7 @@ class CPUExecContext
inst = new_inst;
}
- Fault instRead(CpuRequestPtr &req)
+ Fault instRead(RequestPtr &req)
{
panic("instRead not implemented");
// return funcPhysMem->read(req, inst);
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index dd3d2cba1..9404b126b 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -152,11 +152,11 @@ class ExecContext
virtual int getInstAsid() = 0;
virtual int getDataAsid() = 0;
- virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateInstReq(RequestPtr &req) = 0;
- virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataReadReq(RequestPtr &req) = 0;
- virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
// Also somewhat obnoxious. Really only used for the TLB fault.
// However, may be quite useful in SPARC.
@@ -327,13 +327,13 @@ class ProxyExecContext : public ExecContext
int getInstAsid() { return actualXC->getInstAsid(); }
int getDataAsid() { return actualXC->getDataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{ return actualXC->translateInstReq(req); }
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{ return actualXC->translateDataReadReq(req); }
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{ return actualXC->translateDataWriteReq(req); }
// @todo: Do I need this?
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 88c99c566..261ed8302 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -175,24 +175,24 @@ SimpleCPU::SimpleCPU(Params *p)
xcProxy = cpuXC->getProxy();
#if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- ifetch_req = new CpuRequest;
- ifetch_req->asid = 0;
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req = new Request(true);
+ ifetch_req->setAsid(0);
+ ifetch_req->setSize(sizeof(MachInst));
ifetch_pkt = new Packet;
ifetch_pkt->cmd = Read;
ifetch_pkt->data = (uint8_t *)&inst;
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
- data_read_req = new CpuRequest;
- data_read_req->asid = 0;
+ data_read_req = new Request(true);
+ data_read_req->setAsid(0);
data_read_pkt = new Packet;
data_read_pkt->cmd = Read;
data_read_pkt->data = new uint8_t[8];
data_read_pkt->req = data_read_req;
- data_write_req = new CpuRequest;
- data_write_req->asid = 0;
+ data_write_req = new Request(true);
+ data_write_req->setAsid(0);
data_write_pkt = new Packet;
data_write_pkt->cmd = Write;
data_write_pkt->req = data_write_req;
@@ -493,13 +493,13 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
// memReq->reset(addr, sizeof(T), flags);
#if SIMPLE_CPU_MEM_TIMING
- CpuRequest *data_read_req = new CpuRequest;
+ CpuRequest *data_read_req = new Request(true);
#endif
- data_read_req->vaddr = addr;
- data_read_req->size = sizeof(T);
- data_read_req->flags = flags;
- data_read_req->time = curTick;
+ data_read_req->setVaddr(addr);
+ data_read_req->setSize(sizeof(T));
+ data_read_req->setFlags(flags);
+ data_read_req->setTime(curTick);
// translate to physical address
Fault fault = cpuXC->translateDataReadReq(data_read_req);
@@ -512,7 +512,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
data_read_pkt->req = data_read_req;
data_read_pkt->data = new uint8_t[8];
#endif
- data_read_pkt->addr = data_read_req->paddr;
+ data_read_pkt->addr = data_read_req->getPaddr();
data_read_pkt->size = sizeof(T);
sendDcacheRequest(data_read_pkt);
@@ -559,7 +559,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
}
*/
// This will need a new way to tell if it has a dcache attached.
- if (data_read_req->flags & UNCACHEABLE)
+ if (data_read_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Read");
return fault;
@@ -612,10 +612,10 @@ template <class T>
Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->vaddr = addr;
- data_write_req->time = curTick;
- data_write_req->size = sizeof(T);
- data_write_req->flags = flags;
+ data_write_req->setVaddr(addr);
+ data_write_req->setTime(curTick);
+ data_write_req->setSize(sizeof(T));
+ data_write_req->setFlags(flags);
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
@@ -630,7 +630,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#else
data_write_pkt->data = (uint8_t *)&data;
#endif
- data_write_pkt->addr = data_write_req->paddr;
+ data_write_pkt->addr = data_write_req->getPaddr();
data_write_pkt->size = sizeof(T);
sendDcacheRequest(data_write_pkt);
@@ -664,7 +664,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
*res = data_write_pkt->result;
// This will need a new way to tell if it's hooked up to a cache or not.
- if (data_write_req->flags & UNCACHEABLE)
+ if (data_write_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling
@@ -973,11 +973,11 @@ SimpleCPU::tick()
#if SIMPLE_CPU_MEM_TIMING
CpuRequest *ifetch_req = new CpuRequest();
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req->setSize(sizeof(MachInst));
#endif
- ifetch_req->vaddr = cpuXC->readPC() & ~3;
- ifetch_req->time = curTick;
+ ifetch_req->setVaddr(cpuXC->readPC() & ~3);
+ ifetch_req->setTime(curTick);
/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
IFETCH_FLAGS(xc->regs.pc));
@@ -993,7 +993,7 @@ SimpleCPU::tick()
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
#endif
- ifetch_pkt->addr = ifetch_req->paddr;
+ ifetch_pkt->addr = ifetch_req->getPaddr();
sendIcacheRequest(ifetch_pkt);
#if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 43287a33b..11137b6e6 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -210,12 +210,12 @@ class SimpleCPU : public BaseCPU
#if SIMPLE_CPU_MEM_TIMING
Packet *retry_pkt;
#elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- CpuRequest *ifetch_req;
- Packet *ifetch_pkt;
- CpuRequest *data_read_req;
- Packet *data_read_pkt;
- CpuRequest *data_write_req;
- Packet *data_write_pkt;
+ Request *ifetch_req;
+ Packet *ifetch_pkt;
+ Request *data_read_req;
+ Packet *data_read_pkt;
+ Request *data_write_req;
+ Packet *data_write_pkt;
#endif
// Pointer to the sampler that is telling us to switchover.
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index a200e2849..f0b75c10e 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -397,8 +397,9 @@ class StaticInst : public StaticInstBase
int getRs() { return (machInst & 0x03E00000) >> 21; } //25...21
int getRt() { return (machInst & 0x001F0000) >> 16; } //20...16
int getRd() { return (machInst & 0x0000F800) >> 11; } //15...11
- int getOpname(){ return (machInst & 0x0000003F); }//5...0
- int getBranch(){ return (machInst & 0x0000FFFF); }//5...0
+ int getImm() { return (machInst & 0x0000FFFF); } //15...0
+ int getFunction(){ return (machInst & 0x0000003F); }//5...0
+ int getBranch(){ return (machInst & 0x0000FFFF); }//15...0
int getJump(){ return (machInst & 0x03FFFFFF); }//5...0
int getHint(){ return (machInst & 0x000007C0) >> 6; } //10...6
std::string getName() { return mnemonic; }
diff --git a/dev/io_device.cc b/dev/io_device.cc
index 9fd478826..15c835ded 100644
--- a/dev/io_device.cc
+++ b/dev/io_device.cc
@@ -78,7 +78,7 @@ bool
PioPort::recvTiming(Packet &pkt)
{
device->recvAtomic(pkt);
- sendTiming(pkt, pkt.time-pkt.req->time);
+ sendTiming(pkt, pkt.time-pkt.req->getTime());
return Success;
}
@@ -140,7 +140,7 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
int prevSize = 0;
Packet basePkt;
- Request baseReq;
+ Request baseReq(false);
basePkt.flags = 0;
basePkt.coherence = NULL;
@@ -150,8 +150,8 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
basePkt.cmd = cmd;
basePkt.result = Unknown;
basePkt.req = NULL;
- baseReq.nicReq = true;
- baseReq.time = curTick;
+// baseReq.nicReq = true;
+ baseReq.setTime(curTick);
completionEvent = event;
@@ -162,8 +162,8 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
pkt->addr = gen.addr();
pkt->size = gen.size();
pkt->req = req;
- pkt->req->paddr = pkt->addr;
- pkt->req->size = pkt->size;
+ pkt->req->setPaddr(pkt->addr);
+ pkt->req->setSize(pkt->size);
// Increment the data pointer on a write
pkt->data = data ? data + prevSize : NULL ;
prevSize += pkt->size;
@@ -186,7 +186,7 @@ DmaPort::sendDma(Packet &pkt)
transmitList.push_back(&packet);
} else if (state == Atomic) {*/
sendAtomic(pkt);
- completionEvent->schedule(pkt.time - pkt.req->time);
+ completionEvent->schedule(pkt.time - pkt.req->getTime());
completionEvent = NULL;
/* } else if (state == Functional) {
sendFunctional(pkt);
diff --git a/mem/page_table.cc b/mem/page_table.cc
index 714ddde35..c4e1ea193 100644
--- a/mem/page_table.cc
+++ b/mem/page_table.cc
@@ -121,11 +121,14 @@ PageTable::translate(Addr vaddr, Addr &paddr)
Fault
-PageTable::translate(CpuRequestPtr &req)
+PageTable::translate(RequestPtr &req)
{
- assert(pageAlign(req->vaddr + req->size - 1) == pageAlign(req->vaddr));
- if (!translate(req->vaddr, req->paddr)) {
+ Addr paddr;
+ assert(pageAlign(req->getVaddr() + req->getSize() - 1)
+ == pageAlign(req->getVaddr()));
+ if (!translate(req->getVaddr(), paddr)) {
return genMachineCheckFault();
}
- return page_check(req->paddr, req->size);
+ req->setPaddr(paddr);
+ return page_check(req->getPaddr(), req->getSize());
}
diff --git a/mem/page_table.hh b/mem/page_table.hh
index 8f0842f58..26248261a 100644
--- a/mem/page_table.hh
+++ b/mem/page_table.hh
@@ -83,7 +83,7 @@ class PageTable
* field of mem_req.
* @param req The memory request.
*/
- Fault translate(CpuRequestPtr &req);
+ Fault translate(RequestPtr &req);
};
diff --git a/mem/port.cc b/mem/port.cc
index fb4f3b4e0..d19d8146c 100644
--- a/mem/port.cc
+++ b/mem/port.cc
@@ -36,15 +36,15 @@
void
Port::blobHelper(Addr addr, uint8_t *p, int size, Command cmd)
{
- Request req;
+ Request req(false);
Packet pkt;
pkt.req = &req;
pkt.cmd = cmd;
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
- pkt.addr = req.paddr = gen.addr();
- pkt.size = req.size = gen.size();
+ req.setPaddr(pkt.addr = gen.addr());
+ req.setSize(pkt.size = gen.size());
pkt.data = p;
sendFunctional(pkt);
p += gen.size();
diff --git a/mem/request.hh b/mem/request.hh
index 5e2275741..90c46646e 100644
--- a/mem/request.hh
+++ b/mem/request.hh
@@ -37,10 +37,8 @@
#include "arch/isa_traits.hh"
class Request;
-class CpuRequest;
typedef Request* RequestPtr;
-typedef CpuRequest* CpuRequestPtr;
/** The request is a Load locked/store conditional. */
const unsigned LOCKED = 0x001;
@@ -58,50 +56,140 @@ const unsigned NO_FAULT = 0x020;
const unsigned PF_EXCLUSIVE = 0x100;
/** The request should be marked as LRU. */
const unsigned EVICT_NEXT = 0x200;
+/** The request should ignore unaligned access faults */
+const unsigned NO_ALIGN_FAULT = 0x400;
class Request
{
//@todo Make Accesor functions, make these private.
public:
+ /** Cunstructor, needs a bool to signify if it is/isn't Cpu Request. */
+ Request(bool isCpu);
+
+//First non-cpu request fields
+ private:
/** The physical address of the request. */
Addr paddr;
-
- /** whether this req came from the CPU or not **DO we need this??***/
- bool nicReq;
+ /** Wether or not paddr is valid (has been written yet). */
+ bool validPaddr;
/** The size of the request. */
int size;
+ /** Wether or not size is valid (has been written yet). */
+ bool validSize;
/** The time this request was started. Used to calculate latencies. */
Tick time;
+ /** Wether or not time is valid (has been written yet). */
+ bool validTime;
/** Destination address if this is a block copy. */
Addr copyDest;
+ /** Wether or not copyDest is valid (has been written yet). */
+ bool validCopyDest;
+ /** Flag structure for the request. */
uint32_t flags;
-};
+ /** Wether or not flags is valid (has been written yet). */
+ bool validFlags;
-class CpuRequest : public Request
-{
- //@todo Make Accesor functions, make these private.
+//Accsesors for non-cpu request fields
public:
+ /** Accesor for paddr. */
+ Addr getPaddr();
+ /** Accesor for paddr. */
+ void setPaddr(Addr _paddr);
+
+ /** Accesor for size. */
+ int getSize();
+ /** Accesor for size. */
+ void setSize(int _size);
+
+ /** Accesor for time. */
+ Tick getTime();
+ /** Accesor for time. */
+ void setTime(Tick _time);
+
+ /** Accesor for copy dest. */
+ Addr getCopyDest();
+ /** Accesor for copy dest. */
+ void setCopyDest(Addr _copyDest);
+
+ /** Accesor for flags. */
+ uint32_t getFlags();
+ /** Accesor for paddr. */
+ void setFlags(uint32_t _flags);
+
+//Now cpu-request fields
+ private:
+ /** Bool to signify if this is a cpuRequest. */
+ bool cpuReq;
+
/** The virtual address of the request. */
Addr vaddr;
+ /** Wether or not the vaddr is valid. */
+ bool validVaddr;
/** The address space ID. */
int asid;
+ /** Wether or not the asid is valid. */
+ bool validAsid;
/** The return value of store conditional. */
uint64_t scResult;
+ /** Wether or not the sc result is valid. */
+ bool validScResult;
/** The cpu number for statistics. */
int cpuNum;
+ /** Wether or not the cpu number is valid. */
+ bool validCpuNum;
/** The requesting thread id. */
int threadNum;
+ /** Wether or not the thread id is valid. */
+ bool validThreadNum;
/** program counter of initiating access; for tracing/debugging */
Addr pc;
+ /** Wether or not the pc is valid. */
+ bool validPC;
+
+//Accessor Functions for cpu request fields
+ public:
+ /** Accesor function to determine if this is a cpu request or not.*/
+ bool isCpuRequest();
+
+ /** Accesor function for vaddr.*/
+ Addr getVaddr();
+ /** Accesor function for vaddr.*/
+ void setVaddr(Addr _vaddr);
+
+ /** Accesor function for asid.*/
+ int getAsid();
+ /** Accesor function for asid.*/
+ void setAsid(int _asid);
+
+ /** Accesor function for store conditional return value.*/
+ uint64_t getScResult();
+ /** Accesor function for store conditional return value.*/
+ void setScResult(uint64_t _scResult);
+
+ /** Accesor function for cpu number.*/
+ int getCpuNum();
+ /** Accesor function for cpu number.*/
+ void setCpuNum(int _cpuNum);
+
+ /** Accesor function for thread number.*/
+ int getThreadNum();
+ /** Accesor function for thread number.*/
+ void setThreadNum(int _threadNum);
+
+ /** Accesor function for pc.*/
+ Addr getPC();
+ /** Accesor function for pc.*/
+ void setPC(Addr _pc);
+
};
#endif // __MEM_REQUEST_HH__
diff --git a/sim/syscall_emul.cc b/sim/syscall_emul.cc
index 9e49c6a5e..ed0da628e 100644
--- a/sim/syscall_emul.cc
+++ b/sim/syscall_emul.cc
@@ -48,13 +48,15 @@ using namespace TheISA;
void
SyscallDesc::doSyscall(int callnum, Process *process, ExecContext *xc)
{
- DPRINTFR(SyscallVerbose, "%s: syscall %s called\n",
- xc->getCpuPtr()->name(), name);
+ DPRINTFR(SyscallVerbose, "%d: %s: syscall %s called w/arguments %d,%d,%d,%d\n",
+ curTick,xc->getCpuPtr()->name(), name,
+ xc->getSyscallArg(0),xc->getSyscallArg(1),
+ xc->getSyscallArg(2),xc->getSyscallArg(3));
SyscallReturn retval = (*funcPtr)(this, callnum, process, xc);
- DPRINTFR(SyscallVerbose, "%s: syscall %s returns %d\n",
- xc->getCpuPtr()->name(), name, retval.value());
+ DPRINTFR(SyscallVerbose, "%d: %s: syscall %s returns %d\n",
+ curTick,xc->getCpuPtr()->name(), name, retval.value());
if (!(flags & SyscallDesc::SuppressReturnValue))
xc->setSyscallReturn(retval);
@@ -65,8 +67,6 @@ SyscallReturn
unimplementedFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
- //warn("ignoring syscall %s(%d, %d, ...)", desc->name,
- // xc->getSyscallArg(0), xc->getSyscallArg(1));
fatal("syscall %s (#%d) unimplemented.", desc->name, callnum);
return 1;
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 18:12:54 +0000