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-rw-r--r--src/SConscript1
-rw-r--r--src/cpu/ozone/front_end_impl.hh1
-rw-r--r--src/mem/bus.hh1
-rw-r--r--src/sim/byteswap.hh3
-rw-r--r--src/sim/main.cc5
5 files changed, 3 insertions, 8 deletions
diff --git a/src/SConscript b/src/SConscript
index 157a911ed..124f88708 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -108,7 +108,6 @@ base_sources = Split('''
sim/main.cc
python/swig/cc_main_wrap.cc
sim/param.cc
- sim/profile.cc
sim/root.cc
sim/serialize.cc
sim/sim_events.cc
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 467567c10..8082e01b9 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -35,7 +35,6 @@
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
#include "mem/mem_interface.hh"
-#include "sim/byte_swap.hh"
using namespace TheISA;
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index c2b78c31f..9c7054b94 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
+ * Ali Saidi
*/
/**
diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh
index 03bfad954..c78c77364 100644
--- a/src/sim/byteswap.hh
+++ b/src/sim/byteswap.hh
@@ -25,7 +25,8 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Gabe Black
+ * Authors: Ali Saidi
+ * Nathan Binkert
*/
//The purpose of this file is to provide endainness conversion utility
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 5a99e15b4..bf844da7f 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -427,11 +427,6 @@ finalInit()
SimObject::regAllStats();
- // uncomment the following to get PC-based execution-time profile
-#ifdef DO_PROFILE
- init_profile((char *)&_init, (char *)&_fini);
-#endif
-
// Check to make sure that the stats package is properly initialized
Stats::check();