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-rw-r--r--src/arch/arm/table_walker.cc6
-rw-r--r--src/cpu/minor/cpu.cc8
-rw-r--r--src/cpu/o3/cpu.cc12
-rw-r--r--src/cpu/o3/cpu.hh2
-rw-r--r--src/dev/arm/flash_device.cc4
-rw-r--r--src/dev/arm/ufs_device.cc4
-rw-r--r--src/dev/copy_engine.cc14
-rw-r--r--src/dev/dma_device.cc4
-rw-r--r--src/dev/i8254xGBe.cc14
-rw-r--r--src/dev/i8254xGBe.hh4
-rw-r--r--src/dev/ide_disk.cc6
-rw-r--r--src/dev/io_device.cc4
-rw-r--r--src/dev/ns_gige.cc8
-rw-r--r--src/dev/pcidev.cc4
-rw-r--r--src/dev/sinic.cc4
-rw-r--r--src/mem/cache/base.cc4
-rw-r--r--src/mem/cache/mshr_queue.cc6
-rw-r--r--src/mem/dram_ctrl.cc4
-rw-r--r--src/mem/dramsim2.cc4
-rw-r--r--src/mem/ruby/system/DMASequencer.cc4
-rw-r--r--src/mem/ruby/system/RubyPort.cc4
-rw-r--r--src/mem/ruby/system/Sequencer.cc4
-rw-r--r--src/mem/simple_mem.cc4
-rw-r--r--src/sim/drain.cc6
-rw-r--r--src/sim/drain.hh62
-rw-r--r--src/sim/sim_object.cc2
-rw-r--r--src/sim/system.cc4
27 files changed, 103 insertions, 103 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index f58d8a268..297054131 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -139,7 +139,7 @@ TableWalker::completeDrain()
{
if (drainManager && stateQueues[L1].empty() && stateQueues[L2].empty() &&
pendingQueue.empty()) {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
drainManager->signalDrainDone();
drainManager = NULL;
@@ -160,13 +160,13 @@ TableWalker::drain(DrainManager *dm)
if (state_queues_not_empty || pendingQueue.size()) {
drainManager = dm;
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
DPRINTF(Drain, "TableWalker not drained\n");
// return port drain count plus the table walker itself needs to drain
return 1;
} else {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "TableWalker free, no need to drain\n");
// table walker is drained, but its ports may still need to be drained
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index d21bf7042..ac1a18bf9 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -217,7 +217,7 @@ void
MinorCPU::signalDrainDone()
{
DPRINTF(Drain, "MinorCPU drain done\n");
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
drainManager->signalDrainDone();
drainManager = NULL;
}
@@ -225,8 +225,8 @@ MinorCPU::signalDrainDone()
void
MinorCPU::drainResume()
{
- assert(getDrainState() == Drainable::Drained ||
- getDrainState() == Drainable::Running);
+ assert(getDrainState() == DrainState::Drained ||
+ getDrainState() == DrainState::Running);
if (switchedOut()) {
DPRINTF(Drain, "drainResume while switched out. Ignoring\n");
@@ -243,7 +243,7 @@ MinorCPU::drainResume()
wakeup();
pipeline->drainResume();
- setDrainState(Drainable::Running);
+ setDrainState(DrainState::Running);
}
void
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 18e958278..89256a7f0 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -539,7 +539,7 @@ FullO3CPU<Impl>::tick()
{
DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
assert(!switchedOut());
- assert(getDrainState() != Drainable::Drained);
+ assert(getDrainState() != DrainState::Drained);
++numCycles;
ppCycles->notify(1);
@@ -712,7 +712,7 @@ FullO3CPU<Impl>::activateContext(ThreadID tid)
// We don't want to wake the CPU if it is drained. In that case,
// we just want to flag the thread as active and schedule the tick
// event from drainResume() instead.
- if (getDrainState() == Drainable::Drained)
+ if (getDrainState() == DrainState::Drained)
return;
// If we are time 0 or if the last activation time is in the past,
@@ -1004,12 +1004,12 @@ FullO3CPU<Impl>::drain(DrainManager *drain_manager)
{
// If the CPU isn't doing anything, then return immediately.
if (switchedOut()) {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return 0;
}
DPRINTF(Drain, "Draining...\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
// We only need to signal a drain to the commit stage as this
// initiates squashing controls the draining. Once the commit
@@ -1031,7 +1031,7 @@ FullO3CPU<Impl>::drain(DrainManager *drain_manager)
return 1;
} else {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "CPU is already drained\n");
if (tickEvent.scheduled())
deschedule(tickEvent);
@@ -1132,7 +1132,7 @@ template <class Impl>
void
FullO3CPU<Impl>::drainResume()
{
- setDrainState(Drainable::Running);
+ setDrainState(DrainState::Running);
if (switchedOut())
return;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index bbc9fde8e..44400542a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -336,7 +336,7 @@ class FullO3CPU : public BaseO3CPU
void updateThreadPriority();
/** Is the CPU draining? */
- bool isDraining() const { return getDrainState() == Drainable::Draining; }
+ bool isDraining() const { return getDrainState() == DrainState::Draining; }
void serializeThread(CheckpointOut &cp,
ThreadID tid) const M5_ATTR_OVERRIDE;
diff --git a/src/dev/arm/flash_device.cc b/src/dev/arm/flash_device.cc
index 96f8f0566..e4bfcf5c9 100644
--- a/src/dev/arm/flash_device.cc
+++ b/src/dev/arm/flash_device.cc
@@ -601,10 +601,10 @@ FlashDevice::drain(DrainManager *dm)
if (count) {
DPRINTF(Drain, "Flash device is draining...\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
} else {
DPRINTF(Drain, "Flash device drained\n");
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
}
return count;
}
diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 02df00e35..ef6398216 100644
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -2333,10 +2333,10 @@ UFSHostDevice::drain(DrainManager *dm)
if (count) {
DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
} else {
DPRINTF(UFSHostDevice, "UFSDevice drained\n");
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
}
return count;
}
diff --git a/src/dev/copy_engine.cc b/src/dev/copy_engine.cc
index 5506103b1..035f824fa 100644
--- a/src/dev/copy_engine.cc
+++ b/src/dev/copy_engine.cc
@@ -140,12 +140,12 @@ CopyEngine::CopyEngineChannel::recvCommand()
cr.status.dma_transfer_status(0);
nextState = DescriptorFetch;
fetchAddress = cr.descChainAddr;
- if (ce->getDrainState() == Drainable::Running)
+ if (ce->getDrainState() == DrainState::Running)
fetchDescriptor(cr.descChainAddr);
} else if (cr.command.append_dma()) {
if (!busy) {
nextState = AddressFetch;
- if (ce->getDrainState() == Drainable::Running)
+ if (ce->getDrainState() == DrainState::Running)
fetchNextAddr(lastDescriptorAddr);
} else
refreshNext = true;
@@ -635,20 +635,20 @@ CopyEngine::CopyEngineChannel::fetchAddrComplete()
bool
CopyEngine::CopyEngineChannel::inDrain()
{
- if (ce->getDrainState() == Drainable::Draining) {
+ if (ce->getDrainState() == DrainState::Draining) {
DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
assert(drainManager);
drainManager->signalDrainDone();
drainManager = NULL;
}
- return ce->getDrainState() != Drainable::Running;
+ return ce->getDrainState() != DrainState::Running;
}
unsigned int
CopyEngine::CopyEngineChannel::drain(DrainManager *dm)
{
- if (nextState == Idle || ce->getDrainState() != Drainable::Running)
+ if (nextState == Idle || ce->getDrainState() != DrainState::Running)
return 0;
unsigned int count = 1;
count += cePort.drain(dm);
@@ -667,9 +667,9 @@ CopyEngine::drain(DrainManager *dm)
count += chan[x]->drain(dm);
if (count)
- setDrainState(Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drained);
+ setDrainState(DrainState::Drained);
DPRINTF(Drain, "CopyEngine not drained\n");
return count;
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 24d833b54..a778833ff 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -130,9 +130,9 @@ DmaDevice::drain(DrainManager *dm)
{
unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm);
if (count)
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 0ff52bda0..3b49c8b5d 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -586,7 +586,7 @@ IGbE::write(PacketPtr pkt)
case REG_RDT:
regs.rdt = val;
DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
- if (getDrainState() == Drainable::Running) {
+ if (getDrainState() == DrainState::Running) {
DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
rxDescCache.fetchDescriptors();
} else {
@@ -626,7 +626,7 @@ IGbE::write(PacketPtr pkt)
case REG_TDT:
regs.tdt = val;
DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
- if (getDrainState() == Drainable::Running) {
+ if (getDrainState() == DrainState::Running) {
DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
txDescCache.fetchDescriptors();
} else {
@@ -905,7 +905,7 @@ void
IGbE::DescCache<T>::writeback1()
{
// If we're draining delay issuing this DMA
- if (igbe->getDrainState() != Drainable::Running) {
+ if (igbe->getDrainState() != DrainState::Running) {
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
return;
}
@@ -986,7 +986,7 @@ void
IGbE::DescCache<T>::fetchDescriptors1()
{
// If we're draining delay issuing this DMA
- if (igbe->getDrainState() != Drainable::Running) {
+ if (igbe->getDrainState() != DrainState::Running) {
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
return;
}
@@ -2051,7 +2051,7 @@ void
IGbE::restartClock()
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
- getDrainState() == Drainable::Running)
+ getDrainState() == DrainState::Running)
schedule(tickEvent, clockEdge(Cycles(1)));
}
@@ -2075,9 +2075,9 @@ IGbE::drain(DrainManager *dm)
if (count) {
DPRINTF(Drain, "IGbE not drained\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
} else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index d353c1d83..116fa5b95 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -352,7 +352,7 @@ class IGbE : public EtherDevice
virtual void updateHead(long h) { igbe->regs.rdh(h); }
virtual void enableSm();
virtual void fetchAfterWb() {
- if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running)
+ if (!igbe->rxTick && igbe->getDrainState() == DrainState::Running)
fetchDescriptors();
}
@@ -414,7 +414,7 @@ class IGbE : public EtherDevice
virtual void enableSm();
virtual void actionAfterWb();
virtual void fetchAfterWb() {
- if (!igbe->txTick && igbe->getDrainState() == Drainable::Running)
+ if (!igbe->txTick && igbe->getDrainState() == DrainState::Running)
fetchDescriptors();
}
diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc
index bbdee8e51..2e6df3805 100644
--- a/src/dev/ide_disk.cc
+++ b/src/dev/ide_disk.cc
@@ -342,7 +342,7 @@ IdeDisk::doDmaTransfer()
panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
dmaState, devState);
- if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
+ if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
schedule(dmaTransferEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else
@@ -436,7 +436,7 @@ IdeDisk::doDmaRead()
curPrd.getByteCount(), TheISA::PageBytes);
}
- if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
+ if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
schedule(dmaReadWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaReadCG->done()) {
@@ -518,7 +518,7 @@ IdeDisk::doDmaWrite()
dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
curPrd.getByteCount(), TheISA::PageBytes);
}
- if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
+ if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
DPRINTF(IdeDisk, "doDmaWrite: rescheduling\n");
return;
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index c25a28dd2..9e5855a0b 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -99,9 +99,9 @@ PioDevice::drain(DrainManager *dm)
unsigned int count;
count = pioPort.drain(dm);
if (count)
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index c525f6359..7a8d202c5 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -1068,7 +1068,7 @@ NSGigE::doRxDmaRead()
assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting);
rxDmaState = dmaReading;
- if (dmaPending() || getDrainState() != Drainable::Running)
+ if (dmaPending() || getDrainState() != DrainState::Running)
rxDmaState = dmaReadWaiting;
else
dmaRead(rxDmaAddr, rxDmaLen, &rxDmaReadEvent, (uint8_t*)rxDmaData);
@@ -1099,7 +1099,7 @@ NSGigE::doRxDmaWrite()
assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting);
rxDmaState = dmaWriting;
- if (dmaPending() || getDrainState() != Running)
+ if (dmaPending() || getDrainState() != DrainState::Running)
rxDmaState = dmaWriteWaiting;
else
dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaWriteEvent, (uint8_t*)rxDmaData);
@@ -1515,7 +1515,7 @@ NSGigE::doTxDmaRead()
assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
txDmaState = dmaReading;
- if (dmaPending() || getDrainState() != Running)
+ if (dmaPending() || getDrainState() != DrainState::Running)
txDmaState = dmaReadWaiting;
else
dmaRead(txDmaAddr, txDmaLen, &txDmaReadEvent, (uint8_t*)txDmaData);
@@ -1546,7 +1546,7 @@ NSGigE::doTxDmaWrite()
assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
txDmaState = dmaWriting;
- if (dmaPending() || getDrainState() != Running)
+ if (dmaPending() || getDrainState() != DrainState::Running)
txDmaState = dmaWriteWaiting;
else
dmaWrite(txDmaAddr, txDmaLen, &txDmaWriteEvent, (uint8_t*)txDmaData);
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 581ae2ebd..5788c94d2 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -261,9 +261,9 @@ PciDevice::drain(DrainManager *dm)
unsigned int count;
count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
if (count)
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index d5a05b319..1ba076200 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -868,7 +868,7 @@ Device::rxKick()
break;
case rxBeginCopy:
- if (dmaPending() || getDrainState() != Drainable::Running)
+ if (dmaPending() || getDrainState() != DrainState::Running)
goto exit;
rxDmaAddr = params()->platform->pciToDma(
@@ -1068,7 +1068,7 @@ Device::txKick()
break;
case txBeginCopy:
- if (dmaPending() || getDrainState() != Drainable::Running)
+ if (dmaPending() || getDrainState() != DrainState::Running)
goto exit;
txDmaAddr = params()->platform->pciToDma(
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 1d0b9a3dd..e58d5f6b9 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -783,12 +783,12 @@ BaseCache::drain(DrainManager *dm)
// Set status
if (count != 0) {
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
DPRINTF(Drain, "Cache not drained\n");
return count;
}
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return 0;
}
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index f8587e1f1..3736c9f21 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -186,7 +186,7 @@ MSHRQueue::deallocateOne(MSHR *mshr)
DPRINTF(Drain, "MSHRQueue now empty, signalling drained\n");
drainManager->signalDrainDone();
drainManager = NULL;
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
}
return retval;
}
@@ -269,11 +269,11 @@ unsigned int
MSHRQueue::drain(DrainManager *dm)
{
if (allocated == 0) {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return 0;
} else {
drainManager = dm;
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
return 1;
}
}
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 7657cc776..9d264d971 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -2189,9 +2189,9 @@ DRAMCtrl::drain(DrainManager *dm)
}
if (count)
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index be244bd4a..dfeca0d47 100644
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -362,11 +362,11 @@ DRAMSim2::drain(DrainManager* dm)
// check our outstanding reads and writes and if any they need to
// drain
if (nbrOutstanding() != 0) {
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
drainManager = dm;
return 1;
} else {
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return 0;
}
}
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 43ef37f08..b10538024 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -192,12 +192,12 @@ DMASequencer::drain(DrainManager *dm)
drainManager = dm;
DPRINTF(Drain, "DMASequencer not drained\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
return child_drain_count + 1;
}
drainManager = NULL;
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return child_drain_count;
}
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ec1780c7a..b6aa871b3 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -449,12 +449,12 @@ RubyPort::drain(DrainManager *dm)
drainManager = dm;
DPRINTF(Drain, "RubyPort not drained\n");
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
return child_drain_count + 1;
}
drainManager = NULL;
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return child_drain_count;
}
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index b1d22b549..c33f5f819 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -77,7 +77,7 @@ Sequencer::~Sequencer()
void
Sequencer::wakeup()
{
- assert(getDrainState() != Drainable::Draining);
+ assert(getDrainState() != DrainState::Draining);
// Check for deadlock of any of the requests
Cycles current_time = curCycle();
@@ -215,7 +215,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
// See if we should schedule a deadlock check
if (!deadlockCheckEvent.scheduled() &&
- getDrainState() != Drainable::Draining) {
+ getDrainState() != DrainState::Draining) {
schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
}
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 180339459..f36301809 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -246,9 +246,9 @@ SimpleMemory::drain(DrainManager *dm)
}
if (count)
- setDrainState(Drainable::Draining);
+ setDrainState(DrainState::Draining);
else
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return count;
}
diff --git a/src/sim/drain.cc b/src/sim/drain.cc
index 3daf762f6..90fb0c18d 100644
--- a/src/sim/drain.cc
+++ b/src/sim/drain.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -58,7 +58,7 @@ DrainManager::drainCycleDone()
Drainable::Drainable()
- : _drainState(Running)
+ : _drainState(DrainState::Running)
{
}
@@ -69,5 +69,5 @@ Drainable::~Drainable()
void
Drainable::drainResume()
{
- _drainState = Running;
+ _drainState = DrainState::Running;
}
diff --git a/src/sim/drain.hh b/src/sim/drain.hh
index 6f0769f34..ae80fb7e9 100644
--- a/src/sim/drain.hh
+++ b/src/sim/drain.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -45,7 +45,33 @@
#include "base/flags.hh"
-class Event;
+class Drainable;
+
+#ifndef SWIG // SWIG doesn't support strongly typed enums
+/**
+ * Object drain/handover states
+ *
+ * An object starts out in the Running state. When the simulator
+ * prepares to take a snapshot or prepares a CPU for handover, it
+ * calls the drain() method to transfer the object into the Draining
+ * or Drained state. If any object enters the Draining state
+ * (Drainable::drain() returning >0), simulation continues until it
+ * all objects have entered the Drained state.
+ *
+ * Before resuming simulation, the simulator calls resume() to
+ * transfer the object to the Running state.
+ *
+ * \note Even though the state of an object (visible to the rest of
+ * the world through Drainable::getState()) could be used to determine
+ * if all objects have entered the Drained state, the protocol is
+ * actually a bit more elaborate. See Drainable::drain() for details.
+ */
+enum class DrainState {
+ Running, /** Running normally */
+ Draining, /** Draining buffers pending serialization/handover */
+ Drained /** Buffers drained, ready for serialization/handover */
+};
+#endif
/**
* This class coordinates draining of a System.
@@ -141,30 +167,6 @@ class DrainManager
class Drainable
{
public:
- /**
- * Object drain/handover states
- *
- * An object starts out in the Running state. When the simulator
- * prepares to take a snapshot or prepares a CPU for handover, it
- * calls the drain() method to transfer the object into the
- * Draining or Drained state. If any object enters the Draining
- * state (drain() returning >0), simulation continues until it all
- * objects have entered the Drained state.
- *
- * Before resuming simulation, the simulator calls resume() to
- * transfer the object to the Running state.
- *
- * \note Even though the state of an object (visible to the rest
- * of the world through getState()) could be used to determine if
- * all objects have entered the Drained state, the protocol is
- * actually a bit more elaborate. See drain() for details.
- */
- enum State {
- Running, /** Running normally */
- Draining, /** Draining buffers pending serialization/handover */
- Drained /** Buffers drained, ready for serialization/handover */
- };
-
Drainable();
virtual ~Drainable();
@@ -225,15 +227,13 @@ class Drainable
*/
virtual void memInvalidate() {};
- State getDrainState() const { return _drainState; }
+ DrainState getDrainState() const { return _drainState; }
protected:
- void setDrainState(State new_state) { _drainState = new_state; }
-
+ void setDrainState(DrainState new_state) { _drainState = new_state; }
private:
- State _drainState;
-
+ DrainState _drainState;
};
DrainManager *createDrainManager();
diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 2c4ba48f6..9ea51eb93 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -183,7 +183,7 @@ debugObjectBreak(const char *objs)
unsigned int
SimObject::drain(DrainManager *drain_manager)
{
- setDrainState(Drained);
+ setDrainState(DrainState::Drained);
return 0;
}
diff --git a/src/sim/system.cc b/src/sim/system.cc
index f781377f7..3d4737617 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -191,7 +191,7 @@ System::getMasterPort(const std::string &if_name, PortID idx)
void
System::setMemoryMode(Enums::MemoryMode mode)
{
- assert(getDrainState() == Drainable::Drained);
+ assert(getDrainState() == DrainState::Drained);
memoryMode = mode;
}
@@ -358,7 +358,7 @@ System::isMemAddr(Addr addr) const
unsigned int
System::drain(DrainManager *dm)
{
- setDrainState(Drainable::Drained);
+ setDrainState(DrainState::Drained);
return 0;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 12:42:06 +0000