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-rw-r--r--arch/alpha/alpha_linux_process.cc1
-rw-r--r--arch/alpha/alpha_memory.hh2
-rw-r--r--arch/alpha/alpha_tru64_process.cc1
-rw-r--r--arch/alpha/arguments.cc2
-rw-r--r--arch/alpha/ev5.hh4
-rw-r--r--arch/alpha/isa/branch.isa8
-rw-r--r--arch/alpha/isa/main.isa30
-rw-r--r--arch/alpha/isa/mem.isa20
-rw-r--r--arch/alpha/isa/pal.isa8
-rw-r--r--arch/alpha/isa_traits.hh95
-rw-r--r--arch/alpha/stacktrace.cc3
-rw-r--r--arch/alpha/stacktrace.hh11
-rw-r--r--arch/alpha/vtophys.cc1
-rw-r--r--arch/alpha/vtophys.hh16
-rwxr-xr-xarch/isa_parser.py19
-rw-r--r--arch/isa_specific.hh76
-rw-r--r--arch/mips/isa/base.isa63
-rw-r--r--arch/mips/isa/decoder.isa1108
-rw-r--r--arch/mips/isa/formats.isa14
-rw-r--r--arch/mips/isa/formats/basic.isa3
-rw-r--r--arch/mips/isa/formats/branch.isa184
-rw-r--r--arch/mips/isa/formats/int.isa17
-rw-r--r--arch/mips/isa/formats/noop.isa62
-rw-r--r--arch/mips/isa/formats/util.isa26
-rw-r--r--arch/mips/isa/operands.isa7
-rw-r--r--arch/mips/isa_traits.hh2
-rw-r--r--base/loader/object_file.hh1
-rw-r--r--base/loader/symtab.hh3
-rw-r--r--base/remote_gdb.cc3
-rw-r--r--base/remote_gdb.hh3
-rw-r--r--cpu/base.cc10
-rw-r--r--cpu/base.hh7
-rw-r--r--cpu/base_dyn_inst.cc2
-rw-r--r--cpu/base_dyn_inst.hh20
-rw-r--r--cpu/exec_context.hh24
-rw-r--r--cpu/exetrace.hh10
-rw-r--r--cpu/memtest/memtest.cc1
-rw-r--r--cpu/memtest/memtest.hh2
-rw-r--r--cpu/o3/2bit_local_pred.hh4
-rw-r--r--cpu/o3/alpha_cpu.hh4
-rw-r--r--cpu/o3/alpha_cpu_impl.hh4
-rw-r--r--cpu/o3/alpha_dyn_inst.hh33
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh2
-rw-r--r--cpu/o3/alpha_impl.hh5
-rw-r--r--cpu/o3/bpred_unit.hh2
-rw-r--r--cpu/o3/bpred_unit_impl.hh2
-rw-r--r--cpu/o3/btb.cc2
-rw-r--r--cpu/o3/btb.hh4
-rw-r--r--cpu/o3/commit.hh1
-rw-r--r--cpu/o3/cpu.cc18
-rw-r--r--cpu/o3/cpu.hh5
-rw-r--r--cpu/o3/decode.hh3
-rw-r--r--cpu/o3/fetch.hh6
-rw-r--r--cpu/o3/free_list.hh2
-rw-r--r--cpu/o3/iew.hh1
-rw-r--r--cpu/o3/iew_impl.hh2
-rw-r--r--cpu/o3/ras.hh4
-rw-r--r--cpu/o3/regfile.hh290
-rw-r--r--cpu/o3/rename.hh4
-rw-r--r--cpu/o3/rename_map.hh4
-rw-r--r--cpu/o3/rob.hh2
-rw-r--r--cpu/o3/store_set.hh4
-rw-r--r--cpu/o3/tournament_pred.hh4
-rw-r--r--cpu/ozone/cpu.hh25
-rw-r--r--cpu/pc_event.cc4
-rw-r--r--cpu/pc_event.hh3
-rw-r--r--cpu/profile.hh8
-rw-r--r--cpu/simple/cpu.cc34
-rw-r--r--cpu/simple/cpu.hh20
-rw-r--r--cpu/static_inst.cc22
-rw-r--r--cpu/static_inst.hh100
-rw-r--r--cpu/trace/opt_cpu.hh2
-rw-r--r--cpu/trace/reader/itx_reader.hh3
-rw-r--r--dev/alpha_console.cc1
-rw-r--r--dev/baddev.cc1
-rw-r--r--dev/ide_ctrl.cc1
-rw-r--r--dev/ide_disk.cc1
-rw-r--r--dev/ide_disk.hh2
-rw-r--r--dev/isa_fake.cc1
-rw-r--r--dev/ns_gige.cc1
-rw-r--r--dev/pciconfigall.cc1
-rw-r--r--dev/pcidev.hh2
-rw-r--r--dev/platform.cc1
-rw-r--r--dev/platform.hh2
-rw-r--r--dev/simple_disk.hh22
-rw-r--r--dev/sinic.cc1
-rw-r--r--dev/sinicreg.hh4
-rw-r--r--dev/tsunami.cc2
-rw-r--r--dev/tsunami.hh2
-rw-r--r--dev/tsunami_cchip.cc2
-rw-r--r--dev/tsunami_io.cc2
-rw-r--r--dev/tsunami_pchip.cc2
-rw-r--r--dev/uart8250.cc1
-rw-r--r--kern/freebsd/freebsd_system.cc1
-rw-r--r--kern/kernel_stats.hh7
-rw-r--r--kern/linux/aligned.hh2
-rw-r--r--kern/linux/linux_system.cc1
-rw-r--r--kern/linux/linux_threadinfo.hh4
-rw-r--r--kern/system_events.cc2
-rw-r--r--kern/tru64/dump_mbuf.cc2
-rw-r--r--kern/tru64/mbuf.hh22
-rw-r--r--kern/tru64/tru64_events.cc2
-rw-r--r--sim/process.cc1
-rw-r--r--sim/process.hh4
-rw-r--r--sim/pseudo_inst.cc1
-rw-r--r--sim/pseudo_inst.hh4
-rw-r--r--sim/syscall_emul.cc3
-rw-r--r--sim/syscall_emul.hh7
-rw-r--r--sim/system.cc1
-rw-r--r--sim/system.hh2
-rw-r--r--sim/vptr.hh2
111 files changed, 1474 insertions, 1148 deletions
diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc
index 6d50756f2..783b189cc 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/alpha_linux_process.cc
@@ -39,6 +39,7 @@
#include "sim/syscall_emul.hh"
using namespace std;
+using namespace AlphaISA;
/// Target uname() handler.
static SyscallReturn
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index 849063f59..b39a1ef26 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -42,6 +42,7 @@ class ExecContext;
class AlphaTLB : public SimObject
{
protected:
+ typedef TheISA::Addr Addr;
typedef std::multimap<Addr, int> PageTable;
PageTable lookupTable; // Quick lookup into page table
@@ -82,6 +83,7 @@ class AlphaTLB : public SimObject
class AlphaITB : public AlphaTLB
{
protected:
+ typedef TheISA::Addr Addr;
mutable Stats::Scalar<> hits;
mutable Stats::Scalar<> misses;
mutable Stats::Scalar<> acv;
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/alpha_tru64_process.cc
index e6624305c..8121d3452 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/alpha_tru64_process.cc
@@ -37,6 +37,7 @@
#include "sim/syscall_emul.hh"
using namespace std;
+using namespace AlphaISA;
/// Target uname() handler.
static SyscallReturn
diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index a340a2053..4e8190cbc 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -31,6 +31,8 @@
#include "cpu/exec_context.hh"
#include "mem/functional/physical.hh"
+using namespace AlphaISA;
+
AlphaArguments::Data::~Data()
{
while (!data.empty()) {
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 5173b364f..7c8465cfb 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -30,9 +30,13 @@
#define __ARCH_ALPHA_EV5_HH__
#include "config/alpha_tlaser.hh"
+#include "arch/alpha/isa_traits.hh"
namespace EV5 {
+//It seems like a safe assumption EV5 only applies to alpha
+using namespace AlphaISA;
+
#if ALPHA_TLASER
const uint64_t AsnMask = ULL(0x7f);
#else
diff --git a/arch/alpha/isa/branch.isa b/arch/alpha/isa/branch.isa
index e9c790c53..cc6fd1a09 100644
--- a/arch/alpha/isa/branch.isa
+++ b/arch/alpha/isa/branch.isa
@@ -40,6 +40,8 @@ output header {{
class PCDependentDisassembly : public AlphaStaticInst
{
protected:
+ typedef TheISA::Addr Addr;
+ protected:
/// Cached program counter from last disassembly
mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly
@@ -64,6 +66,7 @@ output header {{
class Branch : public PCDependentDisassembly
{
protected:
+ typedef TheISA::Addr Addr;
/// Displacement to target address (signed).
int32_t disp;
@@ -87,6 +90,7 @@ output header {{
class Jump : public PCDependentDisassembly
{
protected:
+ typedef TheISA::Addr Addr;
/// Displacement to target address (signed).
int32_t disp;
@@ -205,8 +209,8 @@ output decoder {{
def template JumpOrBranchDecode {{
return (RA == 31)
- ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
- : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
+ ? (StaticInst *)new %(class_name)s(machInst)
+ : (StaticInst *)new %(class_name)sAndLink(machInst);
}};
def format CondBranch(code) {{
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index 42fb29404..862b2b95e 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -45,6 +45,8 @@ output decoder {{
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include <math.h>
+
+using namespace AlphaISA;
}};
output exec {{
@@ -58,6 +60,8 @@ output exec {{
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
+
+using namespace AlphaISA;
}};
////////////////////////////////////////////////////////////////////
@@ -179,7 +183,7 @@ output header {{
/**
* Base class for all Alpha static instructions.
*/
- class AlphaStaticInst : public StaticInst<AlphaISA>
+ class AlphaStaticInst : public StaticInst
{
protected:
@@ -196,7 +200,7 @@ output header {{
/// Constructor.
AlphaStaticInst(const char *mnem, MachInst _machInst,
OpClass __opClass)
- : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
+ : StaticInst(mnem, _machInst, __opClass)
{
}
@@ -352,6 +356,17 @@ output header {{
%(BasicExecDeclare)s
};
+
+ /// Helper function for decoding nops. Substitute Nop object
+ /// for original inst passed in as arg (and delete latter).
+ static inline
+ AlphaStaticInst *
+ makeNop(AlphaStaticInst *inst)
+ {
+ AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+ delete inst;
+ return nop;
+ }
}};
output decoder {{
@@ -364,17 +379,6 @@ output decoder {{
return csprintf("%-10s (%s)", "nop", originalDisassembly);
#endif
}
-
- /// Helper function for decoding nops. Substitute Nop object
- /// for original inst passed in as arg (and delete latter).
- inline
- AlphaStaticInst *
- makeNop(AlphaStaticInst *inst)
- {
- AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
- delete inst;
- return nop;
- }
}};
output exec {{
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index df26a534d..33b7341ef 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -37,14 +37,14 @@ output header {{
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
/// Pointer to EAComp object.
- const StaticInstPtr<AlphaISA> eaCompPtr;
+ const StaticInstPtr eaCompPtr;
/// Pointer to MemAcc object.
- const StaticInstPtr<AlphaISA> memAccPtr;
+ const StaticInstPtr memAccPtr;
/// Constructor
Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+ StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+ StaticInstPtr _memAccPtr = nullStaticInstPtr)
: AlphaStaticInst(mnem, _machInst, __opClass),
memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
{
@@ -55,8 +55,8 @@ output header {{
public:
- const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
- const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
+ const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
+ const StaticInstPtr &memAccInst() const { return memAccPtr; }
};
/**
@@ -71,8 +71,8 @@ output header {{
/// Constructor.
MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+ StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+ StaticInstPtr _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
disp(MEMDISP)
{
@@ -90,8 +90,8 @@ output header {{
protected:
/// Constructor
MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+ StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+ StaticInstPtr _memAccPtr = nullStaticInstPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
{
}
diff --git a/arch/alpha/isa/pal.isa b/arch/alpha/isa/pal.isa
index b68a7c19f..49e5bff12 100644
--- a/arch/alpha/isa/pal.isa
+++ b/arch/alpha/isa/pal.isa
@@ -149,8 +149,8 @@ output header {{
/// Constructor
HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
+ StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+ StaticInstPtr _memAccPtr = nullStaticInstPtr);
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -162,8 +162,8 @@ output decoder {{
inline
HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
OpClass __opClass,
- StaticInstPtr<AlphaISA> _eaCompPtr,
- StaticInstPtr<AlphaISA> _memAccPtr)
+ StaticInstPtr _eaCompPtr,
+ StaticInstPtr _memAccPtr)
: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
disp(HW_LDST_DISP)
{
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index a6e34acbb..2da37b2e0 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -44,17 +44,16 @@ class Checkpoint;
#define TARGET_ALPHA
-template <class ISA> class StaticInst;
-template <class ISA> class StaticInstPtr;
+class StaticInst;
+class StaticInstPtr;
namespace EV5 {
int DTB_ASN_ASN(uint64_t reg);
int ITB_ASN_ASN(uint64_t reg);
}
-class AlphaISA
+namespace AlphaISA
{
- public:
typedef uint32_t MachInst;
typedef uint64_t Addr;
@@ -133,10 +132,10 @@ class AlphaISA
Addr lock_addr; // lock address for LL/SC
} MiscRegFile;
-static const Addr PageShift = 13;
-static const Addr PageBytes = ULL(1) << PageShift;
-static const Addr PageMask = ~(PageBytes - 1);
-static const Addr PageOffset = PageBytes - 1;
+extern const Addr PageShift;
+extern const Addr PageBytes;
+extern const Addr PageMask;
+extern const Addr PageOffset;
#if FULL_SYSTEM
@@ -184,10 +183,10 @@ static const Addr PageOffset = PageBytes - 1;
void unserialize(Checkpoint *cp, const std::string &section);
};
- static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+ StaticInstPtr decodeInst(MachInst);
// return a no-op instruction... used for instruction fetch faults
- static const MachInst NoopMachInst;
+ extern const MachInst NoopMachInst;
enum annotes {
ANNOTE_NONE = 0,
@@ -242,10 +241,10 @@ static const Addr PageOffset = PageBytes - 1;
// Machine operations
- static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
+ void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
int regnum);
- static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
+ void restoreMachineReg(RegFile &regs, const AnyReg &reg,
int regnum);
#if 0
@@ -263,41 +262,41 @@ static const Addr PageOffset = PageBytes - 1;
* @param xc The execution context.
*/
template <class XC>
- static void zeroRegisters(XC *xc);
+ void zeroRegisters(XC *xc);
+
+
+//typedef AlphaISA TheISA;
+
+//typedef TheISA::MachInst MachInst;
+//typedef TheISA::Addr Addr;
+//typedef TheISA::RegIndex RegIndex;
+//typedef TheISA::IntReg IntReg;
+//typedef TheISA::IntRegFile IntRegFile;
+//typedef TheISA::FloatReg FloatReg;
+//typedef TheISA::FloatRegFile FloatRegFile;
+//typedef TheISA::MiscReg MiscReg;
+//typedef TheISA::MiscRegFile MiscRegFile;
+//typedef TheISA::AnyReg AnyReg;
+//typedef TheISA::RegFile RegFile;
+
+//const int NumIntRegs = TheISA::NumIntRegs;
+//const int NumFloatRegs = TheISA::NumFloatRegs;
+//const int NumMiscRegs = TheISA::NumMiscRegs;
+//const int TotalNumRegs = TheISA::TotalNumRegs;
+//const int VMPageSize = TheISA::VMPageSize;
+//const int LogVMPageSize = TheISA::LogVMPageSize;
+//const int ZeroReg = TheISA::ZeroReg;
+//const int StackPointerReg = TheISA::StackPointerReg;
+//const int GlobalPointerReg = TheISA::GlobalPointerReg;
+//const int ReturnAddressReg = TheISA::ReturnAddressReg;
+//const int ReturnValueReg = TheISA::ReturnValueReg;
+//const int ArgumentReg0 = TheISA::ArgumentReg0;
+//const int ArgumentReg1 = TheISA::ArgumentReg1;
+//const int ArgumentReg2 = TheISA::ArgumentReg2;
+//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const Addr MaxAddr = (Addr)-1;
};
-
-typedef AlphaISA TheISA;
-
-typedef TheISA::MachInst MachInst;
-typedef TheISA::Addr Addr;
-typedef TheISA::RegIndex RegIndex;
-typedef TheISA::IntReg IntReg;
-typedef TheISA::IntRegFile IntRegFile;
-typedef TheISA::FloatReg FloatReg;
-typedef TheISA::FloatRegFile FloatRegFile;
-typedef TheISA::MiscReg MiscReg;
-typedef TheISA::MiscRegFile MiscRegFile;
-typedef TheISA::AnyReg AnyReg;
-typedef TheISA::RegFile RegFile;
-
-const int NumIntRegs = TheISA::NumIntRegs;
-const int NumFloatRegs = TheISA::NumFloatRegs;
-const int NumMiscRegs = TheISA::NumMiscRegs;
-const int TotalNumRegs = TheISA::TotalNumRegs;
-const int VMPageSize = TheISA::VMPageSize;
-const int LogVMPageSize = TheISA::LogVMPageSize;
-const int ZeroReg = TheISA::ZeroReg;
-const int StackPointerReg = TheISA::StackPointerReg;
-const int GlobalPointerReg = TheISA::GlobalPointerReg;
-const int ReturnAddressReg = TheISA::ReturnAddressReg;
-const int ReturnValueReg = TheISA::ReturnValueReg;
-const int ArgumentReg0 = TheISA::ArgumentReg0;
-const int ArgumentReg1 = TheISA::ArgumentReg1;
-const int ArgumentReg2 = TheISA::ArgumentReg2;
-const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
-const int MaxAddr = (Addr)-1;
-
#if !FULL_SYSTEM
class SyscallReturn {
public:
@@ -336,9 +335,9 @@ class SyscallReturn {
#if FULL_SYSTEM
-typedef TheISA::InternalProcReg InternalProcReg;
-const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
-const int NumInterruptLevels = TheISA::NumInterruptLevels;
+//typedef TheISA::InternalProcReg InternalProcReg;
+//const int NumInternalProcRegs = TheISA::NumInternalProcRegs;
+//const int NumInterruptLevels = TheISA::NumInterruptLevels;
#include "arch/alpha/ev5.hh"
#endif
diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc
index 5a8df3d35..30ed07d9d 100644
--- a/arch/alpha/stacktrace.cc
+++ b/arch/alpha/stacktrace.cc
@@ -37,6 +37,7 @@
#include "cpu/exec_context.hh"
using namespace std;
+using namespace AlphaISA;
ProcessInfo::ProcessInfo(ExecContext *_xc)
: xc(_xc)
@@ -108,7 +109,7 @@ StackTrace::StackTrace()
{
}
-StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr<TheISA> inst)
+StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
: xc(0), stack(64)
{
trace(_xc, inst);
diff --git a/arch/alpha/stacktrace.hh b/arch/alpha/stacktrace.hh
index 244e574b6..211909060 100644
--- a/arch/alpha/stacktrace.hh
+++ b/arch/alpha/stacktrace.hh
@@ -37,6 +37,8 @@ class StackTrace;
class ProcessInfo
{
+ protected:
+ typedef TheISA::Addr Addr;
private:
ExecContext *xc;
@@ -56,6 +58,9 @@ class ProcessInfo
class StackTrace
{
+ protected:
+ typedef TheISA::Addr Addr;
+ typedef TheISA::MachInst MachInst;
private:
ExecContext *xc;
std::vector<Addr> stack;
@@ -70,7 +75,7 @@ class StackTrace
public:
StackTrace();
- StackTrace(ExecContext *xc, StaticInstPtr<TheISA> inst);
+ StackTrace(ExecContext *xc, StaticInstPtr inst);
~StackTrace();
void clear()
@@ -80,7 +85,7 @@ class StackTrace
}
bool valid() const { return xc != NULL; }
- bool trace(ExecContext *xc, StaticInstPtr<TheISA> inst);
+ bool trace(ExecContext *xc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@@ -102,7 +107,7 @@ class StackTrace
};
inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr<TheISA> inst)
+StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 27014164c..3ffa4bd14 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -34,6 +34,7 @@
#include "mem/functional/physical.hh"
using namespace std;
+using namespace AlphaISA;
AlphaISA::PageTableEntry
kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
diff --git a/arch/alpha/vtophys.hh b/arch/alpha/vtophys.hh
index 95430ce77..988f050ba 100644
--- a/arch/alpha/vtophys.hh
+++ b/arch/alpha/vtophys.hh
@@ -35,16 +35,16 @@ class ExecContext;
class PhysicalMemory;
AlphaISA::PageTableEntry
-kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
+kernel_pte_lookup(PhysicalMemory *pmem, AlphaISA::Addr ptbr, AlphaISA::VAddr vaddr);
-Addr vtophys(PhysicalMemory *xc, Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
-uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
-uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len);
+AlphaISA::Addr vtophys(PhysicalMemory *xc, AlphaISA::Addr vaddr);
+AlphaISA::Addr vtophys(ExecContext *xc, AlphaISA::Addr vaddr);
+uint8_t *vtomem(ExecContext *xc, AlphaISA::Addr vaddr, size_t len);
+uint8_t *ptomem(ExecContext *xc, AlphaISA::Addr paddr, size_t len);
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
+void CopyOut(ExecContext *xc, void *dst, AlphaISA::Addr src, size_t len);
+void CopyIn(ExecContext *xc, AlphaISA::Addr dst, void *src, size_t len);
+void CopyString(ExecContext *xc, char *dst, AlphaISA::Addr vaddr, size_t maxlen);
#endif // __ARCH_ALPHA_VTOPHYS_H__
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index bcef77ddf..b92d267c9 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -224,7 +224,7 @@ def p_specification(t):
namespace = isa_name + "Inst"
# wrap the decode block as a function definition
t[4].wrap_decode_block('''
-StaticInstPtr<%(isa_name)s>
+StaticInstPtr
%(isa_name)s::decodeInst(%(isa_name)s::MachInst machInst)
{
using namespace %(namespace)s;
@@ -1351,6 +1351,7 @@ class MemOperand(Operand):
def makeAccSize(self):
return self.size
+
class NPCOperand(Operand):
def makeConstructor(self):
return ''
@@ -1361,6 +1362,15 @@ class NPCOperand(Operand):
def makeWrite(self):
return 'xc->setNextPC(%s);\n' % self.base_name
+class NNPCOperand(Operand):
+ def makeConstructor(self):
+ return ''
+
+ def makeRead(self):
+ return '%s = xc->readPC() + 8;\n' % self.base_name
+
+ def makeWrite(self):
+ return 'xc->setNextNPC(%s);\n' % self.base_name
def buildOperandNameMap(userDict, lineno):
global operandNameMap
@@ -1686,6 +1696,8 @@ namespace %(namespace)s {
%(namespace_output)s
} // namespace %(namespace)s
+
+%(decode_function)s
'''
@@ -1765,13 +1777,15 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
includes = '#include "base/bitfield.hh" // for bitfield support'
global_output = global_code.header_output
namespace_output = namespace_code.header_output
+ decode_function = ''
update_if_needed(output_dir + '/decoder.hh', file_template % vars())
# generate decoder.cc
includes = '#include "%s/decoder.hh"' % include_path
global_output = global_code.decoder_output
namespace_output = namespace_code.decoder_output
- namespace_output += namespace_code.decode_block
+ # namespace_output += namespace_code.decode_block
+ decode_function = namespace_code.decode_block
update_if_needed(output_dir + '/decoder.cc', file_template % vars())
# generate per-cpu exec files
@@ -1780,6 +1794,7 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
includes += cpu.includes
global_output = global_code.exec_output[cpu.name]
namespace_output = namespace_code.exec_output[cpu.name]
+ decode_function = ''
update_if_needed(output_dir + '/' + cpu.filename,
file_template % vars())
diff --git a/arch/isa_specific.hh b/arch/isa_specific.hh
new file mode 100644
index 000000000..e11e6c292
--- /dev/null
+++ b/arch/isa_specific.hh
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ISA_SPECIFIC_HH__
+#define __ARCH_ISA_SPECIFIC_HH__
+
+//This file provides a mechanism for other source code to bring in
+//files from the ISA being compiled with
+
+//These are constants so you can selective compile code based on the isa
+//To use them, do something like
+//
+//#if THE_ISA == YOUR_FAVORITE_ISA
+// conditional_code
+//#endif
+//
+//Note that this is how this file sets up the other isa "hooks"
+
+//These macros have numerical values because otherwise the preprocessor
+//would treat them as 0 in comparisons.
+#define ALPHA_ISA 21064
+#define SPARC_ISA 42
+#define MIPS_ISA 1337
+
+//These tell the preprocessor where to find the files of a particular
+//ISA, and set the "TheISA" macro for use elsewhere.
+#if THE_ISA == ALPHA_ISA
+ #define ISA_PATH arch/alpha/
+ #define TheISA AlphaISA
+#elif THE_ISA == SPARC_ISA
+ #define ISA_PATH arch/sparc/
+ #define TheISA SparcISA
+#elif THE_ISA == MIPS_ISA
+ #define ISA_PATH arch/mips/
+ #define TheISA MipsISA
+#else
+ #error "THE_ISA not set"
+#endif
+//The following is some preprocessor voodoo to allow redirectable includes
+//The end result is the ISA_INCLUDE() macro which is used inside stub
+//include files in arch and which redirect to the isa in use.
+#define STRINGIFY(token) #token
+#define EXPAND(token) token
+#define STICK_TOGETHER(firstpart, secondpart) \
+ EXPAND(firstpart)EXPAND(secondpart)
+#define EXPAND_AND_STRINGIFY(pathAndFile) \
+ STRINGIFY(pathAndFile)
+#define ISA_INCLUDE(filename) \
+ EXPAND_AND_STRINGIFY(STICK_TOGETHER(ISA_PATH, filename))
+
+#endif
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
new file mode 100644
index 000000000..db37cf49c
--- /dev/null
+++ b/arch/mips/isa/base.isa
@@ -0,0 +1,63 @@
+// -*- mode:c++ -*-
+
+////////////////////////////////////////////////////////////////////
+//
+// Base class for MIPS instructions, and some support functions
+//
+
+//Outputs to decoder.hh
+output header {{
+ /**
+ * Base class for all SPARC static instructions.
+ */
+ class MipsStaticInst : public StaticInst<MIPSISA>
+ {
+ protected:
+
+ // Constructor.
+ MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : StaticInst<MIPSISA>(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+}};
+
+//Ouputs to decoder.cc
+output decoder {{
+
+ std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // just print the first two source regs... if there's
+ // a third one, it's a read-modify-write dest (Rc),
+ // e.g. for CMOVxx
+ if(_numSrcRegs > 0)
+ {
+ printReg(ss, _srcRegIdx[0]);
+ }
+ if(_numSrcRegs > 1)
+ {
+ ss << ",";
+ printReg(ss, _srcRegIdx[1]);
+ }
+
+ // just print the first dest... if there's a second one,
+ // it's generally implicit
+ if(_numDestRegs > 0)
+ {
+ if(_numSrcRegs > 0)
+ ss << ",";
+ printReg(ss, _destRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
+}};
+
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 6bb5bf4d8..f46024f15 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
////////////////////////////////////////////////////////////////////
//
// The actual MIPS32 ISA decoder
@@ -12,183 +14,194 @@
decode OPCODE_HI default Unknown::unknown() {
// Derived From ... Table A-2 MIPS32 ISA Manual
- 0x0: decode OPCODE_LO default FailUnimpl::reserved(){
+ 0x0: decode OPCODE_LO {
0x0: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
- 0x1: decode MOVCI {
- format BasicOp {
- 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
- 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
+ 0x1: decode MOVCI {
+ format BasicOp {
+ 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
+ 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
+ }
}
- }
- format BasicOp {
+ format BasicOp {
- //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
- //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
+ //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
+ //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
- 0x0: sll({{ Rd = Rt.uw << SA; }});
+ 0x0: sll({{ Rd = Rt.uw << SA; }});
- 0x2: decode SRL {
- 0: srl({{ Rd = Rt.uw >> SA; }});
+ 0x2: decode SRL {
+ 0: srl({{ Rd = Rt.uw >> SA; }});
- //Hardcoded assuming 32-bit ISA, probably need parameter here
- 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
- }
+ //Hardcoded assuming 32-bit ISA, probably need parameter here
+ 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
+ }
- 0x3: sra({{ Rd = Rt.sw >> SA; }});
+ 0x3: sra({{ Rd = Rt.sw >> SA; }});
- 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
+ 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
- 0x6: decode SRLV {
- 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
+ 0x6: decode SRLV {
+ 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
- //Hardcoded assuming 32-bit ISA, probably need parameter here
- 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
- }
+ //Hardcoded assuming 32-bit ISA, probably need parameter here
+ 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
+ }
- 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
- }
+ 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
+ }
}
0x1: decode FUNCTION_LO {
- //Table A-3 Note: "Specific encodings of the hint field are used
- //to distinguish JR from JR.HB and JALR from JALR.HB"
- format Jump {
- 0x0: jr(IsReturn);
- 0x1: jalr(IsCall,IsReturn);
- }
+ //Table A-3 Note: "Specific encodings of the hint field are used
+ //to distinguish JR from JR.HB and JALR from JALR.HB"
+ format Unconditional {
+ 0x0: decode HINT {
+ 0:jr({{ }},IsReturn,IsLink);
+ 1:jr_hb({{ }},IsReturn,IsLink);
+ }
+
+ 0x1: decode HINT {
+ 0: jalr({{ }},'IsCall','IsReturn','IsLink');
+ 1: jalr_hb({{ }},IsCall,IsReturn,IsLink);
+ }
+ }
- format BasicOp {
- 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
- 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
- }
+ format BasicOp {
+ 0x2: movz({{ if (Rt == 0) Rd = Rs; }});
+ 0x3: movn({{ if (Rt != 0) Rd = Rs; }});
+ }
- format WarnUnimpl {
- 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
- 0x5: break();
- 0x7: sync();
- }
+ format WarnUnimpl {
+ 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative
+ 0x5: break();
+ 0x7: sync();
+ }
}
0x2: decode FUNCTION_LO {
- format BasicOp {
- 0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
- 0x1: mthi({{ xc->miscRegs.hi = Rs; }});
- 0x2: mflo({{ Rd = xc->miscRegs.lo; }});
- 0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
- }
+ format BasicOp {
+ 0x0: mfhi({{ Rd = xc->miscRegs.hi; }});
+ 0x1: mthi({{ xc->miscRegs.hi = Rs; }});
+ 0x2: mflo({{ Rd = xc->miscRegs.lo; }});
+ 0x3: mtlo({{ xc->miscRegs.lo = Rs; }});
+ }
}
0x3: decode FUNCTION_LO {
- format IntOp {
- 0x0: mult({{
+ format IntOp {
+ 0x0: mult({{
INT64 temp1 = Rs.sw * Rt.sw;
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>;
- }});
+ }});
- 0x1: multu({{
+ 0x1: multu({{
INT64 temp1 = Rs.uw * Rt.uw;
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
- Rd.sw = Rs.uw * Rt.uw;
- }});
+ Rd.sw = Rs.uw * Rt.uw;
+ }});
- 0x2: div({{
+ 0x2: div({{
xc->miscRegs.hi = Rs.sw % Rt.sw;
xc->miscRegs.lo = Rs.sw / Rt.sw;
- }});
+ }});
- 0x3: divu({{
+ 0x3: divu({{
xc->miscRegs.hi = Rs.uw % Rt.uw;
xc->miscRegs.lo = Rs.uw / Rt.uw;
- }});
- }
+ }});
+ }
}
0x4: decode FUNCTION_LO {
- format IntOp {
- 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
- 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
- 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
- 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
- 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
- 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
- 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
- 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
- }
+ format IntOp {
+ 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
+ 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
+ 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
+ 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
+ 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
+ 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
+ 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
+ 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
+ }
}
0x5: decode FUNCTION_LO {
- format IntOp{
- 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
- 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
- }
+ format IntOp{
+ 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
+ 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+ }
}
0x6: decode FUNCTION_LO {
- format Trap {
- 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
- 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
- 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
- 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
- 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
- 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
- }
+ format Trap {
+ 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
+ 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
+ 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
+ 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
+ 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
+ }
}
}
0x1: decode REGIMM_HI {
0x0: decode REGIMM_LO {
- format CondBranch {
- 0x0: bltz({{ cond = (Rs.sw < 0); }});
- 0x1: bgez({{ cond = (Rs.sw >= 0); }});
-
- //MIPS obsolete instructions
- 0x2: bltzl({{ cond = (Rs.sw < 0); }});
- 0x3: bgezl({{ cond = (Rs.sw >= 0); }});
- }
+ format Branch {
+ 0x0: bltz({{ cond = (Rs.sw < 0); }});
+ 0x1: bgez({{ cond = (Rs.sw >= 0); }});
+ }
+
+ format BranchLikely {
+ //MIPS obsolete instructions
+ 0x2: bltzl({{ cond = (Rs.sw < 0); }});
+ 0x3: bgezl({{ cond = (Rs.sw >= 0); }});
+ }
}
0x1: decode REGIMM_LO {
- format Trap {
- 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }});
- 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }});
- 0x2: tlti({{ cond = (Rs.sw < INTIMM); }});
- 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
- 0x4: teqi({{ cond = (Rs.sw == INTIMM); }});
- 0x6: tnei({{ cond = (Rs.sw != INTIMM); }});
- }
+ format Trap {
+ 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
+ 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
+ 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
+ 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
+ 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
+ 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
+ }
}
0x2: decode REGIMM_LO {
- format CondBranch {
- 0x0: bltzal({{ cond = (Rs.sw < 0); }});
- 0x1: bgezal({{ cond = (Rs.sw >= 0); }});
-
- //MIPS obsolete instructions
- 0x2: bltzall({{ cond = (Rs.sw < 0); }});
- 0x3: bgezall({{ cond = (Rs.sw >= 0); }});
- }
+ format Branch {
+ 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink);
+ 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink);
+ }
+
+ format BranchLikely {
+ //Will be removed in future MIPS releases
+ 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink);
+ 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink);
+ }
}
0x3: decode REGIMM_LO {
- format WarnUnimpl {
- 0x7: synci();
- }
+ format WarnUnimpl {
+ 0x7: synci();
+ }
}
}
- format Jump {
- 0x2: j();
- 0x3: jal(IsCall);
+ format Unconditional {
+ 0x2: j({{ }});
+ 0x3: jal({{ }},IsCall,IsLink);
}
- format CondBranch {
+ format Branch {
0x4: beq({{ cond = (Rs.sw == 0); }});
0x5: bne({{ cond = (Rs.sw != 0); }});
0x6: blez({{ cond = (Rs.sw <= 0); }});
@@ -196,7 +209,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
- 0x1: decode OPCODE_LO default FailUnimpl::reserved(){
+ 0x1: decode OPCODE_LO {
format IntOp {
0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
@@ -209,539 +222,534 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
- 0x2: decode OPCODE_LO default FailUnimpl::reserved(){
-
- //Table A-11 MIPS32 COP0 Encoding of rs Field
- 0x0: decode RS_MSB {
- 0x0: decode RS {
+ 0x2: decode OPCODE_LO {
- format BasicOp {
- 0x0: mfc0({{
+ //Table A-11 MIPS32 COP0 Encoding of rs Field
+ 0x0: decode RS_MSB {
+ 0x0: decode RS {
+ format BasicOp {
+ 0x0: mfc0({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
//sel field. In those instances, the sel field must be zero.
if (SEL > 0)
- panic("Can't Handle Cop0 with register select yet\n");
+ panic("Can't Handle Cop0 with register select yet\n");
uint64_t reg_num = Rd.uw;
Rt = xc->miscRegs.cop0[reg_num];
- }});
+ }});
- 0x4: mtc0({{
+ 0x4: mtc0({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
//sel field. In those instances, the sel field must be zero.
if (SEL > 0)
- panic("Can't Handle Cop0 with register select yet\n");
+ panic("Can't Handle Cop0 with register select yet\n");
uint64_t reg_num = Rd.uw;
xc->miscRegs.cop0[reg_num] = Rt;
- }});
+ }});
- 0x8: mftr({{
+ 0x8: mftr({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
//sel field. In those instances, the sel field must be zero.
//MT Code Needed Here
- }});
+ }});
- 0xC: mttr({{
+ 0xC: mttr({{
//The contents of the coprocessor 0 register specified by the
//combination of rd and sel are loaded into general register
//rt. Note that not all coprocessor 0 registers support the
//sel field. In those instances, the sel field must be zero.
//MT Code Needed Here
- }});
+ }});
- 0xA: rdpgpr({{
+ 0xA: rdpgpr({{
//Accessing Previous Shadow Set Register Number
uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
uint64_t reg_num = Rt.uw;
Rd = xc->shadowIntRegFile[prev][reg_num];
- }});
- }
+ }});
- 0xB: decode RD {
+ 0xB: decode RD {
- 0x0: decode SC {
- format BasicOp {
- 0x0: dvpe({{
- Rt.sw = xc->miscRegs.cop0.MVPControl;
- xc->miscRegs.cop0.MVPControl[EVP] = 0;
- }});
+ 0x0: decode SC {
+ 0x0: dvpe({{
+ Rt.sw = xc->miscRegs.cop0.MVPControl;
+ xc->miscRegs.cop0.MVPControl[EVP] = 0;
+ }});
- 0x1: evpe({{
- Rt.sw = xc->miscRegs.cop0.MVPControl;
- xc->miscRegs.cop0.MVPControl[EVP] = 1;
- }});
- }
- }
+ 0x1: evpe({{
+ Rt.sw = xc->miscRegs.cop0.MVPControl;
+ xc->miscRegs.cop0.MVPControl[EVP] = 1;
+ }});
+ }
- 0x1: decode SC {
- format BasicOp {
- 0x0: dmt({{
- Rt.sw = xc->miscRegs.cop0.VPEControl;
- xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
- }});
+ 0x1: decode SC {
+ 0x0: dmt({{
+ Rt.sw = xc->miscRegs.cop0.VPEControl;
+ xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0;
+ }});
- 0x1: emt({{
- Rt.sw = xc->miscRegs.cop0.VPEControl;
- xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
- }});
- }
- }
+ 0x1: emt({{
+ Rt.sw = xc->miscRegs.cop0.VPEControl;
+ xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1;
+ }});
+ }
- 0xC: decode SC {
- format BasicOp {
- 0x0: di({{
- Rt.sw = xc->miscRegs.cop0.Status;
- xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
- }});
+ 0xC: decode SC {
+ 0x0: di({{
+ Rt.sw = xc->miscRegs.cop0.Status;
+ xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0;
+ }});
- 0x1: ei({{
- Rt.sw = xc->miscRegs.cop0.Status;
- xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
- }});
- }
- }
- }
+ 0x1: ei({{
+ Rt.sw = xc->miscRegs.cop0.Status;
+ xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1;
+ }});
+ }
+ }
- 0xE: BasicOp::wrpgpr({{
+ 0xE: wrpgpr({{
//Accessing Previous Shadow Set Register Number
uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS];
uint64_t reg_num = Rd.uw;
xc->shadowIntRegFile[prev][reg_num] = Rt;
- }});
- }
-
- //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
- 0x1: decode FUNCTION {
- format Trap {
- 0x01: tlbr({{ }});
- 0x02: tlbwi({{ }});
- 0x06: tlbwr({{ }});
- 0x08: tlbp({{ }});
- }
-
- format WarnUnimpl {
- 0x18: eret();
- 0x1F: deret();
- 0x20: wait();
- }
- }
- }
-
- //Table A-13 MIPS32 COP1 Encoding of rs Field
- 0x1: decode RS_MSB {
-
- 0x0: decode RS_HI {
- 0x0: decode RS_LO {
- format FloatOp {
- 0x0: mfc1({{ Rt = Fs<31:0>; }});
- 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}});
- 0x3: mfhc1({{ Rt = Fs<63:32>;}});
- 0x4: mtc1({{ Fs<31:0> = Rt}});
- 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}});
- 0x7: mftc1({{ Fs<63:32> = Rt}});
- }
- }
-
- 0x1: decode ND {
- 0x0: decode TF {
- format CondBranch {
- 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
- 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
- }
+ }});
+ }
}
- 0x1: decode TF {
- format CondBranch {
- 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
- 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
- }
+ //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
+ 0x1: decode FUNCTION {
+ format Trap {
+ 0x01: tlbr({{ }});
+ 0x02: tlbwi({{ }});
+ 0x06: tlbwr({{ }});
+ 0x08: tlbp({{ }});
+ }
+
+ format WarnUnimpl {
+ 0x18: eret();
+ 0x1F: deret();
+ 0x20: wait();
+ }
}
- }
}
- 0x1: decode RS_HI {
- 0x2: decode RS_LO {
+ //Table A-13 MIPS32 COP1 Encoding of rs Field
+ 0x1: decode RS_MSB {
- //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
- //(( single-word ))
0x0: decode RS_HI {
- 0x0: decode RS_LO {
- format FloatOp {
- 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
- 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
- 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
- 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
- 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
- 0x5: abss({{ Fd.sf = abs(Fs.sf);}});
- 0x6: movs({{ Fd.sf = Fs.sf;}});
- 0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
- }
- }
-
- 0x1: decode RS_LO {
- //only legal for 64 bit-FP
- format Float64Op {
- 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
- 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
- 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
- 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
- }
-
- format FloatOp {
- 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
- 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
- 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
- 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
- }
- }
-
- 0x2: decode RS_LO {
- 0x1: decode MOVCF {
- format FloatOp {
- 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }});
- 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}});
- }
+ 0x0: decode RS_LO {
+ format FloatOp {
+ 0x0: mfc1({{ Rt = Fs<31:0>; }});
+ 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}});
+ 0x3: mfhc1({{ Rt = Fs<63:32>;}});
+ 0x4: mtc1({{ Fs<31:0> = Rt}});
+ 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}});
+ 0x7: mftc1({{ Fs<63:32> = Rt}});
+ }
}
- format BasicOp {
- 0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
- 0x3: movns({{ if (Rt != 0) Fd = Fs; }});
- }
+ 0x1: decode ND {
+ 0x0: decode TF {
+ format Branch {
+ 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
+ 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
+ }
+ }
- format Float64Op {
- 0x2: recips({{ Fd = 1 / Fs; }});
- 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
+ 0x1: decode TF {
+ format BranchLikely {
+ 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
+ 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
+ }
+ }
}
- }
+ }
+
+ 0x1: decode RS_HI {
+ 0x2: decode RS_LO {
+
+ //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
+ //(( single-word ))
+ 0x0: decode RS_HI {
+ 0x0: decode RS_LO {
+ format FloatOp {
+ 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}});
+ 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}});
+ 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}});
+ 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}});
+ 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}});
+ 0x5: abss({{ Fd.sf = abs(Fs.sf);}});
+ 0x6: movs({{ Fd.sf = Fs.sf;}});
+ 0x7: negs({{ Fd.sf = -1 * Fs.sf;}});
+ }
+ }
+
+ 0x1: decode RS_LO {
+ //only legal for 64 bit-FP
+ format Float64Op {
+ 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}});
+ 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}});
+ 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}});
+ 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}});
+ }
+
+ format FloatOp {
+ 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}});
+ 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}});
+ 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}});
+ 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}});
+ }
+ }
- 0x4: decode RS_LO {
+ 0x2: decode RS_LO {
+ 0x1: decode MOVCF {
+ format FloatOp {
+ 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }});
+ 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}});
+ }
+ }
+
+ format BasicOp {
+ 0x2: movzs({{ if (Rt == 0) Fd = Fs; }});
+ 0x3: movns({{ if (Rt != 0) Fd = Fs; }});
+ }
+
+ format Float64Op {
+ 0x2: recips({{ Fd = 1 / Fs; }});
+ 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}});
+ }
+ }
+
+ 0x4: decode RS_LO {
- format FloatOp {
- 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ format FloatOp {
+ 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
- }});
+ }});
- 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
- }});
- }
+ }});
+ }
- //only legal for 64 bit
- format Float64Op {
- 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr;
+ //only legal for 64 bit
+ format Float64Op {
+ 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
- }});
-
- 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }});
- }
- }
- }
+ }});
- //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
- 0x1: decode RS_HI {
- 0x0: decode RS_LO {
- format FloatOp {
- 0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
- 0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
- 0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
- 0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
- 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
- 0x5: absd({{ Fd.df = abs(Fs.df);}});
- 0x6: movd({{ Fd.df = Fs.df;}});
- 0x7: negd({{ Fd.df = -1 * Fs.df;}});
- }
- }
-
- 0x1: decode RS_LO {
- //only legal for 64 bit
- format Float64Op {
- 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
- 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
- 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
- 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
- }
-
- format FloatOp {
- 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
- 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
- 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
- 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
- }
- }
-
- 0x2: decode RS_LO {
- 0x1: decode MOVCF {
- format FloatOp {
- 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }});
- 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }});
- }
- }
+ 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }});
+ }
+ }
+ }
+
+ //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
+ 0x1: decode RS_HI {
+ 0x0: decode RS_LO {
+ format FloatOp {
+ 0x0: addd({{ Fd.df = Fs.df + Ft.df;}});
+ 0x1: subd({{ Fd.df = Fs.df - Ft.df;}});
+ 0x2: muld({{ Fd.df = Fs.df * Ft.df;}});
+ 0x3: divd({{ Fd.df = Fs.df / Ft.df;}});
+ 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}});
+ 0x5: absd({{ Fd.df = abs(Fs.df);}});
+ 0x6: movd({{ Fd.df = Fs.df;}});
+ 0x7: negd({{ Fd.df = -1 * Fs.df;}});
+ }
+ }
- format BasicOp {
- 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }});
- 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
- }
+ 0x1: decode RS_LO {
+ //only legal for 64 bit
+ format Float64Op {
+ 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+ 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}});
+ 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}});
+ 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}});
+ }
+
+ format FloatOp {
+ 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }});
+ 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }});
+ 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }});
+ 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }});
+ }
+ }
- format Float64Op {
- 0x5: recipd({{ Fd.df = 1 / Fs.df}});
- 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
- }
- }
+ 0x2: decode RS_LO {
+ 0x1: decode MOVCF {
+ format FloatOp {
+ 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }});
+ 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }});
+ }
+ }
+
+ format BasicOp {
+ 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }});
+ 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }});
+ }
+
+ format Float64Op {
+ 0x5: recipd({{ Fd.df = 1 / Fs.df}});
+ 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }});
+ }
+ }
- 0x4: decode RS_LO {
- format FloatOp {
- 0x0: cvt_s_d({{
- int rnd_mode = xc->miscRegs.fcsr;
- Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
- }});
+ 0x4: decode RS_LO {
+ format FloatOp {
+ 0x0: cvt_s_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE);
+ }});
- 0x4: cvt_w_d({{
- int rnd_mode = xc->miscRegs.fcsr;
- Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
- }});
- }
+ 0x4: cvt_w_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE);
+ }});
+ }
- //only legal for 64 bit
- format Float64Op {
- 0x5: cvt_l_d({{
- int rnd_mode = xc->miscRegs.fcsr;
- Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
- }});
- }
- }
- }
+ //only legal for 64 bit
+ format Float64Op {
+ 0x5: cvt_l_d({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE);
+ }});
+ }
+ }
+ }
- //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
- 0x4: decode FUNCTION {
- format FloatOp {
- 0x10: cvt_s({{
+ //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
+ 0x4: decode FUNCTION {
+ format FloatOp {
+ 0x10: cvt_s({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD);
}});
- 0x10: cvt_d({{
+ 0x10: cvt_d({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD);
}});
- }
- }
-
- //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
- //Note: "1. Format type L is legal only if 64-bit floating point operations
- //are enabled."
- 0x5: decode FUNCTION_HI {
- format FloatOp {
- 0x10: cvt_s_l({{
+ }
+ }
+
+ //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
+ //Note: "1. Format type L is legal only if 64-bit floating point operations
+ //are enabled."
+ 0x5: decode FUNCTION_HI {
+ format FloatOp {
+ 0x10: cvt_s_l({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG);
}});
- 0x11: cvt_d_l({{
+ 0x11: cvt_d_l({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG);
}});
- }
- }
+ }
+ }
+
+ //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
+ //Note: "1. Format type PS is legal only if 64-bit floating point operations
+ //are enabled. "
+ 0x6: decode RS_HI {
+ 0x0: decode RS_LO {
+ format Float64Op {
+ 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df + Ft.df;
+ }});
- //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
- //Note: "1. Format type PS is legal only if 64-bit floating point operations
- //are enabled. "
- 0x6: decode RS_HI {
- 0x0: decode RS_LO {
- format Float64Op {
- 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = Fs.df + Ft.df;
- }});
-
- 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = Fs.df - Ft.df;
- }});
+ 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df - Ft.df;
+ }});
- 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = Fs.df * Ft.df;
- }});
+ 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs.df * Ft.df;
+ }});
- 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = abs(Fs.df);
- }});
+ 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = abs(Fs.df);
+ }});
- 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = Fs<31:0> | Ft<31:0>;
- }});
+ 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = Fs<31:0> | Ft<31:0>;
+ }});
- 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = -1 * Fs.df;
- }});
- }
- }
+ 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = -1 * Fs.df;
+ }});
+ }
+ }
- 0x2: decode RS_LO {
- 0x1: decode MOVCF {
- format Float64Op {
- 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
- 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
- }
- }
+ 0x2: decode RS_LO {
+ 0x1: decode MOVCF {
+ format Float64Op {
+ 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
+ 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}});
+ }
+ }
- }
+ }
- 0x4: decode RS_LO {
- 0x0: Float64Op::cvt_s_pu({{
+ 0x4: decode RS_LO {
+ 0x0: Float64Op::cvt_s_pu({{
int rnd_mode = xc->miscRegs.fcsr;
Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI);
- }});
- }
+ }});
+ }
- 0x5: decode RS_LO {
- format Float64Op {
- 0x0: cvt_s_pl({{
- int rnd_mode = xc->miscRegs.fcsr;
- Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
- }});
- 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}});
- 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}});
- 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}});
- 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}});
- }
- }
- }
- }
-
- //Table A-19 MIPS32 COP2 Encoding of rs Field
- 0x2: decode RS_MSB {
- 0x0: decode RS_HI {
- 0x0: decode RS_LO {
- format WarnUnimpl {
- 0x0: mfc2();
- 0x2: cfc2();
- 0x3: mfhc2();
- 0x4: mtc2();
- 0x6: ctc2();
- 0x7: mftc2();
- }
- }
-
- 0x1: decode ND {
- 0x0: decode TF {
- format WarnUnimpl {
- 0x0: bc2f();
- 0x1: bc2t();
- }
+ 0x5: decode RS_LO {
+ format Float64Op {
+ 0x0: cvt_s_pl({{
+ int rnd_mode = xc->miscRegs.fcsr;
+ Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO);
+ }});
+ 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}});
+ 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}});
+ 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}});
+ 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}});
+ }
+ }
+ }
+ }
}
+ }
+
+ //Table A-19 MIPS32 COP2 Encoding of rs Field
+ 0x2: decode RS_MSB {
+ 0x0: decode RS_HI {
+ 0x0: decode RS_LO {
+ format WarnUnimpl {
+ 0x0: mfc2();
+ 0x2: cfc2();
+ 0x3: mfhc2();
+ 0x4: mtc2();
+ 0x6: ctc2();
+ 0x7: mftc2();
+ }
+ }
+
+ 0x1: decode ND {
+ 0x0: decode TF {
+ format WarnUnimpl {
+ 0x0: bc2f();
+ 0x1: bc2t();
+ }
+ }
- 0x1: decode TF {
- format WarnUnimpl {
- 0x0: bc2fl();
- 0x1: bc2tl();
- }
+ 0x1: decode TF {
+ format WarnUnimpl {
+ 0x0: bc2fl();
+ 0x1: bc2tl();
+ }
+ }
+ }
}
- }
}
- }
- //Table A-20 MIPS64 COP1X Encoding of Function Field 1
- //Note: "COP1X instructions are legal only if 64-bit floating point
- //operations are enabled."
- 0x3: decode FUNCTION_HI {
- 0x0: decode FUNCTION_LO {
+ //Table A-20 MIPS64 COP1X Encoding of Function Field 1
+ //Note: "COP1X instructions are legal only if 64-bit floating point
+ //operations are enabled."
+ 0x3: decode FUNCTION_HI {
+ 0x0: decode FUNCTION_LO {
format Memory {
- 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }});
- 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }});
- 0x5: luxc1({{ //Need to make EA<2:0> = 0
- EA = Rs + Rt;
- }},
- {{ Ft<31:0> = Mem.df; }});
+ 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }});
+ 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }});
+ 0x5: luxc1({{ //Need to make EA<2:0> = 0
+ EA = Rs + Rt;
+ }},
+ {{ Ft<31:0> = Mem.df; }});
}
- }
+ }
- 0x1: decode FUNCTION_LO {
+ 0x1: decode FUNCTION_LO {
format Memory {
- 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }});
- 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}});
- 0x5: suxc1({{ //Need to make EA<2:0> = 0
- EA = Rs + Rt;
- }},
- {{ Mem.df = Ft<63:0>;}});
+ 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }});
+ 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}});
+ 0x5: suxc1({{ //Need to make EA<2:0> = 0
+ EA = Rs + Rt;
+ }},
+ {{ Mem.df = Ft<63:0>;}});
}
0x7: WarnUnimpl::prefx();
- }
+ }
- format FloatOp {
+ format FloatOp {
0x3: WarnUnimpl::alnv_ps();
format BasicOp {
- 0x4: decode FUNCTION_LO {
- 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
- 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
- 0x6: madd_ps({{
- //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = (Fs.df * Fs.df) + Fr.df;
- }});
- }
-
- 0x5: decode FUNCTION_LO {
- 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
- 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
- 0x6: msub_ps({{
- //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = (Fs.df * Fs.df) - Fr.df;
- }});
- }
-
- 0x6: decode FUNCTION_LO {
- 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
- 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
- 0x6: nmadd_ps({{
- //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
- }});
- }
-
- 0x7: decode FUNCTION_LO {
- 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
- 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
- 0x6: nmsub_ps({{
- //Must Check for Exception Here... Supposed to Operate on Upper and
- //Lower Halves Independently but we take simulator shortcut
- Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
- }});
- }
+ 0x4: decode FUNCTION_LO {
+ 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }});
+ 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }});
+ 0x6: madd_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (Fs.df * Fs.df) + Fr.df;
+ }});
+ }
+
+ 0x5: decode FUNCTION_LO {
+ 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }});
+ 0x6: msub_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (Fs.df * Fs.df) - Fr.df;
+ }});
+ }
+
+ 0x6: decode FUNCTION_LO {
+ 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }});
+ 0x6: nmadd_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+ }});
+ }
+
+ 0x7: decode FUNCTION_LO {
+ 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }});
+ 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }});
+ 0x6: nmsub_ps({{
+ //Must Check for Exception Here... Supposed to Operate on Upper and
+ //Lower Halves Independently but we take simulator shortcut
+ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df;
+ }});
+ }
}
+ }
}
- }
-
- //MIPS obsolete instructions
- format CondBranch {
- 0x4: beql({{ cond = (Rs.sw == 0); }});
- 0x5: bnel({{ cond = (Rs.sw != 0); }});
- 0x6: blezl({{ cond = (Rs.sw <= 0); }});
- 0x7: bgtzl({{ cond = (Rs.sw > 0); }});
+
+ //MIPS obsolete instructions
+ format BranchLikely {
+ 0x4: beql({{ cond = (Rs.sw == 0); }});
+ 0x5: bnel({{ cond = (Rs.sw != 0); }});
+ 0x6: blezl({{ cond = (Rs.sw <= 0); }});
+ 0x7: bgtzl({{ cond = (Rs.sw > 0); }});
}
}
@@ -752,89 +760,89 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode FUNCTION_LO {
format IntOp {
- 0x0: madd({{
+ 0x0: madd({{
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
- }});
+ }});
- 0x1: maddu({{
+ 0x1: maddu({{
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
- }});
+ }});
- 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
+ 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
- 0x4: msub({{
+ 0x4: msub({{
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
- }});
+ }});
- 0x5: msubu({{
+ 0x5: msubu({{
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->miscRegs.hi->temp1<63:32>;
xc->miscRegs.lo->temp1<31:0>
- }});
+ }});
}
}
0x4: decode FUNCTION_LO {
- format BasicOp {
- 0x0: clz({{
+ format BasicOp {
+ 0x0: clz({{
int cnt = 0;
int idx = 0;
while ( Rs.uw<idx>!= 1) {
- cnt++;
- idx--;
+ cnt++;
+ idx--;
}
Rd.uw = cnt;
- }});
+ }});
- 0x1: clo({{
+ 0x1: clo({{
int cnt = 0;
int idx = 0;
while ( Rs.uw<idx>!= 0) {
- cnt++;
- idx--;
+ cnt++;
+ idx--;
}
Rd.uw = cnt;
- }});
- }
+ }});
+ }
}
0x7: decode FUNCTION_LO {
- 0x7: WarnUnimpl::sdbbp();
+ 0x7: WarnUnimpl::sdbbp();
}
}
//Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture
0x7: decode FUNCTION_HI {
- 0x0: decode FUNCTION_LO {
+ 0x0: decode FUNCTION_LO {
format WarnUnimpl {
0x1: ext();
0x4: ins();
}
- }
+ }
- 0x1: decode FUNCTION_LO {
+ 0x1: decode FUNCTION_LO {
format WarnUnimpl {
0x0: fork();
0x1: yield();
}
- }
+ }
- //Table A-10 MIPS32 BSHFL Encoding of sa Field
- 0x4: decode SA {
+ //Table A-10 MIPS32 BSHFL Encoding of sa Field
+ 0x4: decode SA {
0x02: WarnUnimpl::wsbh();
@@ -842,11 +850,11 @@ decode OPCODE_HI default Unknown::unknown() {
0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
}
- }
+ }
- 0x6: decode FUNCTION_LO {
- 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
- }
+ 0x6: decode FUNCTION_LO {
+ 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}});
+ }
}
}
@@ -880,7 +888,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
- 0x0: WarnUnimpl::ll();
+ 0x0: WarnUnimpl::ll();
format Memory {
0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa
index 20ef49d82..c244013df 100644
--- a/arch/mips/isa/formats.isa
+++ b/arch/mips/isa/formats.isa
@@ -1,7 +1,15 @@
-//Include the basic format
+// -*- mode:c++ -*-
+
//Templates from this format are used later
+//Include the basic format
##include "m5/arch/mips/isa/formats/basic.isa"
+//Include the basic format
+##include "m5/arch/mips/isa/formats/noop.isa"
+
+//Include utility formats/functions
+##include "m5/arch/mips/isa/formats/util.isa"
+
//Include the integerOp and integerOpCc format
##include "m5/arch/mips/isa/formats/int.isa"
@@ -18,10 +26,6 @@
##include "m5/arch/mips/isa/formats/branch.isa"
//Include the noop format
-##include "m5/arch/mips/isa/formats/noop.isa"
-
-
-//Include the noop format
##include "m5/arch/mips/isa/formats/unimp.isa"
//Include the noop format
diff --git a/arch/mips/isa/formats/basic.isa b/arch/mips/isa/formats/basic.isa
index fc97c6ffa..3b62aa5c3 100644
--- a/arch/mips/isa/formats/basic.isa
+++ b/arch/mips/isa/formats/basic.isa
@@ -1,3 +1,4 @@
+// -*- mode:c++ -*-
// Declarations for execute() methods.
def template BasicExecDeclare {{
@@ -39,7 +40,7 @@ def template BasicExecute {{
if(fault == No_Fault)
{
- %(op_wb)s;
+ %(op_wb)s;
}
return fault;
}
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa
index e9c790c53..1f7a6f330 100644
--- a/arch/mips/isa/formats/branch.isa
+++ b/arch/mips/isa/formats/branch.isa
@@ -1,30 +1,9 @@
// -*- mode:c++ -*-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
+////////////////////////////////////////////////////////////////////
//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
+// Control transfer instructions
//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
output header {{
@@ -37,18 +16,19 @@ output header {{
* where the disassembly string includes the target address (which
* may depend on the PC and/or symbol table).
*/
- class PCDependentDisassembly : public AlphaStaticInst
+ class PCDependentDisassembly : public MipsStaticInst
{
protected:
/// Cached program counter from last disassembly
mutable Addr cachedPC;
+
/// Cached symbol table pointer from last disassembly
mutable const SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, MachInst _machInst,
OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass),
+ : MipsStaticInst(mnem, _machInst, __opClass),
cachedPC(0), cachedSymtab(0)
{
}
@@ -64,13 +44,35 @@ output header {{
class Branch : public PCDependentDisassembly
{
protected:
- /// Displacement to target address (signed).
+ /// target address (signed) Displacement .
int32_t disp;
/// Constructor.
Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
- disp(BRDISP << 2)
+ disp(OFFSET << 2)
+ {
+ }
+
+ Addr branchTarget(Addr branchPC) const;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for branch likely branches (PC-relative control transfers),
+ */
+ class BranchLikely : public PCDependentDisassembly
+ {
+ protected:
+ /// target address (signed) Displacement .
+ int32_t disp;
+
+ /// Constructor.
+ Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : PCDependentDisassembly(mnem, _machInst, __opClass),
+ disp(OFFSET << 2)
{
}
@@ -82,7 +84,7 @@ output header {{
/**
* Base class for jumps (register-indirect control transfers). In
- * the Alpha ISA, these are always unconditional.
+ * the Mips ISA, these are always unconditional.
*/
class Jump : public PCDependentDisassembly
{
@@ -95,7 +97,7 @@ output header {{
/// Constructor
Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
: PCDependentDisassembly(mnem, _machInst, __opClass),
- disp(BRDISP)
+ disp(OFFSET)
{
}
@@ -114,6 +116,12 @@ output decoder {{
}
Addr
+ BranchLikely::branchTarget(Addr branchPC) const
+ {
+ return branchPC + 4 + disp;
+ }
+
+ Addr
Jump::branchTarget(ExecContext *xc) const
{
Addr NPC = xc->readPC() + 4;
@@ -179,6 +187,44 @@ output decoder {{
}
std::string
+ BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ // There's only one register arg (RA), but it could be
+ // either a source (the condition for conditional
+ // branches) or a destination (the link reg for
+ // unconditional branches)
+ if (_numSrcRegs > 0) {
+ printReg(ss, _srcRegIdx[0]);
+ ss << ",";
+ }
+ else if (_numDestRegs > 0) {
+ printReg(ss, _destRegIdx[0]);
+ ss << ",";
+ }
+
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+ if (_numSrcRegs == 0 && _numDestRegs == 0) {
+ printReg(ss, 31);
+ ss << ",";
+ }
+#endif
+
+ Addr target = pc + 4 + disp;
+
+ std::string str;
+ if (symtab && symtab->findSymbol(target, str))
+ ss << str;
+ else
+ ccprintf(ss, "0x%x", target);
+
+ return ss.str();
+ }
+
+ std::string
Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@@ -203,14 +249,19 @@ output decoder {{
}
}};
-def template JumpOrBranchDecode {{
- return (RA == 31)
- ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
- : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
-}};
+def format Branch(code,*flags) {{
+ code = 'bool cond;\n\t' + code + '\n'
+
+ #Add Link Code if Link instruction
+ strlen = len(name)
+ if name[strlen-2:] == 'al':
+ code += 'R31 = NPC + 4;\n'
+
+ # condition code
+ code += 'if (cond) {'
+ code += ' NPC = NPC + disp;\n'
+ code += ' NNPC = NNPC + disp;\n } \n'
-def format CondBranch(code) {{
- code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
('IsDirectControl', 'IsCondControl'))
header_output = BasicDeclare.subst(iop)
@@ -219,41 +270,38 @@ def format CondBranch(code) {{
exec_output = BasicExecute.subst(iop)
}};
-let {{
-def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
- # Declare basic control transfer w/o link (i.e. link reg is R31)
- nolink_code = 'NPC = %s;\n' % npc_expr
- nolink_iop = InstObjParams(name, Name, base_class,
- CodeBlock(nolink_code), flags)
- header_output = BasicDeclare.subst(nolink_iop)
- decoder_output = BasicConstructor.subst(nolink_iop)
- exec_output = BasicExecute.subst(nolink_iop)
-
- # Generate declaration of '*AndLink' version, append to decls
- link_code = 'Ra = NPC & ~3;\n' + nolink_code
- link_iop = InstObjParams(name, Name + 'AndLink', base_class,
- CodeBlock(link_code), flags)
- header_output += BasicDeclare.subst(link_iop)
- decoder_output += BasicConstructor.subst(link_iop)
- exec_output += BasicExecute.subst(link_iop)
-
- # need to use link_iop for the decode template since it is expecting
- # the shorter version of class_name (w/o "AndLink")
-
- return (header_output, decoder_output,
- JumpOrBranchDecode.subst(nolink_iop), exec_output)
-}};
-def format UncondBranch(*flags) {{
- flags += ('IsUncondControl', 'IsDirectControl')
- (header_output, decoder_output, decode_block, exec_output) = \
- UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
+def format BranchLikely(code,*flags) {{
+ code = 'bool cond;\n\t\t\t' + code
+
+ #Add Link Code if Link instruction
+ strlen = len(name)
+ if name[strlen-3:] == 'all':
+ code += 'R31 = NPC + 4;\n'
+
+ #condition code
+ code += 'if (cond) {'
+ code += ' NPC = NPC + disp;\n'
+ code += ' NNPC = NNPC + disp;\n } \n'
+
+
+ iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
+ ('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
-def format Jump(*flags) {{
- flags += ('IsUncondControl', 'IsIndirectControl')
- (header_output, decoder_output, decode_block, exec_output) = \
- UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
+def format Unconditional(code,*flags) {{
+ iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),
+ ('IsIndirectControl', 'IsUncondControl'))
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};
+
+
diff --git a/arch/mips/isa/formats/int.isa b/arch/mips/isa/formats/int.isa
index 521f3a130..cf06741a1 100644
--- a/arch/mips/isa/formats/int.isa
+++ b/arch/mips/isa/formats/int.isa
@@ -1,8 +1,11 @@
+// -*- mode:c++ -*-
+
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//
+//Outputs to decoder.hh
output header {{
/**
* Base class for integer operations.
@@ -12,7 +15,7 @@ output header {{
protected:
/// Constructor
- IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
@@ -26,7 +29,7 @@ output header {{
uint16_t imm;
/// Constructor
- IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
{
}
@@ -36,6 +39,7 @@ output header {{
}};
+//Outputs to decoder.cc
output decoder {{
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
@@ -48,17 +52,18 @@ output decoder {{
}
}};
-// Primary format for integer operate instructions:
+
+//Used by decoder.isa
def format IntOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
# Figure out if we are creating a IntImmOp or a IntOp
+ # by looking at the instruction name
+ iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
strlen = len(name)
if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
- iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
- else:
- iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
+ iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa
index 6d45ba9b6..d366461e2 100644
--- a/arch/mips/isa/formats/noop.isa
+++ b/arch/mips/isa/formats/noop.isa
@@ -1,50 +1,4 @@
-////////////////////////////////////////////////////////////////////
-//
-// Noop instruction
-//
-
-output header {{
- /**
- * Base class for integer operations.
- */
- class Noop : public MipsStaticInst
- {
- protected:
-
- /// Constructor
- Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return "Disassembly of integer instruction\n";
- }
-}};
-
-def template NoopExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
- {
- //Nothing to see here, move along
- return No_Fault;
- }
-}};
-
-// Primary format for integer operate instructions:
-def format Noop(code, *opt_flags) {{
- orig_code = code
- cblk = CodeBlock(code)
- iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecodeWithMnemonic.subst(iop)
- exec_output = NoopExecute.subst(iop)
-}};
+// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
@@ -55,7 +9,7 @@ output header {{
/**
* Static instruction class for no-ops. This is a leaf class.
*/
- class Nop : public AlphaStaticInst
+ class Nop : public MipsStaticInst
{
/// Disassembly of original instruction.
const std::string originalDisassembly;
@@ -63,7 +17,7 @@ output header {{
public:
/// Constructor
Nop(const std::string _originalDisassembly, MachInst _machInst)
- : AlphaStaticInst("nop", _machInst, No_OpClass),
+ : MipsStaticInst("nop", _machInst, No_OpClass),
originalDisassembly(_originalDisassembly)
{
flags[IsNop] = true;
@@ -92,10 +46,10 @@ output decoder {{
/// Helper function for decoding nops. Substitute Nop object
/// for original inst passed in as arg (and delete latter).
inline
- AlphaStaticInst *
- makeNop(AlphaStaticInst *inst)
+ MipsStaticInst *
+ makeNop(MipsStaticInst *inst)
{
- AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+ MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
delete inst;
return nop;
}
@@ -113,7 +67,7 @@ output exec {{
// Rc == 31 to detect nops
def template OperateNopCheckDecode {{
{
- AlphaStaticInst *i = new %(class_name)s(machInst);
+ MipsStaticInst *i = new %(class_name)s(machInst);
if (RC == 31) {
i = makeNop(i);
}
@@ -124,7 +78,7 @@ def template OperateNopCheckDecode {{
// Like BasicOperate format, but generates NOP if RC/FC == 31
def format BasicOperateWithNopCheck(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),
+ iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code),
opt_args)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa
new file mode 100644
index 000000000..c6dae6783
--- /dev/null
+++ b/arch/mips/isa/formats/util.isa
@@ -0,0 +1,26 @@
+// -*- mode:c++ -*-
+
+let {{
+def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
+ # Declare basic control transfer w/o link (i.e. link reg is R31)
+ nolink_code = 'NPC = %s;\n' % npc_expr
+ nolink_iop = InstObjParams(name, Name, base_class,
+ CodeBlock(nolink_code), flags)
+ header_output = BasicDeclare.subst(nolink_iop)
+ decoder_output = BasicConstructor.subst(nolink_iop)
+ exec_output = BasicExecute.subst(nolink_iop)
+
+ # Generate declaration of '*AndLink' version, append to decls
+ link_code = 'Ra = NPC & ~3;\n' + nolink_code
+ link_iop = InstObjParams(name, Name + 'AndLink', base_class,
+ CodeBlock(link_code), flags)
+ header_output += BasicDeclare.subst(link_iop)
+ decoder_output += BasicConstructor.subst(link_iop)
+ exec_output += BasicExecute.subst(link_iop)
+
+ # need to use link_iop for the decode template since it is expecting
+ # the shorter version of class_name (w/o "AndLink")
+
+ return (header_output, decoder_output,
+ JumpOrBranchDecode.subst(nolink_iop), exec_output)
+}};
diff --git a/arch/mips/isa/operands.isa b/arch/mips/isa/operands.isa
index cf6f10e0b..77035f04c 100644
--- a/arch/mips/isa/operands.isa
+++ b/arch/mips/isa/operands.isa
@@ -16,6 +16,7 @@ def operands {{
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
+ 'R31': ('IntReg', 'uw','R31','IsInteger', 4),
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
@@ -24,12 +25,12 @@ def operands {{
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
- 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+ 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
- #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+ 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
+ 'NNPC': ('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
#'R0': ('IntReg', 'uq', '0', None, 1),
- #'R16': ('IntReg', 'uq', '16', None, 1)
}};
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 55e9c0dcb..e171737a3 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -430,6 +430,8 @@ class MipsISA
Addr pc; // Program Counter
Addr npc; // Next Program Counter
+ Addr nnpc; // Next next program Counter
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh
index 3c8659e18..e90f93847 100644
--- a/base/loader/object_file.hh
+++ b/base/loader/object_file.hh
@@ -37,6 +37,7 @@ class SymbolTable;
class ObjectFile
{
public:
+ typedef TheISA::Addr Addr;
enum Arch {
UnknownArch,
diff --git a/base/loader/symtab.hh b/base/loader/symtab.hh
index ebcda1345..38b4cdee2 100644
--- a/base/loader/symtab.hh
+++ b/base/loader/symtab.hh
@@ -37,8 +37,9 @@
class Checkpoint;
class SymbolTable
{
+ typedef TheISA::Addr Addr;
public:
- typedef std::map<Addr, std::string> ATable;
+ typedef std::map<TheISA::Addr, std::string> ATable;
typedef std::map<std::string, Addr> STable;
private:
diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc
index 67d745d43..17ec21fed 100644
--- a/base/remote_gdb.cc
+++ b/base/remote_gdb.cc
@@ -132,6 +132,7 @@
#include "targetarch/vtophys.hh"
using namespace std;
+using namespace TheISA;
#ifndef NDEBUG
vector<RemoteGDB *> debuggers;
@@ -494,7 +495,7 @@ RemoteGDB::setSingleStep()
// User was stopped at pc, e.g. the instruction at pc was not
// executed.
MachInst inst = read<MachInst>(pc);
- StaticInstPtr<TheISA> si(inst);
+ StaticInstPtr si(inst);
if (si->hasBranchTarget(pc, context, bpc)) {
// Don't bother setting a breakpoint on the taken branch if it
// is the same as the next pc
diff --git a/base/remote_gdb.hh b/base/remote_gdb.hh
index 652a58317..126d5f6f8 100644
--- a/base/remote_gdb.hh
+++ b/base/remote_gdb.hh
@@ -43,6 +43,9 @@ class PhysicalMemory;
class GDBListener;
class RemoteGDB
{
+ protected:
+ typedef TheISA::Addr Addr;
+ typedef TheISA::MachInst MachInst;
private:
friend void debugger();
friend class GDBListener;
diff --git a/cpu/base.cc b/cpu/base.cc
index 8b94b8533..5a7ecf152 100644
--- a/cpu/base.cc
+++ b/cpu/base.cc
@@ -250,7 +250,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
}
#if FULL_SYSTEM
- for (int i = 0; i < NumInterruptLevels; ++i)
+ for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
interrupts[i] = oldCPU->interrupts[i];
intstatus = oldCPU->intstatus;
@@ -285,7 +285,7 @@ BaseCPU::post_interrupt(int int_num, int index)
{
DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
- if (int_num < 0 || int_num >= NumInterruptLevels)
+ if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
panic("int_num out of bounds\n");
if (index < 0 || index >= sizeof(uint64_t) * 8)
@@ -301,7 +301,7 @@ BaseCPU::clear_interrupt(int int_num, int index)
{
DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
- if (int_num < 0 || int_num >= NumInterruptLevels)
+ if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
panic("int_num out of bounds\n");
if (index < 0 || index >= sizeof(uint64_t) * 8)
@@ -325,14 +325,14 @@ BaseCPU::clear_interrupts()
void
BaseCPU::serialize(std::ostream &os)
{
- SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+ SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
SERIALIZE_SCALAR(intstatus);
}
void
BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
{
- UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+ UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
UNSERIALIZE_SCALAR(intstatus);
}
diff --git a/cpu/base.hh b/cpu/base.hh
index 2bd1210d8..311b50f7f 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -48,6 +48,7 @@ class ExecContext;
class BaseCPU : public SimObject
{
protected:
+ typedef TheISA::Addr Addr;
// CPU's clock period in terms of the number of ticks of curTime.
Tick clock;
@@ -58,7 +59,7 @@ class BaseCPU : public SimObject
#if FULL_SYSTEM
protected:
- uint64_t interrupts[NumInterruptLevels];
+ uint64_t interrupts[TheISA::NumInterruptLevels];
uint64_t intstatus;
public:
@@ -68,7 +69,7 @@ class BaseCPU : public SimObject
bool checkInterrupts;
bool check_interrupt(int int_num) const {
- if (int_num > NumInterruptLevels)
+ if (int_num > TheISA::NumInterruptLevels)
panic("int_num out of bounds\n");
return interrupts[int_num] != 0;
@@ -140,6 +141,8 @@ class BaseCPU : public SimObject
virtual void startup();
virtual void regStats();
+ virtual void activateWhenReady(int tid) {};
+
void registerExecContexts();
/// Prepare for another CPU to take over execution. When it is
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 59a12f2d0..9901c90af 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -79,7 +79,7 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
}
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
: staticInst(_staticInst), traceData(NULL)
{
initVars();
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 2c91db99c..dd429fc91 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -51,7 +51,6 @@
*/
// Forward declaration.
-template <class ISA>
class StaticInstPtr;
template <class Impl>
@@ -61,25 +60,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
// Typedef for the CPU.
typedef typename Impl::FullCPU FullCPU;
- //Typedef to get the ISA.
- typedef typename Impl::ISA ISA;
-
/// Binary machine instruction type.
- typedef typename ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
/// Memory address type.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::Addr Addr;
/// Logical register index type.
- typedef typename ISA::RegIndex RegIndex;
+ typedef TheISA::RegIndex RegIndex;
/// Integer register index type.
- typedef typename ISA::IntReg IntReg;
+ typedef TheISA::IntReg IntReg;
enum {
- MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
/** The static inst used by this dyn inst. */
- StaticInstPtr<ISA> staticInst;
+ StaticInstPtr staticInst;
////////////////////////////////////////////
//
@@ -214,7 +210,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
- BaseDynInst(StaticInstPtr<ISA> &_staticInst);
+ BaseDynInst(StaticInstPtr &_staticInst);
/** BaseDynInst destructor. */
~BaseDynInst();
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 7e195af23..3c6bad34d 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -35,6 +35,7 @@
#include "sim/host.hh"
#include "sim/serialize.hh"
#include "arch/isa_traits.hh"
+//#include "arch/isa_registers.hh"
#include "sim/byteswap.hh"
// forward declaration: see functional_memory.hh
@@ -66,6 +67,11 @@ namespace Kernel { class Binning; class Statistics; }
class ExecContext
{
+ protected:
+ typedef TheISA::RegFile RegFile;
+ typedef TheISA::Addr Addr;
+ typedef TheISA::MachInst MachInst;
+ typedef TheISA::MiscRegFile MiscRegFile;
public:
enum Status
{
@@ -80,7 +86,7 @@ class ExecContext
Active,
/// Temporarily inactive. Entered while waiting for
- /// synchronization, etc.
+ /// initialization,synchronization, etc.
Suspended,
/// Permanently shut down. Entered when target executes
@@ -95,6 +101,8 @@ class ExecContext
public:
Status status() const { return _status; }
+ void setStatus(Status newStatus) { _status = newStatus; }
+
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
void activate(int delay = 1);
@@ -431,15 +439,15 @@ class ExecContext
void trap(Fault * fault);
#if !FULL_SYSTEM
- IntReg getSyscallArg(int i)
+ TheISA::IntReg getSyscallArg(int i)
{
- return regs.intRegFile[ArgumentReg0 + i];
+ return regs.intRegFile[TheISA::ArgumentReg0 + i];
}
// used to shift args for indirect syscall
- void setSyscallArg(int i, IntReg val)
+ void setSyscallArg(int i, TheISA::IntReg val)
{
- regs.intRegFile[ArgumentReg0 + i] = val;
+ regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
}
void setSyscallReturn(SyscallReturn return_value)
@@ -451,11 +459,11 @@ class ExecContext
if (return_value.successful()) {
// no error
regs.intRegFile[RegA3] = 0;
- regs.intRegFile[ReturnValueReg] = return_value.value();
+ regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
} else {
// got an error, return details
- regs.intRegFile[RegA3] = (IntReg) -1;
- regs.intRegFile[ReturnValueReg] = -return_value.value();
+ regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
+ regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
}
}
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index 48d8966d8..d37c48ddd 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -46,13 +46,15 @@ namespace Trace {
class InstRecord : public Record
{
protected:
+ typedef TheISA::Addr Addr;
+ typedef TheISA::IntRegFile IntRegFile;
// The following fields are initialized by the constructor and
// thus guaranteed to be valid.
BaseCPU *cpu;
// need to make this ref-counted so it doesn't go away before we
// dump the record
- StaticInstPtr<TheISA> staticInst;
+ StaticInstPtr staticInst;
Addr PC;
bool misspeculating;
unsigned thread;
@@ -92,7 +94,7 @@ class InstRecord : public Record
public:
InstRecord(Tick _cycle, BaseCPU *_cpu,
- const StaticInstPtr<TheISA> &_staticInst,
+ const StaticInstPtr &_staticInst,
Addr _pc, bool spec, int _thread)
: Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
misspeculating(spec), thread(_thread)
@@ -169,8 +171,8 @@ InstRecord::setRegs(const IntRegFile &regs)
inline
InstRecord *
getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
- const StaticInstPtr<TheISA> staticInst,
- Addr pc, int thread = 0)
+ const StaticInstPtr staticInst,
+ TheISA::Addr pc, int thread = 0)
{
if (DTRACE(InstExec) &&
(InstRecord::traceMisspec() || !xc->misspeculating())) {
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 27f790fac..5a4024587 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -44,6 +44,7 @@
#include "sim/stats.hh"
using namespace std;
+using namespace TheISA;
int TESTER_ALLOCATOR=0;
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 7abcf017a..76a89ff2c 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -42,6 +42,8 @@
class ExecContext;
class MemTest : public SimObject
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
MemTest(const std::string &name,
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index a97ce455c..78efe1e43 100644
--- a/cpu/o3/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -30,11 +30,13 @@
#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
class DefaultBP
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
/**
* Default branch predictor constructor.
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 606f9fa0a..bf3556b8e 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -39,8 +39,10 @@
template <class Impl>
class AlphaFullCPU : public FullO3CPU<Impl>
{
+ protected:
+ typedef AlphaISA::Addr Addr;
+ typedef TheISA::IntReg IntReg;
public:
- typedef typename Impl::ISA AlphaISA;
typedef typename Impl::Params Params;
public:
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 408676331..6736cf9bc 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -282,7 +282,7 @@ AlphaFullCPU<Impl>::hwrei()
if (!inPalMode())
return UnimplementedOpcodeFault;
- setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+ this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
// kernelStats.hwrei();
@@ -337,7 +337,7 @@ AlphaFullCPU<Impl>::trap(Fault * fault)
if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
- typename AlphaISA::InternalProcReg *ipr = getIpr();
+ AlphaISA::InternalProcReg *ipr = getIpr();
// exception restart address - Get the commit PC
if (fault != InterruptFault || !inPalMode(PC))
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 77dcbaf74..22be2aae5 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -48,21 +48,18 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Typedef for the CPU. */
typedef typename Impl::FullCPU FullCPU;
- /** Typedef to get the ISA. */
- typedef typename Impl::ISA ISA;
-
/** Binary machine instruction type. */
- typedef typename ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
/** Memory address type. */
- typedef typename ISA::Addr Addr;
+ typedef TheISA::Addr Addr;
/** Logical register index type. */
- typedef typename ISA::RegIndex RegIndex;
+ typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
- typedef typename ISA::IntReg IntReg;
+ typedef TheISA::IntReg IntReg;
enum {
- MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
public:
@@ -71,7 +68,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
- AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
+ AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
Fault * execute()
@@ -130,22 +127,22 @@ class AlphaDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst<ISA> *si, int idx)
+ uint64_t readIntReg(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- float readFloatRegSingle(const StaticInst<ISA> *si, int idx)
+ float readFloatRegSingle(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
}
- double readFloatRegDouble(const StaticInst<ISA> *si, int idx)
+ double readFloatRegDouble(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
}
- uint64_t readFloatRegInt(const StaticInst<ISA> *si, int idx)
+ uint64_t readFloatRegInt(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
}
@@ -153,25 +150,25 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst<ISA> *si, int idx, uint64_t val)
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
this->instResult.integer = val;
}
- void setFloatRegSingle(const StaticInst<ISA> *si, int idx, float val)
+ void setFloatRegSingle(const StaticInst *si, int idx, float val)
{
this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
this->instResult.fp = val;
}
- void setFloatRegDouble(const StaticInst<ISA> *si, int idx, double val)
+ void setFloatRegDouble(const StaticInst *si, int idx, double val)
{
this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
this->instResult.dbl = val;
}
- void setFloatRegInt(const StaticInst<ISA> *si, int idx, uint64_t val)
+ void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setFloatRegInt(_destRegIdx[idx], val);
this->instResult.integer = val;
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index b20af48cd..9f9df3da1 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -50,7 +50,7 @@ AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
}
template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
: BaseDynInst<Impl>(_staticInst)
{
// Make sure to have the renamed register entries set to the same
diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 6c1156041..5e39fcb37 100644
--- a/cpu/o3/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -51,11 +51,8 @@ class AlphaFullCPU;
*/
struct AlphaSimpleImpl
{
- /** The ISA to be used. */
- typedef AlphaISA ISA;
-
/** The type of MachInst. */
- typedef ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
/** The CPU policy to be used (ie fetch, decode, etc.). */
typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..c874f9e04 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -53,6 +53,8 @@
template<class Impl>
class TwobitBPredUnit
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index 9cb2e0490..8d16a0cdf 100644
--- a/cpu/o3/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -98,6 +98,8 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
// Save off record of branch stuff so the RAS can be fixed
// up once it's done.
+ using TheISA::MachInst;
+
bool pred_taken = false;
Addr target;
diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc
index 7671e61e2..2d39c3856 100644
--- a/cpu/o3/btb.cc
+++ b/cpu/o3/btb.cc
@@ -30,6 +30,8 @@
#include "base/trace.hh"
#include "cpu/o3/btb.hh"
+using namespace TheISA;
+
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
unsigned _instShiftAmt)
diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh
index a4ddfecb4..f443ddbaf 100644
--- a/cpu/o3/btb.hh
+++ b/cpu/o3/btb.hh
@@ -30,10 +30,12 @@
#define __CPU_O3_CPU_BTB_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
class DefaultBTB
{
+ protected:
+ typedef TheISA::Addr Addr;
private:
struct BTBEntry
{
diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh
index 6ddc8d6b9..580c1a316 100644
--- a/cpu/o3/commit.hh
+++ b/cpu/o3/commit.hh
@@ -52,7 +52,6 @@ class SimpleCommit
{
public:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index adc7b6bbc..ffa157fbb 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -84,14 +84,14 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
- freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
- Impl::ISA::NumFloatRegs, params.numPhysFloatRegs),
+ freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
+ TheISA::NumFloatRegs, params.numPhysFloatRegs),
- renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
- Impl::ISA::NumFloatRegs, params.numPhysFloatRegs,
- Impl::ISA::NumMiscRegs,
- Impl::ISA::ZeroReg,
- Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs),
+ renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
+ TheISA::NumFloatRegs, params.numPhysFloatRegs,
+ TheISA::NumMiscRegs,
+ TheISA::ZeroReg,
+ TheISA::ZeroReg + TheISA::NumIntRegs),
rob(params.numROBEntries, params.squashWidth),
@@ -254,13 +254,13 @@ FullO3CPU<Impl>::init()
ExecContext *src_xc = thread[0];
#endif
// First loop through the integer registers.
- for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
+ for (int i = 0; i < TheISA::NumIntRegs; ++i)
{
regFile.intRegFile[i] = src_xc->regs.intRegFile[i];
}
// Then loop through the floating point registers.
- for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i)
{
regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 75dca5056..321d61dce 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU
{
public:
//Put typedefs from the Impl here.
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
/** Get instruction asid. */
int getInstAsid()
- { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
+ { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
/** Get data asid. */
int getDataAsid()
- { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
+ { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
#else
bool validInstAddr(Addr addr)
{ return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh
index 42313d83a..bae9a7015 100644
--- a/cpu/o3/decode.hh
+++ b/cpu/o3/decode.hh
@@ -39,7 +39,6 @@ class SimpleDecode
{
private:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
@@ -51,7 +50,7 @@ class SimpleDecode
typedef typename CPUPol::TimeStruct TimeStruct;
// Typedefs from the ISA.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::Addr Addr;
public:
// The only time decode will become blocked is if dispatch becomes
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 5443d274e..e4d374c1d 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -49,7 +49,6 @@ class SimpleFetch
{
public:
/** Typedefs from Impl. */
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInst DynInst;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -61,7 +60,8 @@ class SimpleFetch
typedef typename CPUPol::TimeStruct TimeStruct;
/** Typedefs from ISA. */
- typedef typename ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
+ typedef TheISA::Addr Addr;
public:
enum Status {
@@ -141,7 +141,7 @@ class SimpleFetch
// We fold in the PISA 64- to 32-bit conversion here as well.
Addr icacheBlockAlignPC(Addr addr)
{
- addr = ISA::realPCToFetchPC(addr);
+ addr = TheISA::realPCToFetchPC(addr);
return (addr & ~(cacheBlkMask));
}
diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh
index 733d142fc..0b85dba1e 100644
--- a/cpu/o3/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -32,7 +32,7 @@
#include <iostream>
#include <queue>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/comm.hh"
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index af23c6f45..1e370d4e6 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -45,7 +45,6 @@ class SimpleIEW
{
private:
//Typedefs from Impl
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index b8a2b4dc9..85217dd10 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -256,7 +256,7 @@ SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst)
toCommit->branchMispredict = true;
// Prediction was incorrect, so send back inverse.
toCommit->branchTaken = inst->readNextPC() !=
- (inst->readPC() + sizeof(MachInst));
+ (inst->readPC() + sizeof(TheISA::MachInst));
}
template<class Impl>
diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh
index bbc4162a6..fd7f5fe1c 100644
--- a/cpu/o3/ras.hh
+++ b/cpu/o3/ras.hh
@@ -30,10 +30,12 @@
#define __CPU_O3_CPU_RAS_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
class ReturnAddrStack
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
ReturnAddrStack(unsigned numEntries);
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 5aafd5495..655a3cad9 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -52,6 +52,11 @@ using namespace EV5;
template <class Impl>
class PhysRegFile
{
+ protected:
+ typedef TheISA::Addr Addr;
+ typedef TheISA::IntReg IntReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::MiscRegFile MiscRegFile;
//Note that most of the definitions of the IntReg, FloatReg, etc. exist
//within the Impl/ISA class and not within this PhysRegFile class.
@@ -62,7 +67,6 @@ class PhysRegFile
//Will make these registers public for now, but they probably should
//be private eventually with some accessor functions.
public:
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -281,73 +285,73 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
uint64_t retval = 0; // return value, default 0
switch (idx) {
- case ISA::IPR_PALtemp0:
- case ISA::IPR_PALtemp1:
- case ISA::IPR_PALtemp2:
- case ISA::IPR_PALtemp3:
- case ISA::IPR_PALtemp4:
- case ISA::IPR_PALtemp5:
- case ISA::IPR_PALtemp6:
- case ISA::IPR_PALtemp7:
- case ISA::IPR_PALtemp8:
- case ISA::IPR_PALtemp9:
- case ISA::IPR_PALtemp10:
- case ISA::IPR_PALtemp11:
- case ISA::IPR_PALtemp12:
- case ISA::IPR_PALtemp13:
- case ISA::IPR_PALtemp14:
- case ISA::IPR_PALtemp15:
- case ISA::IPR_PALtemp16:
- case ISA::IPR_PALtemp17:
- case ISA::IPR_PALtemp18:
- case ISA::IPR_PALtemp19:
- case ISA::IPR_PALtemp20:
- case ISA::IPR_PALtemp21:
- case ISA::IPR_PALtemp22:
- case ISA::IPR_PALtemp23:
- case ISA::IPR_PAL_BASE:
-
- case ISA::IPR_IVPTBR:
- case ISA::IPR_DC_MODE:
- case ISA::IPR_MAF_MODE:
- case ISA::IPR_ISR:
- case ISA::IPR_EXC_ADDR:
- case ISA::IPR_IC_PERR_STAT:
- case ISA::IPR_DC_PERR_STAT:
- case ISA::IPR_MCSR:
- case ISA::IPR_ASTRR:
- case ISA::IPR_ASTER:
- case ISA::IPR_SIRR:
- case ISA::IPR_ICSR:
- case ISA::IPR_ICM:
- case ISA::IPR_DTB_CM:
- case ISA::IPR_IPLR:
- case ISA::IPR_INTID:
- case ISA::IPR_PMCTR:
+ case TheISA::IPR_PALtemp0:
+ case TheISA::IPR_PALtemp1:
+ case TheISA::IPR_PALtemp2:
+ case TheISA::IPR_PALtemp3:
+ case TheISA::IPR_PALtemp4:
+ case TheISA::IPR_PALtemp5:
+ case TheISA::IPR_PALtemp6:
+ case TheISA::IPR_PALtemp7:
+ case TheISA::IPR_PALtemp8:
+ case TheISA::IPR_PALtemp9:
+ case TheISA::IPR_PALtemp10:
+ case TheISA::IPR_PALtemp11:
+ case TheISA::IPR_PALtemp12:
+ case TheISA::IPR_PALtemp13:
+ case TheISA::IPR_PALtemp14:
+ case TheISA::IPR_PALtemp15:
+ case TheISA::IPR_PALtemp16:
+ case TheISA::IPR_PALtemp17:
+ case TheISA::IPR_PALtemp18:
+ case TheISA::IPR_PALtemp19:
+ case TheISA::IPR_PALtemp20:
+ case TheISA::IPR_PALtemp21:
+ case TheISA::IPR_PALtemp22:
+ case TheISA::IPR_PALtemp23:
+ case TheISA::IPR_PAL_BASE:
+
+ case TheISA::IPR_IVPTBR:
+ case TheISA::IPR_DC_MODE:
+ case TheISA::IPR_MAF_MODE:
+ case TheISA::IPR_ISR:
+ case TheISA::IPR_EXC_ADDR:
+ case TheISA::IPR_IC_PERR_STAT:
+ case TheISA::IPR_DC_PERR_STAT:
+ case TheISA::IPR_MCSR:
+ case TheISA::IPR_ASTRR:
+ case TheISA::IPR_ASTER:
+ case TheISA::IPR_SIRR:
+ case TheISA::IPR_ICSR:
+ case TheISA::IPR_ICM:
+ case TheISA::IPR_DTB_CM:
+ case TheISA::IPR_IPLR:
+ case TheISA::IPR_INTID:
+ case TheISA::IPR_PMCTR:
// no side-effect
retval = ipr[idx];
break;
- case ISA::IPR_CC:
+ case TheISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= curTick & ULL(0x00000000ffffffff);
break;
- case ISA::IPR_VA:
+ case TheISA::IPR_VA:
retval = ipr[idx];
break;
- case ISA::IPR_VA_FORM:
- case ISA::IPR_MM_STAT:
- case ISA::IPR_IFAULT_VA_FORM:
- case ISA::IPR_EXC_MASK:
- case ISA::IPR_EXC_SUM:
+ case TheISA::IPR_VA_FORM:
+ case TheISA::IPR_MM_STAT:
+ case TheISA::IPR_IFAULT_VA_FORM:
+ case TheISA::IPR_EXC_MASK:
+ case TheISA::IPR_EXC_SUM:
retval = ipr[idx];
break;
- case ISA::IPR_DTB_PTE:
+ case TheISA::IPR_DTB_PTE:
{
- typename ISA::PTE &pte = cpu->dtb->index(1);
+ TheISA::PTE &pte = cpu->dtb->index(1);
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -360,15 +364,15 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
break;
// write only registers
- case ISA::IPR_HWINT_CLR:
- case ISA::IPR_SL_XMIT:
- case ISA::IPR_DC_FLUSH:
- case ISA::IPR_IC_FLUSH:
- case ISA::IPR_ALT_MODE:
- case ISA::IPR_DTB_IA:
- case ISA::IPR_DTB_IAP:
- case ISA::IPR_ITB_IA:
- case ISA::IPR_ITB_IAP:
+ case TheISA::IPR_HWINT_CLR:
+ case TheISA::IPR_SL_XMIT:
+ case TheISA::IPR_DC_FLUSH:
+ case TheISA::IPR_IC_FLUSH:
+ case TheISA::IPR_ALT_MODE:
+ case TheISA::IPR_DTB_IA:
+ case TheISA::IPR_DTB_IAP:
+ case TheISA::IPR_ITB_IA:
+ case TheISA::IPR_ITB_IAP:
fault = UnimplementedOpcodeFault;
break;
@@ -390,195 +394,195 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
uint64_t old;
switch (idx) {
- case ISA::IPR_PALtemp0:
- case ISA::IPR_PALtemp1:
- case ISA::IPR_PALtemp2:
- case ISA::IPR_PALtemp3:
- case ISA::IPR_PALtemp4:
- case ISA::IPR_PALtemp5:
- case ISA::IPR_PALtemp6:
- case ISA::IPR_PALtemp7:
- case ISA::IPR_PALtemp8:
- case ISA::IPR_PALtemp9:
- case ISA::IPR_PALtemp10:
- case ISA::IPR_PALtemp11:
- case ISA::IPR_PALtemp12:
- case ISA::IPR_PALtemp13:
- case ISA::IPR_PALtemp14:
- case ISA::IPR_PALtemp15:
- case ISA::IPR_PALtemp16:
- case ISA::IPR_PALtemp17:
- case ISA::IPR_PALtemp18:
- case ISA::IPR_PALtemp19:
- case ISA::IPR_PALtemp20:
- case ISA::IPR_PALtemp21:
- case ISA::IPR_PALtemp22:
- case ISA::IPR_PAL_BASE:
- case ISA::IPR_IC_PERR_STAT:
- case ISA::IPR_DC_PERR_STAT:
- case ISA::IPR_PMCTR:
+ case TheISA::IPR_PALtemp0:
+ case TheISA::IPR_PALtemp1:
+ case TheISA::IPR_PALtemp2:
+ case TheISA::IPR_PALtemp3:
+ case TheISA::IPR_PALtemp4:
+ case TheISA::IPR_PALtemp5:
+ case TheISA::IPR_PALtemp6:
+ case TheISA::IPR_PALtemp7:
+ case TheISA::IPR_PALtemp8:
+ case TheISA::IPR_PALtemp9:
+ case TheISA::IPR_PALtemp10:
+ case TheISA::IPR_PALtemp11:
+ case TheISA::IPR_PALtemp12:
+ case TheISA::IPR_PALtemp13:
+ case TheISA::IPR_PALtemp14:
+ case TheISA::IPR_PALtemp15:
+ case TheISA::IPR_PALtemp16:
+ case TheISA::IPR_PALtemp17:
+ case TheISA::IPR_PALtemp18:
+ case TheISA::IPR_PALtemp19:
+ case TheISA::IPR_PALtemp20:
+ case TheISA::IPR_PALtemp21:
+ case TheISA::IPR_PALtemp22:
+ case TheISA::IPR_PAL_BASE:
+ case TheISA::IPR_IC_PERR_STAT:
+ case TheISA::IPR_DC_PERR_STAT:
+ case TheISA::IPR_PMCTR:
// write entire quad w/ no side-effect
ipr[idx] = val;
break;
- case ISA::IPR_CC_CTL:
+ case TheISA::IPR_CC_CTL:
// This IPR resets the cycle counter. We assume this only
// happens once... let's verify that.
assert(ipr[idx] == 0);
ipr[idx] = 1;
break;
- case ISA::IPR_CC:
+ case TheISA::IPR_CC:
// This IPR only writes the upper 64 bits. It's ok to write
// all 64 here since we mask out the lower 32 in rpcc (see
// isa_desc).
ipr[idx] = val;
break;
- case ISA::IPR_PALtemp23:
+ case TheISA::IPR_PALtemp23:
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
break;
- case ISA::IPR_DTB_PTE:
+ case TheISA::IPR_DTB_PTE:
// write entire quad w/ no side-effect, tag is forthcoming
ipr[idx] = val;
break;
- case ISA::IPR_EXC_ADDR:
+ case TheISA::IPR_EXC_ADDR:
// second least significant bit in PC is always zero
ipr[idx] = val & ~2;
break;
- case ISA::IPR_ASTRR:
- case ISA::IPR_ASTER:
+ case TheISA::IPR_ASTRR:
+ case TheISA::IPR_ASTER:
// only write least significant four bits - privilege mask
ipr[idx] = val & 0xf;
break;
- case ISA::IPR_IPLR:
+ case TheISA::IPR_IPLR:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
break;
- case ISA::IPR_DTB_CM:
+ case TheISA::IPR_DTB_CM:
- case ISA::IPR_ICM:
+ case TheISA::IPR_ICM:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
- case ISA::IPR_ALT_MODE:
+ case TheISA::IPR_ALT_MODE:
// only write two mode bits - processor mode
ipr[idx] = val & 0x18;
break;
- case ISA::IPR_MCSR:
+ case TheISA::IPR_MCSR:
// more here after optimization...
ipr[idx] = val;
break;
- case ISA::IPR_SIRR:
+ case TheISA::IPR_SIRR:
// only write software interrupt mask
ipr[idx] = val & 0x7fff0;
break;
- case ISA::IPR_ICSR:
+ case TheISA::IPR_ICSR:
ipr[idx] = val & ULL(0xffffff0300);
break;
- case ISA::IPR_IVPTBR:
- case ISA::IPR_MVPTBR:
+ case TheISA::IPR_IVPTBR:
+ case TheISA::IPR_MVPTBR:
ipr[idx] = val & ULL(0xffffffffc0000000);
break;
- case ISA::IPR_DC_TEST_CTL:
+ case TheISA::IPR_DC_TEST_CTL:
ipr[idx] = val & 0x1ffb;
break;
- case ISA::IPR_DC_MODE:
- case ISA::IPR_MAF_MODE:
+ case TheISA::IPR_DC_MODE:
+ case TheISA::IPR_MAF_MODE:
ipr[idx] = val & 0x3f;
break;
- case ISA::IPR_ITB_ASN:
+ case TheISA::IPR_ITB_ASN:
ipr[idx] = val & 0x7f0;
break;
- case ISA::IPR_DTB_ASN:
+ case TheISA::IPR_DTB_ASN:
ipr[idx] = val & ULL(0xfe00000000000000);
break;
- case ISA::IPR_EXC_SUM:
- case ISA::IPR_EXC_MASK:
+ case TheISA::IPR_EXC_SUM:
+ case TheISA::IPR_EXC_MASK:
// any write to this register clears it
ipr[idx] = 0;
break;
- case ISA::IPR_INTID:
- case ISA::IPR_SL_RCV:
- case ISA::IPR_MM_STAT:
- case ISA::IPR_ITB_PTE_TEMP:
- case ISA::IPR_DTB_PTE_TEMP:
+ case TheISA::IPR_INTID:
+ case TheISA::IPR_SL_RCV:
+ case TheISA::IPR_MM_STAT:
+ case TheISA::IPR_ITB_PTE_TEMP:
+ case TheISA::IPR_DTB_PTE_TEMP:
// read-only registers
return UnimplementedOpcodeFault;
- case ISA::IPR_HWINT_CLR:
- case ISA::IPR_SL_XMIT:
- case ISA::IPR_DC_FLUSH:
- case ISA::IPR_IC_FLUSH:
+ case TheISA::IPR_HWINT_CLR:
+ case TheISA::IPR_SL_XMIT:
+ case TheISA::IPR_DC_FLUSH:
+ case TheISA::IPR_IC_FLUSH:
// the following are write only
ipr[idx] = val;
break;
- case ISA::IPR_DTB_IA:
+ case TheISA::IPR_DTB_IA:
// really a control write
ipr[idx] = 0;
cpu->dtb->flushAll();
break;
- case ISA::IPR_DTB_IAP:
+ case TheISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
cpu->dtb->flushProcesses();
break;
- case ISA::IPR_DTB_IS:
+ case TheISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
- cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
+ cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
break;
- case ISA::IPR_DTB_TAG: {
- struct ISA::PTE pte;
+ case TheISA::IPR_DTB_TAG: {
+ struct TheISA::PTE pte;
// FIXME: granularity hints NYI...
- if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
+ if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
- pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
- pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
- pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
- pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
- pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
- pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
- pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
+ pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
+ pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
+ pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
+ pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
+ pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
+ pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
+ pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
cpu->dtb->insert(val, pte);
}
break;
- case ISA::IPR_ITB_PTE: {
- struct ISA::PTE pte;
+ case TheISA::IPR_ITB_PTE: {
+ struct TheISA::PTE pte;
// FIXME: granularity hints NYI...
if (ITB_PTE_GH(val) != 0)
@@ -594,32 +598,32 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
pte.fonr = ITB_PTE_FONR(val);
pte.fonw = ITB_PTE_FONW(val);
pte.asma = ITB_PTE_ASMA(val);
- pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
+ pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
- cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
+ cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
}
break;
- case ISA::IPR_ITB_IA:
+ case TheISA::IPR_ITB_IA:
// really a control write
ipr[idx] = 0;
cpu->itb->flushAll();
break;
- case ISA::IPR_ITB_IAP:
+ case TheISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
cpu->itb->flushProcesses();
break;
- case ISA::IPR_ITB_IS:
+ case TheISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
- cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
+ cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
break;
default:
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index a17ec7311..9781480b6 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -46,7 +46,6 @@ class SimpleRename
{
public:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU;
@@ -62,7 +61,8 @@ class SimpleRename
typedef typename CPUPol::RenameMap RenameMap;
// Typedefs from the ISA.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::Addr Addr;
+ typedef TheISA::RegIndex RegIndex;
public:
// Rename will block if ROB becomes full or issue queue becomes full,
diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh
index c44c7a1ea..57be4a64a 100644
--- a/cpu/o3/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -38,9 +38,13 @@
#include <vector>
#include "cpu/o3/free_list.hh"
+//For RegIndex
+#include "arch/isa_traits.hh"
class SimpleRenameMap
{
+ protected:
+ typedef TheISA::RegIndex RegIndex;
public:
/**
* Pair of a logical register and a physical register. Tells the
diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh
index 29ec48007..1185564ad 100644
--- a/cpu/o3/rob.hh
+++ b/cpu/o3/rob.hh
@@ -47,6 +47,8 @@
template <class Impl>
class ROB
{
+ protected:
+ typedef TheISA::RegIndex RegIndex;
public:
//Typedefs from the Impl.
typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh
index bcd590384..c67d30fcb 100644
--- a/cpu/o3/store_set.hh
+++ b/cpu/o3/store_set.hh
@@ -31,11 +31,13 @@
#include <vector>
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
class StoreSet
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
typedef unsigned SSID;
diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index 58ea1a7d9..6cfd24cfb 100644
--- a/cpu/o3/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -30,11 +30,13 @@
#define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
// For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
class TournamentBP
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
/**
* Default branch predictor constructor.
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 21fe05b6a..7976632d9 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -77,7 +77,6 @@ class OoOCPU : public BaseCPU
private:
typedef typename Impl::DynInst DynInst;
typedef typename Impl::DynInstPtr DynInstPtr;
- typedef typename Impl::ISA ISA;
public:
// main simulation loop (one cycle)
@@ -378,12 +377,12 @@ class OoOCPU : public BaseCPU
private:
InstSeqNum globalSeqNum;
- DynInstPtr renameTable[ISA::TotalNumRegs];
- DynInstPtr commitTable[ISA::TotalNumRegs];
+ DynInstPtr renameTable[TheISA::TotalNumRegs];
+ DynInstPtr commitTable[TheISA::TotalNumRegs];
// Might need a table of the shadow registers as well.
#if FULL_SYSTEM
- DynInstPtr palShadowTable[ISA::NumIntRegs];
+ DynInstPtr palShadowTable[TheISA::NumIntRegs];
#endif
public:
@@ -402,47 +401,47 @@ class OoOCPU : public BaseCPU
// rename table of DynInsts. Also these likely shouldn't be called very
// often, other than when adding things into the xc during say a syscall.
- uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
+ uint64_t readIntReg(StaticInst *si, int idx)
{
return xc->readIntReg(si->srcRegIdx(idx));
}
- float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
+ float readFloatRegSingle(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegSingle(reg_idx);
}
- double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
+ double readFloatRegDouble(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegDouble(reg_idx);
}
- uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
+ uint64_t readFloatRegInt(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegInt(reg_idx);
}
- void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
+ void setIntReg(StaticInst *si, int idx, uint64_t val)
{
xc->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
+ void setFloatRegSingle(StaticInst *si, int idx, float val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegSingle(reg_idx, val);
}
- void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
+ void setFloatRegDouble(StaticInst *si, int idx, double val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegDouble(reg_idx, val);
}
- void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
+ void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegInt(reg_idx, val);
@@ -479,7 +478,7 @@ class OoOCPU : public BaseCPU
// We fold in the PISA 64- to 32-bit conversion here as well.
Addr icacheBlockAlignPC(Addr addr)
{
- addr = ISA::realPCToFetchPC(addr);
+ addr = TheISA::realPCToFetchPC(addr);
return (addr & ~(cacheBlkMask));
}
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index 83fbc3e2d..7a294866d 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -136,14 +136,14 @@ BreakPCEvent::process(ExecContext *xc)
#if FULL_SYSTEM
extern "C"
void
-sched_break_pc_sys(System *sys, Addr addr)
+sched_break_pc_sys(System *sys, TheISA::Addr addr)
{
new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
}
extern "C"
void
-sched_break_pc(Addr addr)
+sched_break_pc(TheISA::Addr addr)
{
for (vector<System *>::iterator sysi = System::systemList.begin();
sysi != System::systemList.end(); ++sysi) {
diff --git a/cpu/pc_event.hh b/cpu/pc_event.hh
index 7fa3902cc..3033a3cfd 100644
--- a/cpu/pc_event.hh
+++ b/cpu/pc_event.hh
@@ -39,6 +39,7 @@ class PCEventQueue;
class PCEvent
{
protected:
+ typedef TheISA::Addr Addr;
static const Addr badpc = MemReq::inval_addr;
protected:
@@ -64,6 +65,7 @@ class PCEvent
class PCEventQueue
{
protected:
+ typedef TheISA::Addr Addr;
typedef PCEvent * record_t;
class MapCompare {
public:
@@ -132,6 +134,7 @@ PCEvent::remove()
class BreakPCEvent : public PCEvent
{
protected:
+ typedef TheISA::Addr Addr;
bool remove;
public:
diff --git a/cpu/profile.hh b/cpu/profile.hh
index 58cd7e79f..b55f87a6a 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -37,6 +37,8 @@
class ProfileNode
{
+ protected:
+ typedef TheISA::Addr Addr;
private:
friend class FunctionProfile;
@@ -57,6 +59,8 @@ class ProfileNode
class Callback;
class FunctionProfile
{
+ public:
+ typedef TheISA::Addr Addr;
private:
Callback *reset;
const SymbolTable *symtab;
@@ -68,7 +72,7 @@ class FunctionProfile
FunctionProfile(const SymbolTable *symtab);
~FunctionProfile();
- ProfileNode *consume(ExecContext *xc, StaticInstPtr<TheISA> inst);
+ ProfileNode *consume(ExecContext *xc, StaticInstPtr inst);
ProfileNode *consume(const std::vector<Addr> &stack);
void clear();
void dump(ExecContext *xc, std::ostream &out) const;
@@ -76,7 +80,7 @@ class FunctionProfile
};
inline ProfileNode *
-FunctionProfile::consume(ExecContext *xc, StaticInstPtr<TheISA> inst)
+FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst)
{
if (!trace.trace(xc, inst))
return NULL;
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 6aff94abd..c3f256de9 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -76,7 +76,7 @@
using namespace std;
//The SimpleCPU does alpha only
-using namespace LittleEndianGuest;
+using namespace AlphaISA;
SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
@@ -125,7 +125,7 @@ SimpleCPU::SimpleCPU(Params *p)
xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
// initialize CPU, including PC
- TheISA::initCPU(&xc->regs);
+ initCPU(&xc->regs);
#else
xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
#endif // !FULL_SYSTEM
@@ -323,7 +323,7 @@ SimpleCPU::copySrcTranslate(Addr src)
// Make sure block doesn't span page
if (no_warn &&
- (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
+ (src & PageMask) != ((src + blk_size) & PageMask) &&
(src >> 40) != 0xfffffc) {
warn("Copied block source spans pages %x.", src);
no_warn = false;
@@ -359,7 +359,7 @@ SimpleCPU::copy(Addr dest)
// Make sure block doesn't span page
if (no_warn &&
- (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
+ (dest & PageMask) != ((dest + blk_size) & PageMask) &&
(dest >> 40) != 0xfffffc) {
no_warn = false;
warn("Copied block destination spans pages %x. ", dest);
@@ -648,20 +648,20 @@ SimpleCPU::tick()
checkInterrupts = false;
IntReg *ipr = xc->regs.ipr;
- if (xc->regs.ipr[TheISA::IPR_SIRR]) {
- for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
- i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
- if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
+ if (xc->regs.ipr[IPR_SIRR]) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (ipr[IPR_SIRR] & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
- ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
summary |= (ULL(1) << i);
}
}
}
uint64_t interrupts = xc->cpu->intr_status();
- for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
- i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
if (interrupts & (ULL(1) << i)) {
// See table 4-19 of 21164 hardware reference
ipl = i;
@@ -669,16 +669,16 @@ SimpleCPU::tick()
}
}
- if (ipr[TheISA::IPR_ASTRR])
+ if (ipr[IPR_ASTRR])
panic("asynchronous traps not implemented\n");
- if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
- ipr[TheISA::IPR_ISR] = summary;
- ipr[TheISA::IPR_INTID] = ipl;
+ if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
+ ipr[IPR_ISR] = summary;
+ ipr[IPR_INTID] = ipl;
xc->ev5_trap(InterruptFault);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- ipr[TheISA::IPR_IPLR], ipl, summary);
+ ipr[IPR_IPLR], ipl, summary);
}
}
#endif
@@ -749,7 +749,7 @@ SimpleCPU::tick()
// decode the instruction
inst = gtoh(inst);
- curStaticInst = StaticInst<TheISA>::decode(inst);
+ curStaticInst = StaticInst::decode(inst);
traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
xc->regs.pc);
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index e7a447117..8a3900726 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -63,6 +63,8 @@ namespace Trace {
class SimpleCPU : public BaseCPU
{
+ protected:
+ typedef TheISA::MachInst MachInst;
public:
// main simulation loop (one cycle)
void tick();
@@ -172,7 +174,7 @@ class SimpleCPU : public BaseCPU
// the next switchover
Sampler *sampler;
- StaticInstPtr<TheISA> curStaticInst;
+ StaticInstPtr curStaticInst;
class CacheCompletionEvent : public Event
{
@@ -269,47 +271,47 @@ class SimpleCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
+ uint64_t readIntReg(const StaticInst *si, int idx)
{
return xc->readIntReg(si->srcRegIdx(idx));
}
- float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
+ float readFloatRegSingle(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegSingle(reg_idx);
}
- double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
+ double readFloatRegDouble(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegDouble(reg_idx);
}
- uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
+ uint64_t readFloatRegInt(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegInt(reg_idx);
}
- void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
xc->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
+ void setFloatRegSingle(const StaticInst *si, int idx, float val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegSingle(reg_idx, val);
}
- void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
+ void setFloatRegDouble(const StaticInst *si, int idx, double val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegDouble(reg_idx, val);
}
- void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
+ void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegInt(reg_idx, val);
diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc
index 54bd9914e..c307dc6fc 100644
--- a/cpu/static_inst.cc
+++ b/cpu/static_inst.cc
@@ -30,19 +30,13 @@
#include "cpu/static_inst.hh"
#include "sim/root.hh"
-template <class ISA>
-StaticInstPtr<ISA> StaticInst<ISA>::nullStaticInstPtr;
-
-template <class ISA>
-typename StaticInst<ISA>::DecodeCache StaticInst<ISA>::decodeCache;
+StaticInstPtr StaticInst::nullStaticInstPtr;
// Define the decode cache hash map.
-template StaticInst<AlphaISA>::DecodeCache
-StaticInst<AlphaISA>::decodeCache;
+StaticInst::DecodeCache StaticInst::decodeCache;
-template <class ISA>
void
-StaticInst<ISA>::dumpDecodeCacheStats()
+StaticInst::dumpDecodeCacheStats()
{
using namespace std;
@@ -62,13 +56,8 @@ StaticInst<ISA>::dumpDecodeCacheStats()
}
}
-
-template StaticInstPtr<AlphaISA>
-StaticInst<AlphaISA>::nullStaticInstPtr;
-
-template <class ISA>
bool
-StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
{
if (isDirectCtrl()) {
tgt = branchTarget(pc);
@@ -83,6 +72,3 @@ StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
return false;
}
-
-// force instantiation of template function(s) above
-template class StaticInst<AlphaISA>;
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 24997eadc..1ff14df08 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -113,6 +113,8 @@ class StaticInstBase : public RefCounted
IsSerializing, ///< Serializes pipeline: won't execute until all
/// older instructions have committed.
+ IsSerializeBefore,
+ IsSerializeAfter,
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
@@ -196,7 +198,11 @@ class StaticInstBase : public RefCounted
bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
- bool isSerializing() const { return flags[IsSerializing]; }
+ bool isSerializing() const { return flags[IsSerializing] ||
+ flags[IsSerializeBefore] ||
+ flags[IsSerializeAfter]; }
+ bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
+ bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
@@ -208,7 +214,6 @@ class StaticInstBase : public RefCounted
// forward declaration
-template <class ISA>
class StaticInstPtr;
/**
@@ -218,21 +223,20 @@ class StaticInstPtr;
* that are generic across all ISAs but that differ in details
* according to the specific ISA being used.
*/
-template <class ISA>
class StaticInst : public StaticInstBase
{
public:
/// Binary machine instruction type.
- typedef typename ISA::MachInst MachInst;
+ typedef TheISA::MachInst MachInst;
/// Memory address type.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::Addr Addr;
/// Logical register index type.
- typedef typename ISA::RegIndex RegIndex;
+ typedef TheISA::RegIndex RegIndex;
enum {
- MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
@@ -247,7 +251,7 @@ class StaticInst : public StaticInstBase
/// Pointer to a statically allocated "null" instruction object.
/// Used to give eaCompInst() and memAccInst() something to return
/// when called on non-memory instructions.
- static StaticInstPtr<ISA> nullStaticInstPtr;
+ static StaticInstPtr nullStaticInstPtr;
/**
* Memory references only: returns "fake" instruction representing
@@ -256,7 +260,7 @@ class StaticInst : public StaticInstBase
* just the EA computation.
*/
virtual const
- StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
+ StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
/**
* Memory references only: returns "fake" instruction representing
@@ -265,7 +269,7 @@ class StaticInst : public StaticInstBase
* just the memory access (not the EA computation).
*/
virtual const
- StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
+ StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
const MachInst machInst;
@@ -364,7 +368,7 @@ class StaticInst : public StaticInstBase
/// Decoded instruction cache type.
/// For now we're using a generic hash_map; this seems to work
/// pretty well.
- typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
+ typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache;
/// A cache of decoded instruction objects.
static DecodeCache decodeCache;
@@ -378,63 +382,40 @@ class StaticInst : public StaticInstBase
/// Decode a machine instruction.
/// @param mach_inst The binary instruction to decode.
/// @retval A pointer to the corresponding StaticInst object.
- static
- StaticInstPtr<ISA> decode(MachInst mach_inst)
- {
-#ifdef DECODE_CACHE_HASH_STATS
- // Simple stats on decode hash_map. Turns out the default
- // hash function is as good as anything I could come up with.
- const int dump_every_n = 10000000;
- static int decodes_til_dump = dump_every_n;
-
- if (--decodes_til_dump == 0) {
- dumpDecodeCacheStats();
- decodes_til_dump = dump_every_n;
- }
-#endif
-
- typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
- if (iter != decodeCache.end()) {
- return iter->second;
- }
-
- StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
- decodeCache[mach_inst] = si;
- return si;
- }
+ //This is defined as inline below.
+ static StaticInstPtr decode(MachInst mach_inst);
};
typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
/// Reference-counted pointer to a StaticInst object.
-/// This type should be used instead of "StaticInst<ISA> *" so that
+/// This type should be used instead of "StaticInst *" so that
/// StaticInst objects can be properly reference-counted.
-template <class ISA>
-class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
+class StaticInstPtr : public RefCountingPtr<StaticInst>
{
public:
/// Constructor.
StaticInstPtr()
- : RefCountingPtr<StaticInst<ISA> >()
+ : RefCountingPtr<StaticInst>()
{
}
- /// Conversion from "StaticInst<ISA> *".
- StaticInstPtr(StaticInst<ISA> *p)
- : RefCountingPtr<StaticInst<ISA> >(p)
+ /// Conversion from "StaticInst *".
+ StaticInstPtr(StaticInst *p)
+ : RefCountingPtr<StaticInst>(p)
{
}
/// Copy constructor.
StaticInstPtr(const StaticInstPtr &r)
- : RefCountingPtr<StaticInst<ISA> >(r)
+ : RefCountingPtr<StaticInst>(r)
{
}
/// Construct directly from machine instruction.
- /// Calls StaticInst<ISA>::decode().
- StaticInstPtr(typename ISA::MachInst mach_inst)
- : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
+ /// Calls StaticInst::decode().
+ StaticInstPtr(TheISA::MachInst mach_inst)
+ : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
{
}
@@ -445,4 +426,29 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
}
};
+inline StaticInstPtr
+StaticInst::decode(StaticInst::MachInst mach_inst)
+{
+#ifdef DECODE_CACHE_HASH_STATS
+ // Simple stats on decode hash_map. Turns out the default
+ // hash function is as good as anything I could come up with.
+ const int dump_every_n = 10000000;
+ static int decodes_til_dump = dump_every_n;
+
+ if (--decodes_til_dump == 0) {
+ dumpDecodeCacheStats();
+ decodes_til_dump = dump_every_n;
+ }
+#endif
+
+ DecodeCache::iterator iter = decodeCache.find(mach_inst);
+ if (iter != decodeCache.end()) {
+ return iter->second;
+ }
+
+ StaticInstPtr si = TheISA::decodeInst(mach_inst);
+ decodeCache[mach_inst] = si;
+ return si;
+}
+
#endif // __CPU_STATIC_INST_HH__
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index f81691733..704dc09fa 100644
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -49,6 +49,8 @@ class MemTraceReader;
*/
class OptCPU : public SimObject
{
+ protected:
+ typedef TheISA::Addr Addr;
private:
typedef int RefIndex;
diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh
index faec73138..e402b2d52 100644
--- a/cpu/trace/reader/itx_reader.hh
+++ b/cpu/trace/reader/itx_reader.hh
@@ -46,6 +46,9 @@
*/
class ITXReader : public MemTraceReader
{
+ protected:
+ typedef TheISA::Addr Addr;
+ private:
/** Trace file. */
FILE *trace;
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 38fbbdef0..a7ef8f641 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -53,6 +53,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace AlphaISA;
AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *p,
diff --git a/dev/baddev.cc b/dev/baddev.cc
index b6ca919e4..62871e348 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -46,6 +46,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *pio_bus, const string &devicename)
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index a5cb0dfd8..18c988b81 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -48,6 +48,7 @@
#include "sim/sim_object.hh"
using namespace std;
+using namespace TheISA;
////
// Initialization and destruction
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index 9d8bb8825..41400c590 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -53,6 +53,7 @@
#include "arch/isa_traits.hh"
using namespace std;
+using namespace TheISA;
IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
int id, Tick delay)
diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh
index a656ca464..32888c81c 100644
--- a/dev/ide_disk.hh
+++ b/dev/ide_disk.hh
@@ -188,6 +188,8 @@ class IdeController;
class IdeDisk : public SimObject
{
protected:
+ typedef TheISA::Addr Addr;
+ protected:
/** The IDE controller for this disk. */
IdeController *ctrl;
/** The DMA interface to use for transfers */
diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc
index 93c9eedbf..117c9e5ad 100644
--- a/dev/isa_fake.cc
+++ b/dev/isa_fake.cc
@@ -45,6 +45,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *pio_bus, Addr size)
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index c28615438..07bf178fc 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -84,6 +84,7 @@ const char *NsDmaState[] =
using namespace std;
using namespace Net;
+using namespace TheISA;
///////////////////////////////////////////////////////////////////////
//
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 1175172c4..c581e1561 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -47,6 +47,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
PciConfigAll::PciConfigAll(const string &name,
Addr a, MemoryController *mmu,
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index c8d9685c1..a100bf746 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -53,6 +53,8 @@ class MemoryController;
*/
class PciConfigData : public SimObject
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
/**
* Constructor to initialize the devices config space to 0.
diff --git a/dev/platform.cc b/dev/platform.cc
index 58f94db7b..5b667b12c 100644
--- a/dev/platform.cc
+++ b/dev/platform.cc
@@ -31,6 +31,7 @@
#include "sim/sim_exit.hh"
using namespace std;
+using namespace TheISA;
Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
: SimObject(name), intrctrl(intctrl), pciconfig(pci)
diff --git a/dev/platform.hh b/dev/platform.hh
index 1ee645454..87810250a 100644
--- a/dev/platform.hh
+++ b/dev/platform.hh
@@ -44,6 +44,8 @@ class Uart;
class Platform : public SimObject
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh
index 6560e15c2..f68d5bfff 100644
--- a/dev/simple_disk.hh
+++ b/dev/simple_disk.hh
@@ -44,19 +44,21 @@ class PhysicalMemory;
*/
class SimpleDisk : public SimObject
{
-public:
- typedef uint64_t baddr_t;
+ protected:
+ typedef TheISA::Addr Addr;
+ public:
+ typedef uint64_t baddr_t;
-protected:
- PhysicalMemory *physmem;
- DiskImage *image;
+ protected:
+ PhysicalMemory *physmem;
+ DiskImage *image;
-public:
- SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
- ~SimpleDisk();
+ public:
+ SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
+ ~SimpleDisk();
- void read(Addr addr, baddr_t block, int count) const;
- void write(Addr addr, baddr_t block, int count);
+ void read(Addr addr, baddr_t block, int count) const;
+ void write(Addr addr, baddr_t block, int count);
};
#endif // __DEV_SIMPLE_DISK_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index e79f80678..829d58d32 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -50,6 +50,7 @@
#include "targetarch/vtophys.hh"
using namespace Net;
+using namespace TheISA;
namespace Sinic {
diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh
index b7008b4e1..343db6303 100644
--- a/dev/sinicreg.hh
+++ b/dev/sinicreg.hh
@@ -165,7 +165,7 @@ struct Info
/* namespace Regs */ }
inline const Regs::Info&
-regInfo(Addr daddr)
+regInfo(TheISA::Addr daddr)
{
static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
static Regs::Info info [] = {
@@ -201,7 +201,7 @@ regInfo(Addr daddr)
}
inline bool
-regValid(Addr daddr)
+regValid(TheISA::Addr daddr)
{
if (daddr > Regs::Size)
return false;
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index 760848a00..58fc7434e 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -46,6 +46,8 @@
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
PciConfigAll *pci)
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 7fd91d5b2..79b561ed7 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -55,6 +55,8 @@ class System;
class Tsunami : public Platform
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
/** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 64;
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 4cda9ec36..10c08a7a2 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -47,6 +47,8 @@
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 0d0d27570..e90bb5abc 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -50,6 +50,8 @@
#include "mem/functional/memory_control.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
: _name(name), event(t, i), addr(0)
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index a4c04a79f..706daf9dc 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -47,6 +47,8 @@
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index a2e782189..99355e28a 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -46,6 +46,7 @@
#include "sim/builder.hh"
using namespace std;
+using namespace TheISA;
Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
: Event(&mainEventQueue), uart(u)
diff --git a/kern/freebsd/freebsd_system.cc b/kern/freebsd/freebsd_system.cc
index dbf60a3fc..cead8caaf 100644
--- a/kern/freebsd/freebsd_system.cc
+++ b/kern/freebsd/freebsd_system.cc
@@ -46,6 +46,7 @@
#define TIMER_FREQUENCY 1193180
using namespace std;
+using namespace TheISA;
FreebsdSystem::FreebsdSystem(Params *p)
: System(p)
diff --git a/kern/kernel_stats.hh b/kern/kernel_stats.hh
index a36c73fb4..3e4fdf9e6 100644
--- a/kern/kernel_stats.hh
+++ b/kern/kernel_stats.hh
@@ -50,6 +50,8 @@ extern const char *modestr[];
class Binning
{
+ protected:
+ typedef TheISA::Addr Addr;
private:
std::string myname;
System *system;
@@ -106,7 +108,7 @@ class Binning
cpu_mode themode;
void palSwapContext(ExecContext *xc);
- void execute(ExecContext *xc, StaticInstPtr<TheISA> inst);
+ void execute(ExecContext *xc, StaticInstPtr inst);
void call(ExecContext *xc, Stats::MainBin *myBin);
void changeMode(cpu_mode mode);
@@ -124,6 +126,9 @@ class Binning
class Statistics : public Serializable
{
+ protected:
+ typedef TheISA::Addr Addr;
+ private:
friend class Binning;
private:
diff --git a/kern/linux/aligned.hh b/kern/linux/aligned.hh
index 18d1b43c0..137f65076 100644
--- a/kern/linux/aligned.hh
+++ b/kern/linux/aligned.hh
@@ -37,7 +37,7 @@
#if __GNUC__ == 3 && __GNUC_MINOR__ != 3
typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
-typedef Addr Addr_a __attribute__ ((aligned (8))) ;
+typedef TheISA::Addr Addr_a __attribute__ ((aligned (8))) ;
#else
#define uint64_ta uint64_t __attribute__ ((aligned (8)))
#define int64_ta int64_t __attribute__ ((aligned (8)))
diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc
index 26a4c0d3e..c5a9e184a 100644
--- a/kern/linux/linux_system.cc
+++ b/kern/linux/linux_system.cc
@@ -50,6 +50,7 @@
#include "targetarch/vtophys.hh"
using namespace std;
+using namespace TheISA;
LinuxSystem::LinuxSystem(Params *p)
: System(p)
diff --git a/kern/linux/linux_threadinfo.hh b/kern/linux/linux_threadinfo.hh
index 9bab1dc49..f20188360 100644
--- a/kern/linux/linux_threadinfo.hh
+++ b/kern/linux/linux_threadinfo.hh
@@ -37,6 +37,8 @@ namespace Linux {
class ThreadInfo
{
+ protected:
+ typedef TheISA::Addr Addr;
private:
ExecContext *xc;
@@ -53,7 +55,7 @@ class ThreadInfo
* thread_info struct. So we can get the address by masking off
* the lower 14 bits.
*/
- current = xc->regs.intRegFile[StackPointerReg] & ~0x3fff;
+ current = xc->regs.intRegFile[TheISA::StackPointerReg] & ~0x3fff;
return VPtr<thread_info>(xc, current);
}
diff --git a/kern/system_events.cc b/kern/system_events.cc
index ba3c9274a..55595b9b6 100644
--- a/kern/system_events.cc
+++ b/kern/system_events.cc
@@ -29,6 +29,8 @@
#include "encumbered/cpu/full/cpu.hh"
#include "kern/kernel_stats.hh"
+using namespace TheISA;
+
void
SkipFuncEvent::process(ExecContext *xc)
{
diff --git a/kern/tru64/dump_mbuf.cc b/kern/tru64/dump_mbuf.cc
index 85cb4de96..efdaed62d 100644
--- a/kern/tru64/dump_mbuf.cc
+++ b/kern/tru64/dump_mbuf.cc
@@ -38,6 +38,8 @@
#include "arch/isa_traits.hh"
#include "targetarch/vtophys.hh"
+using namespace TheISA;
+
namespace tru64 {
void
diff --git a/kern/tru64/mbuf.hh b/kern/tru64/mbuf.hh
index 93424858f..7b84b5e10 100644
--- a/kern/tru64/mbuf.hh
+++ b/kern/tru64/mbuf.hh
@@ -35,35 +35,35 @@
namespace tru64 {
struct m_hdr {
- Addr mh_next; // 0x00
- Addr mh_nextpkt; // 0x08
- Addr mh_data; // 0x10
+ TheISA::Addr mh_next; // 0x00
+ TheISA::Addr mh_nextpkt; // 0x08
+ TheISA::Addr mh_data; // 0x10
int32_t mh_len; // 0x18
int32_t mh_type; // 0x1C
int32_t mh_flags; // 0x20
int32_t mh_pad0; // 0x24
- Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
+ TheISA::Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
};
struct pkthdr {
int32_t len;
int32_t protocolSum;
- Addr rcvif;
+ TheISA::Addr rcvif;
};
struct m_ext {
- Addr ext_buf; // 0x00
- Addr ext_free; // 0x08
+ TheISA::Addr ext_buf; // 0x00
+ TheISA::Addr ext_free; // 0x08
uint32_t ext_size; // 0x10
uint32_t ext_pad0; // 0x14
- Addr ext_arg; // 0x18
+ TheISA::Addr ext_arg; // 0x18
struct ext_refq {
- Addr forw, back; // 0x20, 0x28
+ TheISA::Addr forw, back; // 0x20, 0x28
} ext_ref;
- Addr uiomove_f; // 0x30
+ TheISA::Addr uiomove_f; // 0x30
int32_t protocolSum; // 0x38
int32_t bytesSummed; // 0x3C
- Addr checksum; // 0x40
+ TheISA::Addr checksum; // 0x40
};
struct mbuf {
diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc
index d769aab0f..2fe6a2dc4 100644
--- a/kern/tru64/tru64_events.cc
+++ b/kern/tru64/tru64_events.cc
@@ -36,6 +36,8 @@
#include "targetarch/arguments.hh"
#include "arch/isa_traits.hh"
+using namespace TheISA;
+
//void SkipFuncEvent::process(ExecContext *xc);
void
diff --git a/sim/process.cc b/sim/process.cc
index 3ae3abb52..0a7e46082 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -54,6 +54,7 @@
#endif
using namespace std;
+using namespace TheISA;
//
// The purpose of this code is to fake the loader & syscall mechanism
diff --git a/sim/process.hh b/sim/process.hh
index 40143ea04..6e91bb0ab 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -51,6 +51,10 @@ class FunctionalMemory;
class SyscallDesc;
class Process : public SimObject
{
+ protected:
+ typedef TheISA::Addr Addr;
+ typedef TheISA::RegFile RegFile;
+ typedef TheISA::MachInst MachInst;
public:
// have we initialized an execution context from this process? If
diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc
index 11ab55f53..58ea8266f 100644
--- a/sim/pseudo_inst.cc
+++ b/sim/pseudo_inst.cc
@@ -53,6 +53,7 @@ using namespace std;
extern Sampler *SampCPU;
using namespace Stats;
+using namespace TheISA;
namespace AlphaPseudo
{
diff --git a/sim/pseudo_inst.hh b/sim/pseudo_inst.hh
index 3857f2050..07bdd7091 100644
--- a/sim/pseudo_inst.hh
+++ b/sim/pseudo_inst.hh
@@ -52,8 +52,8 @@ namespace AlphaPseudo
void dumpstats(ExecContext *xc, Tick delay, Tick period);
void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
- uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
+ uint64_t readfile(ExecContext *xc, TheISA::Addr vaddr, uint64_t len, uint64_t offset);
void debugbreak(ExecContext *xc);
void switchcpu(ExecContext *xc);
- void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
+ void addsymbol(ExecContext *xc, TheISA::Addr addr, TheISA::Addr symbolAddr);
}
diff --git a/sim/syscall_emul.cc b/sim/syscall_emul.cc
index 0bfb9ddf5..d22dde3b8 100644
--- a/sim/syscall_emul.cc
+++ b/sim/syscall_emul.cc
@@ -41,6 +41,7 @@
#include "sim/sim_events.hh"
using namespace std;
+using namespace TheISA;
void
SyscallDesc::doSyscall(int callnum, Process *process, ExecContext *xc)
@@ -90,7 +91,7 @@ exitFunc(SyscallDesc *desc, int callnum, Process *process,
SyscallReturn
getpagesizeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
- return VMPageSize;
+ return (int)VMPageSize;
}
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 72e454ae1..4e4f9a5d7 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -90,6 +90,9 @@ class SyscallDesc {
class BaseBufferArg {
+ protected:
+ typedef TheISA::Addr Addr;
+
public:
BaseBufferArg(Addr _addr, int _size) : addr(_addr), size(_size)
@@ -640,7 +643,7 @@ template <class OS>
SyscallReturn
mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
- Addr start = xc->getSyscallArg(0);
+ TheISA::Addr start = xc->getSyscallArg(0);
uint64_t length = xc->getSyscallArg(1);
// int prot = xc->getSyscallArg(2);
int flags = xc->getSyscallArg(3);
@@ -650,7 +653,7 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
if (start == 0) {
// user didn't give an address... pick one from our "mmap region"
start = p->mmap_end;
- p->mmap_end += roundUp(length, VMPageSize);
+ p->mmap_end += roundUp(length, TheISA::VMPageSize);
if (p->nxm_start != 0) {
//If we have an nxm space, make sure we haven't colided
assert(p->mmap_end < p->nxm_start);
diff --git a/sim/system.cc b/sim/system.cc
index 990145826..ebeb5b244 100644
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -41,6 +41,7 @@
#include "base/trace.hh"
using namespace std;
+using namespace TheISA;
vector<System *> System::systemList;
diff --git a/sim/system.hh b/sim/system.hh
index aa697c040..4bf33a170 100644
--- a/sim/system.hh
+++ b/sim/system.hh
@@ -50,6 +50,8 @@ namespace Kernel { class Binning; }
class System : public SimObject
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
MemoryController *memctrl;
PhysicalMemory *physmem;
diff --git a/sim/vptr.hh b/sim/vptr.hh
index 7ec43602d..1baa00610 100644
--- a/sim/vptr.hh
+++ b/sim/vptr.hh
@@ -37,6 +37,8 @@ class ExecContext;
template <class T>
class VPtr
{
+ protected:
+ typedef TheISA::Addr Addr;
public:
typedef T Type;