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-rw-r--r--configs/example/fs.py4
-rw-r--r--configs/example/ruby_direct_test.py2
-rw-r--r--configs/example/ruby_fs.py8
-rw-r--r--configs/example/ruby_mem_test.py2
-rw-r--r--configs/example/ruby_network_test.py2
-rw-r--r--configs/example/ruby_random_test.py2
-rw-r--r--configs/example/se.py4
-rw-r--r--configs/ruby/MESI_CMP_directory.py6
-rw-r--r--configs/ruby/MI_example.py8
-rw-r--r--configs/ruby/MOESI_CMP_directory.py6
-rw-r--r--configs/ruby/MOESI_CMP_token.py6
-rw-r--r--configs/ruby/MOESI_hammer.py6
-rw-r--r--configs/ruby/Network_test.py2
13 files changed, 29 insertions, 29 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 754a0b79b..4c2aeeefe 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -195,8 +195,8 @@ if len(bm) == 2:
drive_sys.kernel = binary(options.kernel)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(bm[1].mem())])
- drive_sys.iobridge.slave = drive_sys.iobus.port
- drive_sys.iobridge.master = drive_sys.membus.port
+ drive_sys.iobridge.slave = drive_sys.iobus.master
+ drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.init_param = options.init_param
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 28c7dde55..7f38d5431 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -102,7 +102,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
- system.tester.cpuPort = ruby_port.port
+ system.tester.cpuPort = ruby_port.slave
# -----------------------
# run simulation
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 04b99034c..869a10ef7 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -125,11 +125,11 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
- cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
+ cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
- cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
+ cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
+ cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.interrupts.pio = system.piobus.master
cpu.interrupts.int_master = system.piobus.slave
cpu.interrupts.int_slave = system.piobus.master
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 5b693f3f6..20c25e833 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -133,7 +133,7 @@ for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby._cpu_ruby_ports[i].port
+ cpu.test = system.ruby._cpu_ruby_ports[i].slave
cpu.functional = system.funcmem.port
#
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index 79e6365af..aa93acd2f 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -109,7 +109,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
- cpus[i].test = ruby_port.port
+ cpus[i].test = ruby_port.slave
ruby_port.access_phys_mem = False
i += 1
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 4074b08f1..5e6d82372 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -110,7 +110,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
- tester.cpuPort = ruby_port.port
+ tester.cpuPort = ruby_port.slave
#
# Tell each sequencer this is the ruby tester so that it
diff --git a/configs/example/se.py b/configs/example/se.py
index d7b876d46..de98fa002 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -190,8 +190,8 @@ for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
- system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
- system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
+ system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
+ system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 79de421bb..4fdba3c27 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
@@ -180,9 +180,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 13f4c9c80..851001b6f 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -95,7 +95,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -153,10 +153,10 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
- dma_cntrl.dma_sequencer.port = dma_device.dma
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
+ dma_cntrl.dma_sequencer.slave = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index f6baa4026..ac582e4e6 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -177,9 +177,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 79e0f15f9..20b50e3af 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -125,7 +125,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -201,9 +201,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index f50315599..3f89a1a90 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -118,7 +118,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
@@ -213,9 +213,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency:
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index bbe7fe844..768b14677 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -96,7 +96,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 14:33:47 +0000