diff options
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index e546e2a9a..5aecea7d5 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -825,6 +825,10 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) } if (mshr->promoteDeferredTargets()) { + assert(mshr->needsExclusive() && !blk->isWritable()); + // avoid later read getting stale data while write miss is + // outstanding.. see comment in timingAccess() + blk->status &= ~BlkReadable; MSHRQueue *mq = mshr->queue; mq->markPending(mshr); requestMemSideBus((RequestCause)mq->index, pkt->finishTime); |