diff options
| -rw-r--r-- | src/arch/mips/mips_core_specific.hh | 68 | ||||
| -rw-r--r-- | src/arch/mips/utility.hh | 9 |
2 files changed, 33 insertions, 44 deletions
diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh index 4e20c11f2..0d19bf944 100644 --- a/src/arch/mips/mips_core_specific.hh +++ b/src/arch/mips/mips_core_specific.hh @@ -1,51 +1,49 @@ /* - * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved + * Copyright (c) 2007 MIPS Technologies, Inc. + * All rights reserved. * - * This software is part of the M5 simulator. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * - * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING - * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING - * TO THESE TERMS AND CONDITIONS. - * - * Permission is granted to use, copy, create derivative works and - * distribute this software and such derivative works for any purpose, - * so long as (1) the copyright notice above, this grant of permission, - * and the disclaimer below appear in all copies and derivative works - * made, (2) the copyright notice above is augmented as appropriate to - * reflect the addition of any new copyrightable work in a derivative - * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) - * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any - * advertising or publicity pertaining to the use or distribution of - * this software without specific, written prior authorization. - * - * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND - * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR - * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND - * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. - * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, - * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF - * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, - * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY - * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR - * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE - * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Jaidev Patwardhan - * */ - #ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__ #define __ARCH_MIPS_CORE_SPECIFIC_HH__ #include "arch/mips/isa_traits.hh" -namespace MipsISA { - - - +class ThreadContext; +namespace MipsISA { + void initCPU(ThreadContext *tc, int cpuId); + + /** + * Function to check for and process any interrupts. + * @param tc The thread context. + */ + template <class CPU> + void processInterrupts(CPU *cpu); }; #endif // __ARCH_MIPS_CORE_SPECIFIC_HH__ diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 7282124a9..12ce3af9e 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -141,15 +141,6 @@ namespace MipsISA { // // CPU Utility // - void initCPU(ThreadContext *tc, int cpuId); - - /** - * Function to check for and process any interrupts. - * @param tc The thread context. - */ - template <class TC> - void processInterrupts(TC *tc); - void startupCPU(ThreadContext *tc, int cpuId); }; |