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-rw-r--r--configs/example/fs.py10
-rw-r--r--configs/example/se.py6
-rw-r--r--src/cpu/base.hh14
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py14
-rw-r--r--src/cpu/simple/atomic.cc43
-rw-r--r--src/cpu/simple/atomic.hh22
6 files changed, 65 insertions, 44 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4b6956b72..38571fec3 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010-2011 ARM Limited
+# Copyright (c) 2010-2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -133,9 +133,13 @@ else:
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
+# Sanity check
+if options.fastmem and (options.caches or options.l2cache):
+ fatal("You cannot use fastmem in combination with caches!")
+
for i in xrange(np):
if options.fastmem:
- test_sys.cpu[i].physmem_port = test_sys.physmem.port
+ test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
@@ -160,7 +164,7 @@ if len(bm) == 2:
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
- drive_sys.cpu.physmem_port = drive_sys.physmem.port
+ drive_sys.cpu.fastmem = True
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
diff --git a/configs/example/se.py b/configs/example/se.py
index a6cf1ec19..a2f8a09dc 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -155,11 +155,15 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = PhysicalMemory(range=AddrRange("512MB")),
membus = Bus(), mem_mode = test_mem_mode)
+# Sanity check
+if options.fastmem and (options.caches or options.l2cache):
+ fatal("You cannot use fastmem in combination with caches!")
+
for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
if options.fastmem:
- system.cpu[0].physmem_port = system.physmem.port
+ system.cpu[0].fastmem = True
if options.checker:
system.cpu[i].addCheckerCpu()
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 145b014aa..3fb0f648b 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -170,22 +170,16 @@ class BaseCPU : public MemObject
MasterID instMasterId() { return _instMasterId; }
/**
- * Get a master port on this MemObject. This method is virtual to allow
- * the subclasses of the BaseCPU to override it. All CPUs have a
- * data and instruction port, but the Atomic CPU (in its current
- * form) adds a port directly connected to the memory and has to
- * override getMasterPort.
- *
- * This method uses getDataPort and getInstPort to resolve the two
- * ports.
+ * Get a master port on this CPU. All CPUs have a data and
+ * instruction port, and this method uses getDataPort and
+ * getInstPort of the subclasses to resolve the two ports.
*
* @param if_name the port name
* @param idx ignored index
*
* @return a reference to the port with the given name
*/
- virtual MasterPort &getMasterPort(const std::string &if_name,
- int idx = -1);
+ MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
// Tick currentTick;
inline Tick frequency() const { return SimClock::Frequency / clock; }
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 1199f35e1..54daaec63 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -34,4 +46,4 @@ class AtomicSimpleCPU(BaseSimpleCPU):
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
- physmem_port = MasterPort("Physical Memory Port")
+ fastmem = Param.Bool(False, "Access memory directly")
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index d7ad07a5e..41bcf9268 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -39,6 +51,7 @@
#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "mem/physical.hh"
#include "params/AtomicSimpleCPU.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
@@ -65,17 +78,6 @@ AtomicSimpleCPU::TickEvent::description() const
return "AtomicSimpleCPU tick";
}
-MasterPort &
-AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
-{
- if (if_name == "physmem_port") {
- hasPhysMemPort = true;
- return physmemPort;
- } else {
- return BaseCPU::getMasterPort(if_name, idx);
- }
-}
-
void
AtomicSimpleCPU::init()
{
@@ -93,8 +95,8 @@ AtomicSimpleCPU::init()
}
}
- if (hasPhysMemPort) {
- AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
+ if (fastmem) {
+ AddrRangeList pmAddrList = system->physmem->getAddrRanges();
physMemAddr = *pmAddrList.begin();
}
// Atomic doesn't do MT right now, so contextId == threadId
@@ -108,7 +110,7 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
- physmemPort(name() + "-iport", this), hasPhysMemPort(false)
+ fastmem(p->fastmem)
{
_status = Idle;
}
@@ -281,8 +283,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
if (req->isMmappedIpr())
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
else {
- if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
- dcache_latency += physmemPort.sendAtomic(&pkt);
+ if (fastmem && pkt.getAddr() == physMemAddr)
+ dcache_latency += system->physmem->doAtomicAccess(&pkt);
else
dcache_latency += dcachePort.sendAtomic(&pkt);
}
@@ -383,8 +385,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
- if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
- dcache_latency += physmemPort.sendAtomic(&pkt);
+ if (fastmem && pkt.getAddr() == physMemAddr)
+ dcache_latency += system->physmem->doAtomicAccess(&pkt);
else
dcache_latency += dcachePort.sendAtomic(&pkt);
}
@@ -479,8 +481,9 @@ AtomicSimpleCPU::tick()
Packet::Broadcast);
ifetch_pkt.dataStatic(&inst);
- if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
- icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
+ if (fastmem && ifetch_pkt.getAddr() == physMemAddr)
+ icache_latency =
+ system->physmem->doAtomicAccess(&ifetch_pkt);
else
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 126cd3765..c0112836a 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -90,8 +102,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
AtomicCPUPort icachePort;
AtomicCPUPort dcachePort;
- CpuPort physmemPort;
- bool hasPhysMemPort;
+ bool fastmem;
Request ifetch_req;
Request data_read_req;
Request data_write_req;
@@ -111,13 +122,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
- /**
- * Override the getMasterPort of the BaseCPU so that we can
- * provide the physmemPort, unique to the Atomic CPU.
- */
- virtual MasterPort &getMasterPort(const std::string &if_name,
- int idx = -1);
-
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual void resume();
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 19:10:51 +0000