diff options
| -rw-r--r-- | configs/splash2/cluster.py | 1 | ||||
| -rw-r--r-- | configs/splash2/run.py | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py index 77591dc62..e8c471eaa 100644 --- a/configs/splash2/cluster.py +++ b/configs/splash2/cluster.py @@ -234,7 +234,6 @@ for cluster in clusters: for cpu in cluster.cpus: cpu.icache_port = cluster.clusterbus.port cpu.dcache_port = cluster.clusterbus.port - cpu.mem = cluster.l1 # ---------------------- # Define the root diff --git a/configs/splash2/run.py b/configs/splash2/run.py index 24faade17..8d42b3ab8 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -217,7 +217,6 @@ system.l2.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), L1(size = options.l1size, assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2bus) |