diff options
| -rw-r--r-- | arch/alpha/linux/system.cc | 2 | ||||
| -rw-r--r-- | cpu/simple/cpu.cc | 20 | ||||
| -rw-r--r-- | mem/bus.cc | 12 | ||||
| -rw-r--r-- | mem/port.cc | 2 | ||||
| -rw-r--r-- | mem/request.hh | 6 |
5 files changed, 28 insertions, 14 deletions
diff --git a/arch/alpha/linux/system.cc b/arch/alpha/linux/system.cc index edd2cdaf1..cdb96096c 100644 --- a/arch/alpha/linux/system.cc +++ b/arch/alpha/linux/system.cc @@ -73,7 +73,7 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p) * kernel arguments directly into the kernel's memory. */ virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(), - CommandLineSize); + params()->boot_osflags.length()+1); /** * find the address of the est_cycle_freq variable and insert it diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 6fbf9d077..ca88b0701 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -662,6 +662,11 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (data_write_req->getFlags() & UNCACHEABLE) recordEvent("Uncached Write"); + // @todo this is a hack and only works on uniprocessor systems some one else + // can implement LL/SC. + if (data_write_req->getFlags() & LOCKED) + *res = 1; + // If the write needs to have a fault on the access, consider calling // changeStatus() and changing it to "bad addr write" or something. return fault; @@ -957,11 +962,6 @@ SimpleCPU::tick() // Try to fetch an instruction // set up memory request for instruction fetch -#if FULL_SYSTEM -#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 -#else -#define IFETCH_FLAGS(pc) 0 -#endif DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(), cpuXC->readNextPC(),cpuXC->readNextNPC()); @@ -971,12 +971,14 @@ SimpleCPU::tick() ifetch_req->setSize(sizeof(MachInst)); #endif + ifetch_req->reset(true); ifetch_req->setVaddr(cpuXC->readPC() & ~3); ifetch_req->setTime(curTick); - -/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), - IFETCH_FLAGS(xc->regs.pc)); -*/ +#if FULL_SYSTEM + ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0); +#else + ifetch_req->setFlags(0); +#endif fault = cpuXC->translateInstReq(ifetch_req); diff --git a/mem/bus.cc b/mem/bus.cc index 8e8bc2203..8031dae96 100644 --- a/mem/bus.cc +++ b/mem/bus.cc @@ -31,7 +31,8 @@ */ -#include "bus.hh" +#include "base/trace.hh" +#include "mem/bus.hh" #include "sim/builder.hh" /** Function called by the port when the bus is recieving a Timing @@ -57,8 +58,11 @@ Bus::findPort(Addr addr, int id) dest_id = portList[i].portId; found = true; } + i++; } - assert(dest_id != -1 && "Unable to find destination"); + if (dest_id == -1) + panic("Unable to find destination for addr: %llx", addr); + // we shouldn't be sending this back to where it came from assert(dest_id != id); @@ -99,11 +103,15 @@ Bus::recvStatusChange(Port::Status status, int id) assert(snoops.size() == 0); // or multiple ranges assert(ranges.size() == 1); + DevMap dm; dm.portId = id; dm.range = ranges.front(); + DPRINTF(MMU, "Adding range %llx - %llx for id %d\n", dm.range.start, + dm.range.end, id); portList.push_back(dm); + DPRINTF(MMU, "port list has %d entries\n", portList.size()); } void diff --git a/mem/port.cc b/mem/port.cc index d19d8146c..d312f3e3c 100644 --- a/mem/port.cc +++ b/mem/port.cc @@ -72,5 +72,5 @@ Port::memsetBlob(Addr addr, uint8_t val, int size) memset(buf, val, size); blobHelper(addr, buf, size, Write); - delete buf; + delete [] buf; } diff --git a/mem/request.hh b/mem/request.hh index 90c46646e..6bcfd9c5b 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -63,9 +63,13 @@ class Request { //@todo Make Accesor functions, make these private. public: - /** Cunstructor, needs a bool to signify if it is/isn't Cpu Request. */ + /** Constructor, needs a bool to signify if it is/isn't Cpu Request. */ Request(bool isCpu); + /** reset the request to it's initial state so it can be reused by the + * CPU.*/ + void reset(bool isCpu); + //First non-cpu request fields private: /** The physical address of the request. */ |