summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/arch/mips/mmaped_ipr.hh3
-rw-r--r--src/arch/sparc/miscregfile.cc18
-rw-r--r--src/cpu/exetrace.cc2
3 files changed, 18 insertions, 5 deletions
diff --git a/src/arch/mips/mmaped_ipr.hh b/src/arch/mips/mmaped_ipr.hh
index 041c76fdc..fa82a645c 100644
--- a/src/arch/mips/mmaped_ipr.hh
+++ b/src/arch/mips/mmaped_ipr.hh
@@ -37,8 +37,10 @@
* ISA-specific helper functions for memory mapped IPR accesses.
*/
+#include "base/misc.hh"
#include "mem/packet.hh"
+class ThreadContext;
namespace MipsISA
{
@@ -48,7 +50,6 @@ handleIprRead(ThreadContext *xc, Packet *pkt)
panic("No implementation for handleIprRead in MIPS\n");
}
-
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 5bc11aae6..53559c072 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -341,7 +341,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
- case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
@@ -357,9 +356,16 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
+ case MISCREG_HPSTATE:
return readFSRegWithEffect(miscReg, tc);
#else
- panic("Accessing Fullsystem register is SE mode\n");
+ case MISCREG_HPSTATE:
+ //HPSTATE is special because because sometimes in privilege checks for instructions
+ //it will read HPSTATE to make sure the priv. level is ok
+ //So, we'll just have to tell it it isn't, instead of panicing.
+ return 0;
+
+ panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
#endif
}
@@ -633,7 +639,6 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_SOFTINT:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
- case MISCREG_HPSTATE:
case MISCREG_HINTP:
case MISCREG_HTSTATE:
case MISCREG_HTBA:
@@ -649,10 +654,15 @@ void MiscRegFile::setRegWithEffect(int miscReg,
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
+ case MISCREG_HPSTATE:
setFSRegWithEffect(miscReg, val, tc);
return;
#else
- panic("Accessing Fullsystem register is SE mode\n");
+ case MISCREG_HPSTATE:
+ //HPSTATE is special because normal trap processing saves HPSTATE when
+ //it goes into a trap, and restores it when it returns.
+ return;
+ panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
#endif
}
setReg(miscReg, val);
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 316716540..3fe40b4c1 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -57,7 +57,9 @@
using namespace std;
using namespace TheISA;
+#if THE_ISA == SPARC_ISA && FULL_SYSTEM
static int diffcount = 0;
+#endif
namespace Trace {
SharedData *shared_data = NULL;