diff options
| -rw-r--r-- | src/cpu/o3/inst_queue.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 7 |
2 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index c6c55d08a..23d8d416c 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -437,6 +437,9 @@ class InstructionQueue /** The number of physical registers in the CPU. */ unsigned numPhysRegs; + /** Number of instructions currently in flight to FUs */ + int wbOutstanding; + /** Delay between commit stage and the IQ. * @todo: Make there be a distinction between the delays within IEW. */ diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 6a76b49d0..33e523f4d 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -415,6 +415,7 @@ InstructionQueue<Impl>::resetState() deferredMemInsts.clear(); blockedMemInsts.clear(); retryMemInsts.clear(); + wbOutstanding = 0; } template <class Impl> @@ -444,7 +445,9 @@ template <class Impl> bool InstructionQueue<Impl>::isDrained() const { - bool drained = dependGraph.empty() && instsToExecute.empty(); + bool drained = dependGraph.empty() && + instsToExecute.empty() && + wbOutstanding == 0; for (ThreadID tid = 0; tid < numThreads; ++tid) drained = drained && memDepUnit[tid].isDrained(); @@ -723,6 +726,7 @@ InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) assert(!cpu->switchedOut()); // The CPU could have been sleeping until this op completed (*extremely* // long latency op). Wake it if it was. This may be overkill. + --wbOutstanding; iewStage->wakeCPU(); if (fu_idx > -1) @@ -823,6 +827,7 @@ InstructionQueue<Impl>::scheduleReadyInsts() } else { Cycles issue_latency = fuPool->getIssueLatency(op_class); // Generate completion event for the FU + ++wbOutstanding; FUCompletion *execution = new FUCompletion(issuing_inst, idx, this); |