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-rw-r--r--src/python/m5/objects/BaseCPU.py2
-rw-r--r--tests/SConscript5
2 files changed, 4 insertions, 3 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 7906156a2..01458aeb4 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -49,5 +49,5 @@ class BaseCPU(SimObject):
self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c
- self.l2cache.cpu_side = toL2Bus.port
+ self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side']
diff --git a/tests/SConscript b/tests/SConscript
index 8720939de..d5968d3e3 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -61,8 +61,9 @@ def check_test(target, source, env):
# Exclude m5stats.txt since we will use diff-out on that.
Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' +
'-I "^command line:" ' + # for stdout file
- '-I "^M5 compiled on" ' + # for stderr file
- '-I "^M5 simulation started" ' + # for stderr file
+ '-I "^M5 compiled " ' + # for stderr file
+ '-I "^M5 started " ' + # for stderr file
+ '-I "^M5 executing on " ' + # for stderr file
'-I "^Simulation complete at" ' + # for stderr file
'-I "^Listening for" ' + # for stderr file
'--exclude=m5stats.txt --exclude=SCCS ' +