diff options
| -rw-r--r-- | src/arch/arm/isa.cc | 54 | ||||
| -rw-r--r-- | src/arch/arm/isa.hh | 3 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.cc | 20 |
3 files changed, 55 insertions, 22 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 4d27c9a22..1f3f53657 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1145,6 +1145,19 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) hyp = 1; tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); return; + case MISCREG_TLBIIPAS2L: + case MISCREG_TLBIIPAS2LIS: + // mcr tlbiipas2l(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. + case MISCREG_TLBIIPAS2: + case MISCREG_TLBIIPAS2IS: + assert32(tc); + target_el = 1; // EL 0 and 1 are handled together + scr = readMiscReg(MISCREG_SCR, tc); + secure_lookup = haveSecurity && !scr.ns; + tlbiIPA(tc, newVal, secure_lookup, target_el); + return; // TLBI by address and asid, EL0&1, instruction side only case MISCREG_ITLBIMVA: assert32(tc); @@ -1330,23 +1343,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) target_el = 1; // EL 0 and 1 are handled together scr = readMiscReg(MISCREG_SCR, tc); secure_lookup = haveSecurity && !scr.ns; - sys = tc->getSystemPtr(); - for (x = 0; x < sys->numContexts(); x++) { - oc = sys->getThreadContext(x); - Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; - getITBPtr(oc)->flushIpaVmid(ipa, - secure_lookup, false, target_el); - getDTBPtr(oc)->flushIpaVmid(ipa, - secure_lookup, false, target_el); - - CheckerCPU *checker = oc->getCheckerCpuPtr(); - if (checker) { - getITBPtr(checker)->flushIpaVmid(ipa, - secure_lookup, false, target_el); - getDTBPtr(checker)->flushIpaVmid(ipa, - secure_lookup, false, target_el); - } - } + tlbiIPA(tc, newVal, secure_lookup, target_el); return; case MISCREG_ACTLR: warn("Not doing anything for write of miscreg ACTLR\n"); @@ -1877,6 +1874,29 @@ ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, } } +void +ISA::tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, + uint8_t target_el) +{ + System *sys = tc->getSystemPtr(); + for (auto x = 0; x < sys->numContexts(); x++) { + tc = sys->getThreadContext(x); + Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; + getITBPtr(tc)->flushIpaVmid(ipa, + secure_lookup, false, target_el); + getDTBPtr(tc)->flushIpaVmid(ipa, + secure_lookup, false, target_el); + + CheckerCPU *checker = tc->getCheckerCpuPtr(); + if (checker) { + getITBPtr(checker)->flushIpaVmid(ipa, + secure_lookup, false, target_el); + getDTBPtr(checker)->flushIpaVmid(ipa, + secure_lookup, false, target_el); + } + } +} + BaseISADevice & ISA::getGenericTimer(ThreadContext *tc) { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index aa905e500..f36bc89ca 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -401,6 +401,9 @@ namespace ArmISA void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, uint8_t target_el); + void tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, + uint8_t target_el); + public: void clear(); void clear64(const ArmISAParams *p); diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 5a1ef5a6a..e14be7fd4 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -488,7 +488,14 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) break; } } else if (opc1 == 4) { - if (crm == 3) { + if (crm == 0) { + switch (opc2) { + case 1: + return MISCREG_TLBIIPAS2IS; + case 5: + return MISCREG_TLBIIPAS2LIS; + } + } else if (crm == 3) { switch (opc2) { case 0: return MISCREG_TLBIALLHIS; @@ -499,6 +506,13 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) case 5: return MISCREG_TLBIMVALHIS; } + } else if (crm == 4) { + switch (opc2) { + case 1: + return MISCREG_TLBIIPAS2; + case 5: + return MISCREG_TLBIIPAS2L; + } } else if (crm == 7) { switch (opc2) { case 0: @@ -2932,10 +2946,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIMVAAL) .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIIPAS2IS) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2LIS) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIALLHIS) .monNonSecureWrite().hypWrite(); @@ -2946,10 +2958,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIMVALHIS) .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2L) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIALLH) .monNonSecureWrite().hypWrite(); |