diff options
55 files changed, 506 insertions, 306 deletions
diff --git a/SConscript b/SConscript index 966cb6d3e..540876699 100644 --- a/SConscript +++ b/SConscript @@ -305,23 +305,23 @@ syscall_emulation_sources = Split(''' # time. These will have to go away if we want to build a binary that # supports multiple ISAs. -targetarch_files = Split(''' - alpha_linux_process.hh - alpha_memory.hh - alpha_tru64_process.hh - aout_machdep.h - arguments.hh - ecoff_machdep.h - ev5.hh - faults.hh - stacktrace.hh - vtophys.hh - ''') +#targetarch_files = Split(''' +# alpha_linux_process.hh +# alpha_memory.hh +# alpha_tru64_process.hh +# aout_machdep.h +# arguments.hh +# ecoff_machdep.h +# ev5.hh +# faults.hh +# stacktrace.hh +# vtophys.hh +# ''') # Set up bridging headers to the architecture specific versions -for f in targetarch_files: - env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f), - '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f)) +#for f in targetarch_files: +# env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f), +# '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f)) # Add a flag defining what THE_ISA should be for all compilation env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())]) diff --git a/arch/SConscript b/arch/SConscript index 142bd763b..5783b39dd 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -46,6 +46,16 @@ sources = [] # List of headers to generate isa_switch_hdrs = Split(''' isa_traits.hh + linux_process.hh + tru64_process.hh + tlb.hh + aout_machdep.h + ecoff_machdep.h + arguments.hh + stacktrace.hh + vtophys.hh + faults.hh + ev5.hh ''') # Generate the header. target[0] is the full path of the output diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript index 050dfb9cf..3b0e69b7a 100644 --- a/arch/alpha/SConscript +++ b/arch/alpha/SConscript @@ -50,7 +50,7 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - alpha_memory.cc + tlb.cc arguments.cc ev5.cc osfpal.cc @@ -61,9 +61,9 @@ full_system_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' - alpha_common_syscall_emul.cc - alpha_linux_process.cc - alpha_tru64_process.cc + common_syscall_emul.cc + linux_process.cc + tru64_process.cc ''') # Set up complete list of sources based on configuration. diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 14b87b16f..ca26fc257 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/tlb.hh" #include "arch/alpha/isa_traits.hh" #include "arch/alpha/osfpal.hh" #include "base/kgdb.h" @@ -79,25 +79,10 @@ AlphaISA::initCPU(RegFile *regs, int cpuId) regs->intRegFile[16] = cpuId; regs->intRegFile[0] = cpuId; - regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault); + regs->pc = regs->ipr[IPR_PAL_BASE] + (new ResetFault)->vect(); regs->npc = regs->pc + sizeof(MachInst); } -//////////////////////////////////////////////////////////////////////// -// -// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE -// -const Addr -AlphaISA::fault_addr(Fault fault) -{ - //Check for the system wide faults - if(fault == NoFault) return 0x0000; - else if(fault == MachineCheckFault) return 0x0401; - else if(fault == AlignmentFault) return 0x0301; - //Deal with the alpha specific faults - return ((AlphaFault*)fault)->vect; -}; - const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0, @@ -162,7 +147,7 @@ AlphaISA::processInterrupts(CPU *cpu) if (ipl && ipl > ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - cpu->trap(InterruptFault); + cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); } @@ -181,33 +166,34 @@ AlphaISA::zeroRegisters(CPU *cpu) } void -ExecContext::ev5_trap(Fault fault) +ExecContext::ev5_temp_trap(Fault fault) { - DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc); - cpu->recordEvent(csprintf("Fault %s", fault->name)); + DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc); + cpu->recordEvent(csprintf("Fault %s", fault->name())); assert(!misspeculating()); kernelStats->fault(fault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); AlphaISA::InternalProcReg *ipr = regs.ipr; // exception restart address - if (fault != InterruptFault || !inPalMode()) + if (!fault->isA<InterruptFault>() || !inPalMode()) ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc; - if (fault == PalFault || fault == ArithmeticFault /* || + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || fault == InterruptFault && !inPalMode() */) { - // traps... skip faulting instruction + // traps... skip faulting instruction. ipr[AlphaISA::IPR_EXC_ADDR] += 4; } if (!inPalMode()) AlphaISA::swap_palshadow(®s, true); - regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault); + regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + + (dynamic_cast<AlphaFault *>(fault.get()))->vect(); regs.npc = regs.pc + sizeof(MachInst); } @@ -218,11 +204,11 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) InternalProcReg *ipr = regs->ipr; bool use_pc = (fault == NoFault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("arithmetic faults NYI..."); // compute exception restart address - if (use_pc || fault == PalFault || fault == ArithmeticFault) { + if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) { // traps... skip faulting instruction ipr[IPR_EXC_ADDR] = regs->pc + 4; } else { @@ -232,7 +218,8 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) // jump to expection address (PAL PC bit set here as well...) if (!use_pc) - regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault); + regs->npc = ipr[IPR_PAL_BASE] + + (dynamic_cast<AlphaFault *>(fault.get()))->vect(); else regs->npc = ipr[IPR_PAL_BASE] + pc; @@ -245,7 +232,7 @@ ExecContext::hwrei() uint64_t *ipr = regs.ipr; if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); @@ -357,12 +344,12 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_IAP: case AlphaISA::IPR_ITB_IA: case AlphaISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; default: // invalid IPR - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; } @@ -527,7 +514,7 @@ ExecContext::setIpr(int idx, uint64_t val) case AlphaISA::IPR_ITB_PTE_TEMP: case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; case AlphaISA::IPR_HWINT_CLR: case AlphaISA::IPR_SL_XMIT: @@ -629,7 +616,7 @@ ExecContext::setIpr(int idx, uint64_t val) default: // invalid IPR - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } // no error... diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc index fa4950198..78613761d 100644 --- a/arch/alpha/faults.cc +++ b/arch/alpha/faults.cc @@ -27,37 +27,95 @@ */ #include "arch/alpha/faults.hh" +#include "cpu/exec_context.hh" -ResetFaultType * const ResetFault = - new ResetFaultType("reset", 1, 0x0001); -ArithmeticFaultType * const ArithmeticFault = - new ArithmeticFaultType("arith", 3, 0x0501); -InterruptFaultType * const InterruptFault = - new InterruptFaultType("interrupt", 4, 0x0101); -NDtbMissFaultType * const NDtbMissFault = - new NDtbMissFaultType("dtb_miss_single", 5, 0x0201); -PDtbMissFaultType * const PDtbMissFault = - new PDtbMissFaultType("dtb_miss_double", 6, 0x0281); -DtbPageFaultType * const DtbPageFault = - new DtbPageFaultType("dfault", 8, 0x0381); -DtbAcvFaultType * const DtbAcvFault = - new DtbAcvFaultType("dfault", 9, 0x0381); -ItbMissFaultType * const ItbMissFault = - new ItbMissFaultType("itbmiss", 10, 0x0181); -ItbPageFaultType * const ItbPageFault = - new ItbPageFaultType("itbmiss", 11, 0x0181); -ItbAcvFaultType * const ItbAcvFault = - new ItbAcvFaultType("iaccvio", 12, 0x0081); -UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault = - new UnimplementedOpcodeFaultType("opdec", 13, 0x0481); -FloatEnableFaultType * const FloatEnableFault = - new FloatEnableFaultType("fen", 14, 0x0581); -PalFaultType * const PalFault = - new PalFaultType("pal", 15, 0x2001); -IntegerOverflowFaultType * const IntegerOverflowFault = - new IntegerOverflowFaultType("intover", 16, 0x0501); - -Fault * ListOfFaults[] = { +namespace AlphaISA +{ + +FaultVect AlphaMachineCheckFault::_vect = 0x0401; +FaultStat AlphaMachineCheckFault::_stat; + +FaultVect AlphaAlignmentFault::_vect = 0x0301; +FaultStat AlphaAlignmentFault::_stat; + +FaultName ResetFault::_name = "reset"; +FaultVect ResetFault::_vect = 0x0001; +FaultStat ResetFault::_stat; + +FaultName ArithmeticFault::_name = "arith"; +FaultVect ArithmeticFault::_vect = 0x0501; +FaultStat ArithmeticFault::_stat; + +FaultName InterruptFault::_name = "interrupt"; +FaultVect InterruptFault::_vect = 0x0101; +FaultStat InterruptFault::_stat; + +FaultName NDtbMissFault::_name = "dtb_miss_single"; +FaultVect NDtbMissFault::_vect = 0x0201; +FaultStat NDtbMissFault::_stat; + +FaultName PDtbMissFault::_name = "dtb_miss_double"; +FaultVect PDtbMissFault::_vect = 0x0281; +FaultStat PDtbMissFault::_stat; + +FaultName DtbPageFault::_name = "dfault"; +FaultVect DtbPageFault::_vect = 0x0381; +FaultStat DtbPageFault::_stat; + +FaultName DtbAcvFault::_name = "dfault"; +FaultVect DtbAcvFault::_vect = 0x0381; +FaultStat DtbAcvFault::_stat; + +FaultName ItbMissFault::_name = "itbmiss"; +FaultVect ItbMissFault::_vect = 0x0181; +FaultStat ItbMissFault::_stat; + +FaultName ItbPageFault::_name = "itbmiss"; +FaultVect ItbPageFault::_vect = 0x0181; +FaultStat ItbPageFault::_stat; + +FaultName ItbAcvFault::_name = "iaccvio"; +FaultVect ItbAcvFault::_vect = 0x0081; +FaultStat ItbAcvFault::_stat; + +FaultName UnimplementedOpcodeFault::_name = "opdec"; +FaultVect UnimplementedOpcodeFault::_vect = 0x0481; +FaultStat UnimplementedOpcodeFault::_stat; + +FaultName FloatEnableFault::_name = "fen"; +FaultVect FloatEnableFault::_vect = 0x0581; +FaultStat FloatEnableFault::_stat; + +FaultName PalFault::_name = "pal"; +FaultVect PalFault::_vect = 0x2001; +FaultStat PalFault::_stat; + +FaultName IntegerOverflowFault::_name = "intover"; +FaultVect IntegerOverflowFault::_vect = 0x0501; +FaultStat IntegerOverflowFault::_stat; + +#if FULL_SYSTEM + +void AlphaFault::ev5_trap(ExecContext * xc) +{ + xc->ev5_temp_trap(this); +} + +void AlphaMachineCheckFault::ev5_trap(ExecContext * xc) +{ + xc->ev5_temp_trap(this); +} + +void AlphaAlignmentFault::ev5_trap(ExecContext * xc) +{ + xc->ev5_temp_trap(this); +} + +#endif + +} // namespace AlphaISA + +/*Fault * ListOfFaults[] = { (Fault *)&NoFault, (Fault *)&ResetFault, (Fault *)&MachineCheckFault, @@ -77,4 +135,4 @@ Fault * ListOfFaults[] = { (Fault *)&IntegerOverflowFault, }; -int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *); +int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/ diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh index 3e25adc4e..156faa8fb 100644 --- a/arch/alpha/faults.hh +++ b/arch/alpha/faults.hh @@ -30,131 +30,231 @@ #define __ALPHA_FAULTS_HH__ #include "sim/faults.hh" -#include "arch/isa_traits.hh" //For the Addr type -class AlphaFault : public FaultBase +// The design of the "name" and "vect" functions is in sim/faults.hh + +namespace AlphaISA +{ + +typedef const Addr FaultVect; + +class AlphaFault : public virtual FaultBase { public: - AlphaFault(char * newName, int newId, Addr newVect) - : FaultBase(newName, newId), vect(newVect) - {;} +#if FULL_SYSTEM + void ev5_trap(ExecContext * xc); +#endif + virtual FaultVect vect() = 0; +}; - Addr vect; +class AlphaMachineCheckFault : + public MachineCheckFault, + public AlphaFault +{ + private: + static FaultVect _vect; + static FaultStat _stat; + public: +#if FULL_SYSTEM + void ev5_trap(ExecContext * xc); +#endif + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} }; -extern class ResetFaultType : public AlphaFault +class AlphaAlignmentFault : + public AlignmentFault, + public AlphaFault { + private: + static FaultVect _vect; + static FaultStat _stat; public: - ResetFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ResetFault; +#if FULL_SYSTEM + void ev5_trap(ExecContext * xc); +#endif + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ArithmeticFaultType : public AlphaFault +static inline Fault genMachineCheckFault() { + return new AlphaMachineCheckFault; +} + +static inline Fault genAlignmentFault() +{ + return new AlphaAlignmentFault; +} + +class ResetFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ArithmeticFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ArithmeticFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class InterruptFaultType : public AlphaFault +class ArithmeticFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - InterruptFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const InterruptFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class NDtbMissFaultType : public AlphaFault +class InterruptFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - NDtbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const NDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class PDtbMissFaultType : public AlphaFault +class NDtbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - PDtbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const PDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class DtbPageFaultType : public AlphaFault +class PDtbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - DtbPageFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const DtbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class DtbAcvFaultType : public AlphaFault +class DtbPageFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - DtbAcvFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const DtbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; + +class DtbAcvFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbMissFaultType : public AlphaFault +class ItbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbPageFaultType : public AlphaFault +class ItbPageFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbPageFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbAcvFaultType : public AlphaFault +class ItbAcvFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbAcvFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class UnimplementedOpcodeFaultType : public AlphaFault +class UnimplementedOpcodeFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const UnimplementedOpcodeFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class FloatEnableFaultType : public AlphaFault +class FloatEnableFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - FloatEnableFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const FloatEnableFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class PalFaultType : public AlphaFault +class PalFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - PalFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const PalFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class IntegerOverflowFaultType : public AlphaFault +class IntegerOverflowFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - IntegerOverflowFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const IntegerOverflowFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern Fault * ListOfFaults[]; -extern int NumFaults; +} // AlphaISA namespace #endif // __FAULTS_HH__ diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa index 37b15416b..cdcf96215 100644 --- a/arch/alpha/isa/decoder.isa +++ b/arch/alpha/isa/decoder.isa @@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() { // signed overflow occurs when operands have same sign // and sign of result does not match. if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp; }}); 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); @@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() { // signed overflow occurs when operands have same sign // and sign of result does not match. if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = tmp; }}); 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); @@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() { // sign bit of the subtrahend (Rb), i.e., if the initial // signs are the *same* then no overflow can occur if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp; }}); 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); @@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() { // sign bit of the subtrahend (Rb), i.e., if the initial // signs are the *same* then no overflow can occur if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = tmp; }}); 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); @@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() { // checking the upper 33 bits for all 0s or all 1s. uint64_t sign_bits = tmp<63:31>; if (sign_bits != 0 && sign_bits != mask(33)) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp<31:0>; }}, IntMultOp); 0x60: mulqv({{ @@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() { // the lower 64 if (!((hi == 0 && lo<63:> == 0) || (hi == mask(64) && lo<63:> == 1))) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = lo; }}, IntMultOp); } @@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() { #if SS_COMPATIBLE_FP 0x0b: sqrts({{ if (Fb < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc = sqrt(Fb); }}, FloatSqrtOp); #else 0x0b: sqrts({{ if (Fb.sf < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc.sf = sqrt(Fb.sf); }}, FloatSqrtOp); #endif 0x2b: sqrtt({{ if (Fb < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc = sqrt(Fb); }}, FloatSqrtOp); } @@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() { // checking the upper 33 bits for all 0s or all 1s. uint64_t sign_bits = Fb.uq<63:31>; if (sign_bits != 0 && sign_bits != mask(33)) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); }}); @@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() { && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { // invalid pal function code, or attempt to do privileged // PAL call in non-kernel mode - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { // check to see if simulator wants to do something special @@ -729,7 +729,7 @@ decode OPCODE default Unknown::unknown() { 0x19: hw_mfpr({{ // this instruction is only valid in PAL mode if (!xc->inPalMode()) { - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { Ra = xc->readIpr(ipr_index, fault); @@ -738,7 +738,7 @@ decode OPCODE default Unknown::unknown() { 0x1d: hw_mtpr({{ // this instruction is only valid in PAL mode if (!xc->inPalMode()) { - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { xc->setIpr(ipr_index, Ra); diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa index 7e81fb830..2ee714b0f 100644 --- a/arch/alpha/isa/fp.isa +++ b/arch/alpha/isa/fp.isa @@ -36,7 +36,7 @@ output exec {{ { Fault fault = NoFault; // dummy... this ipr access should not fault if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) { - fault = FloatEnableFault; + fault = new FloatEnableFault; } return fault; } diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa index de4ac3eaf..09df39706 100644 --- a/arch/alpha/isa/unimp.isa +++ b/arch/alpha/isa/unimp.isa @@ -111,7 +111,7 @@ output exec {{ { panic("attempt to execute unimplemented instruction '%s' " "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } Fault diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa index 4601b3684..47d166255 100644 --- a/arch/alpha/isa/unknown.isa +++ b/arch/alpha/isa/unknown.isa @@ -42,7 +42,7 @@ output exec {{ { panic("attempt to execute unknown instruction " "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } }}; diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/linux_process.cc index 16ebcca7b..0b193fb55 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/linux_process.cc @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/alpha_common_syscall_emul.hh" -#include "arch/alpha/alpha_linux_process.hh" +#include "arch/alpha/common_syscall_emul.hh" +#include "arch/alpha/linux_process.hh" #include "arch/alpha/isa_traits.hh" #include "base/trace.hh" diff --git a/arch/alpha/alpha_linux_process.hh b/arch/alpha/linux_process.hh index 7de1b1ac1..7de1b1ac1 100644 --- a/arch/alpha/alpha_linux_process.hh +++ b/arch/alpha/linux_process.hh diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/tlb.cc index d00186d95..8297737bd 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/tlb.cc @@ -30,7 +30,7 @@ #include <string> #include <vector> -#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/tlb.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -322,7 +322,7 @@ AlphaITB::translate(MemReqPtr &req) const if (!validVirtualAddress(req->vaddr)) { fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } @@ -339,7 +339,7 @@ AlphaITB::translate(MemReqPtr &req) const AlphaISA::mode_kernel) { fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } req->paddr = req->vaddr & PAddrImplMask; @@ -360,7 +360,7 @@ AlphaITB::translate(MemReqPtr &req) const if (!pte) { fault(req->vaddr, req->xc); misses++; - return ItbPageFault; + return new ItbPageFault; } req->paddr = (pte->ppn << AlphaISA::PageShift) + @@ -371,7 +371,7 @@ AlphaITB::translate(MemReqPtr &req) const // instruction access fault fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } hits++; @@ -380,7 +380,7 @@ AlphaITB::translate(MemReqPtr &req) const // check that the physical address is ok (catch bad physical addresses) if (req->paddr & ~PAddrImplMask) - return MachineCheckFault; + return genMachineCheckFault(); checkCacheability(req); @@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, write ? MM_STAT_WR_MASK : 0); DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, req->size); - return AlignmentFault; + return genAlignmentFault(); } if (pc & 0x1) { @@ -530,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const MM_STAT_ACV_MASK); if (write) { write_acv++; } else { read_acv++; } - return DtbPageFault; + return new DtbPageFault; } // Check for "superpage" mapping @@ -547,7 +547,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK)); if (write) { write_acv++; } else { read_acv++; } - return DtbAcvFault; + return new DtbAcvFault; } req->paddr = req->vaddr & PAddrImplMask; @@ -575,7 +575,9 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, (write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK); if (write) { write_misses++; } else { read_misses++; } - return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault; + return (req->flags & VPTE) ? + (Fault)(new PDtbMissFault) : + (Fault)(new NDtbMissFault); } req->paddr = (pte->ppn << AlphaISA::PageShift) + @@ -588,25 +590,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const MM_STAT_ACV_MASK | (pte->fonw ? MM_STAT_FONW_MASK : 0)); write_acv++; - return DtbPageFault; + return new DtbPageFault; } if (pte->fonw) { fault(req, MM_STAT_WR_MASK | MM_STAT_FONW_MASK); write_acv++; - return DtbPageFault; + return new DtbPageFault; } } else { if (!(pte->xre & MODE2MASK(mode))) { fault(req, MM_STAT_ACV_MASK | (pte->fonr ? MM_STAT_FONR_MASK : 0)); read_acv++; - return DtbAcvFault; + return new DtbAcvFault; } if (pte->fonr) { fault(req, MM_STAT_FONR_MASK); read_acv++; - return DtbPageFault; + return new DtbPageFault; } } } @@ -619,7 +621,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const // check that the physical address is ok (catch bad physical addresses) if (req->paddr & ~PAddrImplMask) - return MachineCheckFault; + return genMachineCheckFault(); checkCacheability(req); diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/tlb.hh index de955fa46..de955fa46 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/tlb.hh diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/tru64_process.cc index 8121d3452..90e8b1139 100644 --- a/arch/alpha/alpha_tru64_process.cc +++ b/arch/alpha/tru64_process.cc @@ -27,8 +27,8 @@ */ #include "arch/alpha/isa_traits.hh" -#include "arch/alpha/alpha_common_syscall_emul.hh" -#include "arch/alpha/alpha_tru64_process.hh" +#include "arch/alpha/common_syscall_emul.hh" +#include "arch/alpha/tru64_process.hh" #include "cpu/exec_context.hh" #include "kern/tru64/tru64.hh" #include "mem/functional/functional.hh" diff --git a/arch/alpha/alpha_tru64_process.hh b/arch/alpha/tru64_process.hh index 051760702..051760702 100644 --- a/arch/alpha/alpha_tru64_process.hh +++ b/arch/alpha/tru64_process.hh diff --git a/base/loader/exec_aout.h b/base/loader/exec_aout.h index 76ebe9bb5..3863a92fb 100644 --- a/base/loader/exec_aout.h +++ b/base/loader/exec_aout.h @@ -55,6 +55,6 @@ (N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \ N_GETMAGIC(ex) != ZMAGIC) -#include "targetarch/aout_machdep.h" +#include "arch/aout_machdep.h" #endif /* !_SYS_EXEC_AOUT_H_ */ diff --git a/base/loader/exec_ecoff.h b/base/loader/exec_ecoff.h index 4eece4318..79cd22a6e 100644 --- a/base/loader/exec_ecoff.h +++ b/base/loader/exec_ecoff.h @@ -37,7 +37,7 @@ #ifndef _SYS_EXEC_ECOFF_H_ #define _SYS_EXEC_ECOFF_H_ -#include "targetarch/ecoff_machdep.h" +#include "arch/ecoff_machdep.h" struct ecoff_filehdr { coff_ushort f_magic; /* magic number */ diff --git a/base/refcnt.hh b/base/refcnt.hh index 9d9ed4337..de589f7c5 100644 --- a/base/refcnt.hh +++ b/base/refcnt.hh @@ -29,6 +29,8 @@ #ifndef __REFCNT_HH__ #define __REFCNT_HH__ +#include <stddef.h> //For the NULL macro definition + class RefCounted { private: diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 17ec21fed..24280244f 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -129,7 +129,7 @@ #include "cpu/static_inst.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace std; using namespace TheISA; diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index 86314bef1..5905cdad2 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -36,7 +36,7 @@ #include "base/cprintf.hh" #include "base/trace.hh" -#include "arch/alpha/faults.hh" +#include "arch/faults.hh" #include "cpu/exetrace.hh" #include "mem/mem_req.hh" @@ -45,6 +45,7 @@ #include "cpu/o3/alpha_cpu.hh" using namespace std; +using namespace TheISA; #define NOHASH #ifndef NOHASH @@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars() asid = 0; // Initialize the fault to be unimplemented opcode. - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; ++instcount; @@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) break; default: - fault = MachineCheckFault; + fault = genMachineCheckFault(); break; } diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc index 9bed3ba47..7e8b81e18 100644 --- a/cpu/exec_context.cc +++ b/cpu/exec_context.cc @@ -40,7 +40,7 @@ #include "sim/serialize.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" #else #include "sim/process.hh" #endif @@ -227,7 +227,7 @@ ExecContext::trap(Fault fault) /** @todo: Going to hack it for now. Do a true fixup later. */ #if FULL_SYSTEM - ev5_trap(fault); + fault->ev5_trap(this); #else fatal("fault (%d) detected @ PC 0x%08p", fault, readPC()); #endif diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 3e0d77254..e23370d0b 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -46,7 +46,7 @@ class BaseCPU; #if FULL_SYSTEM #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" +#include "arch/tlb.hh" class FunctionProfile; class ProfileNode; @@ -425,7 +425,7 @@ class ExecContext void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault fault); + void ev5_temp_trap(Fault fault); bool simPalCheck(int palFunc); #endif diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index b35bcf9e3..ea0aae41f 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -280,7 +280,7 @@ class AlphaFullCPU : public FullO3CPU<Impl> #endif - return this->mem->write(req, (T)::htog(data)); + return this->mem->write(req, (T)htog(data)); } template <class T> diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 3547fb1b5..95d2f8f37 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -50,8 +50,8 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 7ec1ba663..9b7cd8a0e 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -280,7 +280,7 @@ AlphaFullCPU<Impl>::hwrei() uint64_t *ipr = getIpr(); if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); @@ -329,21 +329,21 @@ AlphaFullCPU<Impl>::trap(Fault fault) // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); - this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); + DPRINTF(Fault, "Fault %s\n", fault->name()); + this->recordEvent(csprintf("Fault %s", fault->name())); -// kernelStats.fault(fault); + //kernelStats.fault(fault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); AlphaISA::InternalProcReg *ipr = getIpr(); // exception restart address - Get the commit PC - if (fault != InterruptFault || !inPalMode(PC)) + if (!fault->isA<InterruptFault>() || !inPalMode(PC)) ipr[AlphaISA::IPR_EXC_ADDR] = PC; - if (fault == PalFault || fault == ArithmeticFault /* || + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction ipr[AlphaISA::IPR_EXC_ADDR] += 4; @@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault) swapPALShadow(true); this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - AlphaISA::fault_addr(fault) ); + (dynamic_cast<AlphaFault *>(fault.get()))->vect()); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 0a77b83dc..2725684f7 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -30,7 +30,7 @@ #define __BPRED_UNIT_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index e4de1d304..c74c77ddf 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -31,7 +31,7 @@ #include <vector> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 321d61dce..802860ab5 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include "sim/process.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" using namespace EV5; #endif diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index ee7b8858e..3bf96a37b 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -31,14 +31,14 @@ // @todo: Destructor -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/faults.hh" +#include "arch/isa_traits.hh" +#include "arch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" #include "kern/kernel_stats.hh" using namespace EV5; @@ -372,12 +372,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault) case TheISA::IPR_DTB_IAP: case TheISA::IPR_ITB_IA: case TheISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; default: // invalid IPR - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; } @@ -525,7 +525,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) case TheISA::IPR_ITB_PTE_TEMP: case TheISA::IPR_DTB_PTE_TEMP: // read-only registers - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; case TheISA::IPR_HWINT_CLR: case TheISA::IPR_SL_XMIT: @@ -627,7 +627,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) default: // invalid IPR - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } // no error... diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 009a81b98..e7ed3cfe0 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -29,7 +29,7 @@ #ifndef __CPU_OOO_CPU_OOO_IMPL_HH__ #define __CPU_OOO_CPU_OOO_IMPL_HH__ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" template <class Impl> class OoOCPU; diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc index 80cf80fb8..6114a0ca1 100644 --- a/cpu/ozone/ea_list.cc +++ b/cpu/ozone/ea_list.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "cpu/ooo_cpu/ea_list.hh" diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh index def7e67d5..c0eee4bb8 100644 --- a/cpu/ozone/ea_list.hh +++ b/cpu/ozone/ea_list.hh @@ -32,7 +32,7 @@ #include <list> #include <utility> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" /** diff --git a/cpu/profile.hh b/cpu/profile.hh index 18061f9bf..1eb012a27 100644 --- a/cpu/profile.hh +++ b/cpu/profile.hh @@ -33,7 +33,7 @@ #include "cpu/static_inst.hh" #include "sim/host.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" class ProfileNode { diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 944bdbb0a..1f362876f 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -67,9 +67,9 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/stacktrace.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/stacktrace.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM @@ -347,7 +347,7 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(fault != AlignmentFault); + assert(!fault->isAlignmentFault()); if (fault == NoFault) { xc->copySrcAddr = src; @@ -382,7 +382,7 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(fault != AlignmentFault); + assert(!fault->isAlignmentFault()); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; @@ -688,7 +688,7 @@ SimpleCPU::tick() if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - xc->ev5_trap(InterruptFault); + (new InterruptFault)->ev5_trap(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); @@ -812,7 +812,7 @@ SimpleCPU::tick() if (fault != NoFault) { #if FULL_SYSTEM - xc->ev5_trap(fault); + fault->ev5_trap(xc); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); #endif // FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index ed7b1e29b..c58b3c5ba 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -334,7 +334,7 @@ class SimpleCPU : public BaseCPU int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault fault) { fault->ev5_trap(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 2e8bbd1dd..c8327736f 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) } break; default: - return MachineCheckFault; + return genMachineCheckFault(); } return NoFault; @@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) val = *(uint64_t *)data; break; default: - return MachineCheckFault; + return genMachineCheckFault(); } Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 4b08d8497..d6df347bc 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -49,7 +49,7 @@ #include "sim/debug.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" const char *NsRxStateStrings[] = { diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 9427463bf..bdfc6b932 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -260,6 +260,7 @@ class PciDev : public DmaDevice inline Fault PciDev::readBar(MemReqPtr &req, uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return readBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return readBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return readBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return genMachineCheckFault(); } inline Fault PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return writeBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data) return writeBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return writeBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return genMachineCheckFault(); } #endif // __DEV_PCIDEV_HH__ diff --git a/dev/sinic.cc b/dev/sinic.cc index a9363954b..c28ab335b 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -47,7 +47,7 @@ #include "sim/eventq.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace Net; using namespace TheISA; @@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = readBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = writeBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -489,17 +489,35 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - uint32_t reg32 = *(uint32_t *)data; - uint64_t reg64 = *(uint64_t *)data; - VirtualReg &vnic = virtualRegs[index]; - + //These are commmented out because when the DPRINTF below isn't used, + //these values aren't used and gcc issues a warning. With -Werror, + //this prevents compilation. + //uint32_t reg32 = *(uint32_t *)data; + //uint64_t reg64 = *(uint64_t *)data; DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? reg32 : reg64, daddr, - req->paddr, req->vaddr, req->size); + info.name, cpu, info.size == 4 ? + (*(uint32_t *)data) : + (*(uint32_t *)data), + daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); + regWrite(daddr, cpu, data); + + return NoFault; +} + +void +Device::regWrite(Addr daddr, int cpu, const uint8_t *data) +{ + Addr index = daddr >> Regs::VirtualShift; + Addr raddr = daddr & Regs::VirtualMask; + + uint32_t reg32 = *(uint32_t *)data; + uint64_t reg64 = *(uint64_t *)data; + VirtualReg &vnic = virtualRegs[index]; + switch (raddr) { case Regs::Config: changeConfig(reg32); @@ -546,8 +564,6 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) } break; } - - return NoFault; } void diff --git a/kern/freebsd/freebsd_system.cc b/kern/freebsd/freebsd_system.cc index cead8caaf..24d228b5f 100644 --- a/kern/freebsd/freebsd_system.cc +++ b/kern/freebsd/freebsd_system.cc @@ -41,7 +41,7 @@ #include "sim/builder.hh" #include "arch/isa_traits.hh" #include "sim/byteswap.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #define TIMER_FREQUENCY 1193180 diff --git a/kern/kernel_stats.cc b/kern/kernel_stats.cc index 50bbaee00..31a3049f1 100644 --- a/kern/kernel_stats.cc +++ b/kern/kernel_stats.cc @@ -136,7 +136,7 @@ Statistics::regStats(const string &_name) } } - _faults +/* _faults .init(NumFaults) .name(name() + ".faults") .desc("number of faults") @@ -147,7 +147,7 @@ Statistics::regStats(const string &_name) const char *str = (*ListOfFaults[i])->name; if (str) _faults.subname(i, str); - } + }*/ _mode .init(cpu_mode_num) diff --git a/kern/kernel_stats.hh b/kern/kernel_stats.hh index 02d78e4d9..4896a0705 100644 --- a/kern/kernel_stats.hh +++ b/kern/kernel_stats.hh @@ -151,7 +151,7 @@ class Statistics : public Serializable Stats::Vector<> _callpal; Stats::Vector<> _syscall; - Stats::Vector<> _faults; +// Stats::Vector<> _faults; Stats::Vector<> _mode; Stats::Vector<> _modeGood; @@ -178,10 +178,8 @@ class Statistics : public Serializable void hwrei() { _hwrei++; } void fault(Fault fault) { - if(fault == NoFault) _faults[0]++; - else if(fault == MachineCheckFault) _faults[2]++; - else if(fault == AlignmentFault) _faults[7]++; - else _faults[fault->id]++; + if(fault != NoFault) + fault->stat()++; }// FIXME: When there are no generic system fault objects, this will go back to _faults[fault]++; } void swpipl(int ipl); void mode(cpu_mode newmode); diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc index c5a9e184a..eb189658c 100644 --- a/kern/linux/linux_system.cc +++ b/kern/linux/linux_system.cc @@ -46,8 +46,8 @@ #include "sim/builder.hh" #include "sim/byteswap.hh" #include "dev/platform.hh" -#include "targetarch/arguments.hh" -#include "targetarch/vtophys.hh" +#include "arch/arguments.hh" +#include "arch/vtophys.hh" using namespace std; using namespace TheISA; diff --git a/kern/linux/printk.cc b/kern/linux/printk.cc index fbc8bdad1..f5313759b 100644 --- a/kern/linux/printk.cc +++ b/kern/linux/printk.cc @@ -30,7 +30,7 @@ #include <algorithm> #include "base/trace.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" using namespace std; diff --git a/kern/tru64/dump_mbuf.cc b/kern/tru64/dump_mbuf.cc index efdaed62d..10137ceb0 100644 --- a/kern/tru64/dump_mbuf.cc +++ b/kern/tru64/dump_mbuf.cc @@ -34,9 +34,9 @@ #include "cpu/exec_context.hh" #include "kern/tru64/mbuf.hh" #include "sim/host.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" #include "arch/isa_traits.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace TheISA; diff --git a/kern/tru64/printf.cc b/kern/tru64/printf.cc index 12a089c40..77ac17c3a 100644 --- a/kern/tru64/printf.cc +++ b/kern/tru64/printf.cc @@ -32,8 +32,8 @@ #include "base/cprintf.hh" #include "base/trace.hh" #include "sim/host.hh" -#include "targetarch/arguments.hh" -#include "targetarch/vtophys.hh" +#include "arch/arguments.hh" +#include "arch/vtophys.hh" using namespace std; diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc index 2fe6a2dc4..1fd26b87b 100644 --- a/kern/tru64/tru64_events.cc +++ b/kern/tru64/tru64_events.cc @@ -33,7 +33,7 @@ #include "kern/tru64/dump_mbuf.hh" #include "kern/tru64/printf.hh" #include "mem/functional/memory_control.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" #include "arch/isa_traits.hh" using namespace TheISA; diff --git a/kern/tru64/tru64_system.cc b/kern/tru64/tru64_system.cc index ebcdc1553..48e02d90b 100644 --- a/kern/tru64/tru64_system.cc +++ b/kern/tru64/tru64_system.cc @@ -37,7 +37,7 @@ #include "mem/functional/physical.hh" #include "sim/builder.hh" #include "arch/isa_traits.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace std; diff --git a/sim/faults.cc b/sim/faults.cc index 58a631263..78bfc8092 100644 --- a/sim/faults.cc +++ b/sim/faults.cc @@ -28,9 +28,6 @@ #include "sim/faults.hh" -NoFaultType * const NoFault = new NoFaultType("none"); -MachineCheckFaultType * const MachineCheckFault = - new MachineCheckFaultType("mchk"); -AlignmentFaultType * const AlignmentFault = - new AlignmentFaultType("unalign"); +FaultName MachineCheckFault::_name = "mchk"; +FaultName AlignmentFault::_name = "unalign"; diff --git a/sim/faults.hh b/sim/faults.hh index dbec399af..9b8c94cda 100644 --- a/sim/faults.hh +++ b/sim/faults.hh @@ -29,34 +29,63 @@ #ifndef __FAULTS_HH__ #define __FAULTS_HH__ +#include "base/refcnt.hh" +#include "sim/stats.hh" +#include "config/full_system.hh" + +class ExecContext; class FaultBase; -typedef FaultBase * Fault; +typedef RefCountingPtr<FaultBase> Fault; + +typedef const char * FaultName; +typedef Stats::Scalar<> FaultStat; -class FaultBase +// Each class has it's name statically define in _name, +// and has a virtual function to access it's name. +// The function is necessary because otherwise, all objects +// which are being accessed cast as a FaultBase * (namely +// all faults returned using the Fault type) will use the +// generic FaultBase name. + +class FaultBase : public RefCounted { -public: - FaultBase(char * newName, int newId = 0) : name(newName), id(newId) {;} - const char * name; - int id; + public: + virtual FaultName name() = 0; + virtual FaultStat & stat() = 0; +#if FULL_SYSTEM + virtual void ev5_trap(ExecContext * xc) = 0; +#endif + template<typename T> + bool isA() {return dynamic_cast<T *>(this);} + virtual bool isMachineCheckFault() {return false;} + virtual bool isAlignmentFault() {return false;} }; -extern class NoFaultType : public FaultBase -{ -public: - NoFaultType(char * newName) : FaultBase(newName) {;} -} * const NoFault; +FaultBase * const NoFault = 0; -extern class MachineCheckFaultType : public FaultBase +//The ISAs are each responsible for providing a genMachineCheckFault and a +//genAlignmentFault functions, which return faults to use in the case of a +//machine check fault or an alignment fault, respectively. Base classes which +//provide the name() function, and the isMachineCheckFault and isAlignmentFault +//functions are provided below. + +class MachineCheckFault : public virtual FaultBase { -public: - MachineCheckFaultType(char * newName) : FaultBase(newName) {;} -} * const MachineCheckFault; + private: + static FaultName _name; + public: + FaultName name() {return _name;} + bool isMachineCheckFault() {return true;} +}; -extern class AlignmentFaultType : public FaultBase +class AlignmentFault : public virtual FaultBase { -public: - AlignmentFaultType(char * newName) : FaultBase(newName) {;} -} * const AlignmentFault; + private: + static FaultName _name; + public: + FaultName name() {return _name;} + bool isAlignmentFault() {return true;} +}; #endif // __FAULTS_HH__ diff --git a/sim/process.cc b/sim/process.cc index 0a7e46082..e3cae2855 100644 --- a/sim/process.cc +++ b/sim/process.cc @@ -48,10 +48,8 @@ #include "sim/stats.hh" #include "sim/syscall_emul.hh" -#ifdef TARGET_ALPHA -#include "arch/alpha/alpha_tru64_process.hh" -#include "arch/alpha/alpha_linux_process.hh" -#endif +#include "arch/tru64_process.hh" +#include "arch/linux_process.hh" using namespace std; using namespace TheISA; diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc index 58ea8266f..36c854d1c 100644 --- a/sim/pseudo_inst.cc +++ b/sim/pseudo_inst.cc @@ -34,7 +34,7 @@ #include <string> #include "sim/pseudo_inst.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "cpu/base.hh" #include "cpu/sampler/sampler.hh" #include "cpu/exec_context.hh" diff --git a/sim/system.cc b/sim/system.cc index 41de8cee4..378568a8a 100644 --- a/sim/system.cc +++ b/sim/system.cc @@ -33,7 +33,7 @@ #include "kern/kernel_stats.hh" #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "sim/builder.hh" #include "arch/isa_traits.hh" #include "sim/byteswap.hh" diff --git a/sim/vptr.hh b/sim/vptr.hh index 7ec43602d..0ec452f25 100644 --- a/sim/vptr.hh +++ b/sim/vptr.hh @@ -29,7 +29,7 @@ #ifndef __ARCH_ALPHA_VPTR_HH__ #define __ARCH_ALPHA_VPTR_HH__ -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "arch/isa_traits.hh" class ExecContext; |