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-rw-r--r--SConscript2
-rw-r--r--arch/alpha/ev5.cc4
-rw-r--r--arch/alpha/regfile.hh12
-rw-r--r--base/loader/object_file.cc4
-rw-r--r--cpu/base.hh1
-rw-r--r--cpu/cpu_exec_context.cc19
-rw-r--r--cpu/cpu_exec_context.hh1
-rw-r--r--cpu/simple/cpu.cc16
-rw-r--r--cpu/simple/cpu.hh5
-rw-r--r--mem/mem_object.cc37
-rw-r--r--mem/mem_object.hh6
-rw-r--r--mem/physical.cc18
-rw-r--r--mem/physical.hh9
-rw-r--r--mem/port.cc6
-rw-r--r--mem/port.hh11
-rw-r--r--mem/translating_port.cc54
-rw-r--r--mem/translating_port.hh28
-rw-r--r--sim/process.cc29
-rw-r--r--sim/process.hh14
-rw-r--r--sim/syscall_emul.cc10
-rw-r--r--sim/syscall_emul.hh30
-rw-r--r--sim/system.cc4
-rw-r--r--sim/system.hh6
23 files changed, 167 insertions, 159 deletions
diff --git a/SConscript b/SConscript
index ae7602c9d..e9957e143 100644
--- a/SConscript
+++ b/SConscript
@@ -88,7 +88,7 @@ base_sources = Split('''
cpu/static_inst.cc
cpu/sampler/sampler.cc
- mem/memory.cc
+ mem/mem_object.cc
mem/page_table.cc
mem/physical.cc
mem/port.cc
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index fed2f5358..a5a8851c2 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -542,10 +542,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
}
void
-AlphaISA::MiscRegFile::copyIprs(ExecContext *xc)
+AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
{
for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
- ipr[i] = xc->readMiscReg(i);
+ dest->setMiscReg(i, src->readMiscReg(i));
}
}
diff --git a/arch/alpha/regfile.hh b/arch/alpha/regfile.hh
index 13288e087..8a11a8eb6 100644
--- a/arch/alpha/regfile.hh
+++ b/arch/alpha/regfile.hh
@@ -34,6 +34,7 @@
#include "sim/faults.hh"
class Checkpoint;
+class ExecContext;
namespace AlphaISA
{
@@ -121,8 +122,6 @@ namespace AlphaISA
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc);
- void copyMiscRegs(ExecContext *xc);
-
#if FULL_SYSTEM
protected:
typedef uint64_t InternalProcReg;
@@ -133,8 +132,6 @@ namespace AlphaISA
InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
-
- void copyIprs(ExecContext *xc);
#endif
friend class RegFile;
};
@@ -159,6 +156,13 @@ namespace AlphaISA
void unserialize(Checkpoint *cp, const std::string &section);
};
+ void copyRegs(ExecContext *src, ExecContext *dest);
+
+ void copyMiscRegs(ExecContext *src, ExecContext *dest);
+
+#if FULL_SYSTEM
+ void copyIprs(ExecContext *src, ExecContext *dest);
+#endif
} // namespace AlphaISA
#endif
diff --git a/base/loader/object_file.cc b/base/loader/object_file.cc
index f33957269..7f46ae2fb 100644
--- a/base/loader/object_file.cc
+++ b/base/loader/object_file.cc
@@ -74,11 +74,11 @@ ObjectFile::loadSection(Section *sec, TranslatingPort *memPort, bool loadPhys)
}
if (sec->fileImage) {
- memPort->writeBlobFunctional(addr, sec->fileImage, sec->size, true);
+ memPort->writeBlob(addr, sec->fileImage, sec->size, true);
}
else {
// no image: must be bss
- memPort->memsetBlobFunctional(addr, 0, sec->size, true);
+ memPort->memsetBlob(addr, 0, sec->size, true);
}
}
return true;
diff --git a/cpu/base.hh b/cpu/base.hh
index 0866b49a7..79700c117 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -42,7 +42,6 @@ class System;
namespace Kernel { class Statistics; }
class BranchPred;
class ExecContext;
-class Port;
class BaseCPU : public SimObject
{
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index 79a4c00c6..0a3dc5675 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -28,6 +28,7 @@
#include <string>
+#include "arch/isa_traits.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
#include "cpu/exec_context.hh"
@@ -269,22 +270,6 @@ CPUExecContext::regStats(const string &name)
void
CPUExecContext::copyArchRegs(ExecContext *xc)
{
- // First loop through the integer registers.
- for (int i = 0; i < TheISA::NumIntRegs; ++i) {
- setIntReg(i, xc->readIntReg(i));
- }
-
- // Then loop through the floating point registers.
- for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
- setFloatRegBits(i, xc->readFloatRegBits(i));
- }
-
- // Copy misc. registers
- regs.miscRegs.copyMiscRegs(xc);
-
- // Lastly copy PC/NPC
- setPC(xc->readPC());
- setNextPC(xc->readNextPC());
- setNextNPC(xc->readNextNPC());
+ TheISA::copyRegs(xc, proxy);
}
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 2a90e07d3..236619752 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -53,6 +53,7 @@ class MemoryController;
#else // !FULL_SYSTEM
#include "sim/process.hh"
+#include "mem/page_table.hh"
class TranslatingPort;
#endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index b335944e9..ce690cd06 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -71,7 +71,7 @@
#include "arch/stacktrace.hh"
#include "arch/vtophys.hh"
#else // !FULL_SYSTEM
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
#endif // FULL_SYSTEM
using namespace std;
@@ -152,13 +152,13 @@ SimpleCPU::SimpleCPU(Params *p)
_status = Idle;
//Create Memory Ports (conect them up)
- p->mem->addPort("DCACHE");
- dcachePort.setPeer(p->mem->getPort("DCACHE"));
- (p->mem->getPort("DCACHE"))->setPeer(&dcachePort);
+ Port *mem_dport = p->mem->getPort();
+ dcachePort.setPeer(mem_dport);
+ mem_dport->setPeer(&dcachePort);
- p->mem->addPort("ICACHE");
- icachePort.setPeer(p->mem->getPort("ICACHE"));
- (p->mem->getPort("ICACHE"))->setPeer(&icachePort);
+ Port *mem_iport = p->mem->getPort();
+ icachePort.setPeer(mem_iport);
+ mem_iport->setPeer(&icachePort);
#if FULL_SYSTEM
cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
@@ -1128,7 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<int> cpu_id;
Param<Tick> profile;
#else
- SimObjectParam<Memory *> mem;
+ SimObjectParam<MemObject *> mem;
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index c1cf7ce96..dc07027f9 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -46,7 +46,7 @@
class Processor;
class AlphaITB;
class AlphaDTB;
-class Memory;
+class MemObject;
class RemoteGDB;
class GDBListener;
@@ -58,7 +58,6 @@ class Process;
#endif // FULL_SYSTEM
class ExecContext;
-class MemInterface;
class Checkpoint;
namespace Trace {
@@ -182,7 +181,7 @@ class SimpleCPU : public BaseCPU
AlphaITB *itb;
AlphaDTB *dtb;
#else
- Memory *mem;
+ MemObject *mem;
Process *process;
#endif
};
diff --git a/mem/mem_object.cc b/mem/mem_object.cc
new file mode 100644
index 000000000..f579a0727
--- /dev/null
+++ b/mem/mem_object.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/mem_object.hh"
+#include "sim/param.hh"
+
+MemObject::MemObject(const std::string &name)
+ : SimObject(name)
+{
+}
+
+DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
diff --git a/mem/mem_object.hh b/mem/mem_object.hh
index 634fb164a..7b3d942a4 100644
--- a/mem/mem_object.hh
+++ b/mem/mem_object.hh
@@ -44,13 +44,11 @@
class MemObject : public SimObject
{
public:
- MemObject(const std::string &name)
- : SimObject(name)
- {};
+ MemObject(const std::string &name);
public:
/** Additional function to return the Port of a memory object. */
- virtual Port *getPort(const char *if_name) = 0;
+ virtual Port *getPort(const char *if_name = NULL) = 0;
};
#endif //__MEM_MEM_OBJECT_HH__
diff --git a/mem/physical.cc b/mem/physical.cc
index a00c59139..c1e83fb9e 100644
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -70,7 +70,7 @@ PhysicalMemory::MemResponseEvent::description()
}
PhysicalMemory::PhysicalMemory(const string &n)
- : Memory(n), base_addr(0), pmem_addr(NULL)
+ : MemObject(n), base_addr(0), pmem_addr(NULL)
{
// Hardcoded to 128 MB for now.
pmem_size = 1 << 27;
@@ -107,13 +107,6 @@ PhysicalMemory::new_page()
return return_addr;
}
-Port *
-PhysicalMemory::addPort(std::string portName)
-{
- memoryPortList[portName] = new MemoryPort(this);
- return memoryPortList[portName];
-}
-
int
PhysicalMemory::deviceBlockSize()
{
@@ -161,10 +154,11 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
Port *
PhysicalMemory::getPort(const char *if_name)
{
- if (memoryPortList.find(if_name) != memoryPortList.end())
- return memoryPortList[if_name];
- else
- panic("Looking for a port that didn't exist\n");
+ if (if_name == NULL) {
+ return new MemoryPort(this);
+ } else {
+ panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
+ }
}
void
diff --git a/mem/physical.hh b/mem/physical.hh
index 658ba18ff..b066d3dfc 100644
--- a/mem/physical.hh
+++ b/mem/physical.hh
@@ -33,16 +33,17 @@
#define __PHYSICAL_MEMORY_HH__
#include "base/range.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
#include <map>
#include <string>
+
//
// Functional model for a contiguous block of physical memory. (i.e. RAM)
//
-class PhysicalMemory : public Memory
+class PhysicalMemory : public MemObject
{
class MemoryPort : public Port
{
@@ -68,12 +69,8 @@ class PhysicalMemory : public Memory
virtual int deviceBlockSize();
};
- std::map<std::string, MemoryPort*> memoryPortList;
-
virtual Port * getPort(const char *if_name);
- virtual Port * addPort(std::string portName);
-
int numPorts;
int lat;
diff --git a/mem/port.cc b/mem/port.cc
index 75362b472..fb4f3b4e0 100644
--- a/mem/port.cc
+++ b/mem/port.cc
@@ -52,19 +52,19 @@ Port::blobHelper(Addr addr, uint8_t *p, int size, Command cmd)
}
void
-Port::writeBlobFunctional(Addr addr, uint8_t *p, int size)
+Port::writeBlob(Addr addr, uint8_t *p, int size)
{
blobHelper(addr, p, size, Write);
}
void
-Port::readBlobFunctional(Addr addr, uint8_t *p, int size)
+Port::readBlob(Addr addr, uint8_t *p, int size)
{
blobHelper(addr, p, size, Read);
}
void
-Port::memsetBlobFunctional(Addr addr, uint8_t val, int size)
+Port::memsetBlob(Addr addr, uint8_t val, int size)
{
// quick and dirty...
uint8_t *buf = new uint8_t[size];
diff --git a/mem/port.hh b/mem/port.hh
index 5c89c74a5..ea2929a81 100644
--- a/mem/port.hh
+++ b/mem/port.hh
@@ -191,29 +191,26 @@ class Port
void getPeerAddressRanges(AddrRangeList &range_list, bool &owner)
{ peer->getDeviceAddressRanges(range_list, owner); }
- // Do we need similar wrappers for sendAtomic()? If not, should
- // we drop the "Functional" from the names?
-
/** This function is a wrapper around sendFunctional()
that breaks a larger, arbitrarily aligned access into
appropriate chunks. The default implementation can use
getBlockSize() to determine the block size and go from there.
*/
- void readBlobFunctional(Addr addr, uint8_t *p, int size);
+ void readBlob(Addr addr, uint8_t *p, int size);
/** This function is a wrapper around sendFunctional()
that breaks a larger, arbitrarily aligned access into
appropriate chunks. The default implementation can use
getBlockSize() to determine the block size and go from there.
*/
- void writeBlobFunctional(Addr addr, uint8_t *p, int size);
+ void writeBlob(Addr addr, uint8_t *p, int size);
/** Fill size bytes starting at addr with byte value val. This
should not need to be virtual, since it can be implemented in
- terms of writeBlobFunctional(). However, it shouldn't be
+ terms of writeBlob(). However, it shouldn't be
performance-critical either, so it could be if we wanted to.
*/
- void memsetBlobFunctional(Addr addr, uint8_t val, int size);
+ void memsetBlob(Addr addr, uint8_t val, int size);
private:
diff --git a/mem/translating_port.cc b/mem/translating_port.cc
index a3bf1baa7..f0059fc08 100644
--- a/mem/translating_port.cc
+++ b/mem/translating_port.cc
@@ -42,7 +42,7 @@ TranslatingPort::~TranslatingPort()
{ }
bool
-TranslatingPort::tryReadBlobFunctional(Addr addr, uint8_t *p, int size)
+TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size)
{
Addr paddr;
int prevSize = 0;
@@ -52,7 +52,7 @@ TranslatingPort::tryReadBlobFunctional(Addr addr, uint8_t *p, int size)
if (!pTable->translate(gen.addr(),paddr))
return false;
- port->readBlobFunctional(paddr, p + prevSize, gen.size());
+ port->readBlob(paddr, p + prevSize, gen.size());
prevSize += gen.size();
}
@@ -60,16 +60,15 @@ TranslatingPort::tryReadBlobFunctional(Addr addr, uint8_t *p, int size)
}
void
-TranslatingPort::readBlobFunctional(Addr addr, uint8_t *p, int size)
+TranslatingPort::readBlob(Addr addr, uint8_t *p, int size)
{
- if (!tryReadBlobFunctional(addr, p, size))
- fatal("readBlobFunctional(0x%x, ...) failed", addr);
+ if (!tryReadBlob(addr, p, size))
+ fatal("readBlob(0x%x, ...) failed", addr);
}
bool
-TranslatingPort::tryWriteBlobFunctional(Addr addr, uint8_t *p, int size,
- bool alloc)
+TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size, bool alloc)
{
Addr paddr;
@@ -87,7 +86,7 @@ TranslatingPort::tryWriteBlobFunctional(Addr addr, uint8_t *p, int size,
}
}
- port->writeBlobFunctional(paddr, p + prevSize, gen.size());
+ port->writeBlob(paddr, p + prevSize, gen.size());
prevSize += gen.size();
}
@@ -96,16 +95,14 @@ TranslatingPort::tryWriteBlobFunctional(Addr addr, uint8_t *p, int size,
void
-TranslatingPort::writeBlobFunctional(Addr addr, uint8_t *p, int size,
- bool alloc)
+TranslatingPort::writeBlob(Addr addr, uint8_t *p, int size, bool alloc)
{
- if (!tryWriteBlobFunctional(addr, p, size, alloc))
- fatal("writeBlobFunctional(0x%x, ...) failed", addr);
+ if (!tryWriteBlob(addr, p, size, alloc))
+ fatal("writeBlob(0x%x, ...) failed", addr);
}
bool
-TranslatingPort::tryMemsetBlobFunctional(Addr addr, uint8_t val, int size,
- bool alloc)
+TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size, bool alloc)
{
Addr paddr;
@@ -121,23 +118,22 @@ TranslatingPort::tryMemsetBlobFunctional(Addr addr, uint8_t val, int size,
}
}
- port->memsetBlobFunctional(paddr, val, gen.size());
+ port->memsetBlob(paddr, val, gen.size());
}
return true;
}
void
-TranslatingPort::memsetBlobFunctional(Addr addr, uint8_t val, int size,
- bool alloc)
+TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size, bool alloc)
{
- if (!tryMemsetBlobFunctional(addr, val, size, alloc))
- fatal("memsetBlobFunctional(0x%x, ...) failed", addr);
+ if (!tryMemsetBlob(addr, val, size, alloc))
+ fatal("memsetBlob(0x%x, ...) failed", addr);
}
bool
-TranslatingPort::tryWriteStringFunctional(Addr addr, const char *str)
+TranslatingPort::tryWriteString(Addr addr, const char *str)
{
Addr paddr,vaddr;
uint8_t c;
@@ -149,21 +145,21 @@ TranslatingPort::tryWriteStringFunctional(Addr addr, const char *str)
if (!pTable->translate(vaddr++,paddr))
return false;
- port->writeBlobFunctional(paddr, &c, 1);
+ port->writeBlob(paddr, &c, 1);
} while (c);
return true;
}
void
-TranslatingPort::writeStringFunctional(Addr addr, const char *str)
+TranslatingPort::writeString(Addr addr, const char *str)
{
- if (!tryWriteStringFunctional(addr, str))
- fatal("writeStringFunctional(0x%x, ...) failed", addr);
+ if (!tryWriteString(addr, str))
+ fatal("writeString(0x%x, ...) failed", addr);
}
bool
-TranslatingPort::tryReadStringFunctional(std::string &str, Addr addr)
+TranslatingPort::tryReadString(std::string &str, Addr addr)
{
Addr paddr,vaddr;
uint8_t c;
@@ -174,7 +170,7 @@ TranslatingPort::tryReadStringFunctional(std::string &str, Addr addr)
if (!pTable->translate(vaddr++,paddr))
return false;
- port->readBlobFunctional(paddr, &c, 1);
+ port->readBlob(paddr, &c, 1);
str += c;
} while (c);
@@ -182,9 +178,9 @@ TranslatingPort::tryReadStringFunctional(std::string &str, Addr addr)
}
void
-TranslatingPort::readStringFunctional(std::string &str, Addr addr)
+TranslatingPort::readString(std::string &str, Addr addr)
{
- if (!tryReadStringFunctional(str, addr))
- fatal("readStringFunctional(0x%x, ...) failed", addr);
+ if (!tryReadString(str, addr))
+ fatal("readString(0x%x, ...) failed", addr);
}
diff --git a/mem/translating_port.hh b/mem/translating_port.hh
index eaecff35a..2ba3d68e2 100644
--- a/mem/translating_port.hh
+++ b/mem/translating_port.hh
@@ -29,8 +29,6 @@
#ifndef __MEM_TRANSLATING_PROT_HH__
#define __MEM_TRANSLATING_PROT_HH__
-#include "mem/memory.hh"
-
class Port;
class PageTable;
@@ -48,21 +46,17 @@ class TranslatingPort
virtual ~TranslatingPort();
public:
- bool tryReadBlobFunctional(Addr addr, uint8_t *p, int size);
- bool tryWriteBlobFunctional(Addr addr, uint8_t *p, int size,
- bool alloc = false);
- bool tryMemsetBlobFunctional(Addr addr, uint8_t val, int size,
- bool alloc = false);
- bool tryWriteStringFunctional(Addr addr, const char *str);
- bool tryReadStringFunctional(std::string &str, Addr addr);
-
- void readBlobFunctional(Addr addr, uint8_t *p, int size);
- void writeBlobFunctional(Addr addr, uint8_t *p, int size,
- bool alloc = false);
- void memsetBlobFunctional(Addr addr, uint8_t val, int size,
- bool alloc = false);
- void writeStringFunctional(Addr addr, const char *str);
- void readStringFunctional(std::string &str, Addr addr);
+ bool tryReadBlob(Addr addr, uint8_t *p, int size);
+ bool tryWriteBlob(Addr addr, uint8_t *p, int size, bool alloc = false);
+ bool tryMemsetBlob(Addr addr, uint8_t val, int size, bool alloc = false);
+ bool tryWriteString(Addr addr, const char *str);
+ bool tryReadString(std::string &str, Addr addr);
+
+ void readBlob(Addr addr, uint8_t *p, int size);
+ void writeBlob(Addr addr, uint8_t *p, int size, bool alloc = false);
+ void memsetBlob(Addr addr, uint8_t val, int size, bool alloc = false);
+ void writeString(Addr addr, const char *str);
+ void readString(std::string &str, Addr addr);
};
#endif
diff --git a/sim/process.cc b/sim/process.cc
index c8c4d0ba6..80f787062 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -39,7 +39,7 @@
#include "config/full_system.hh"
#include "cpu/exec_context.hh"
#include "mem/page_table.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
#include "mem/translating_port.hh"
#include "sim/builder.hh"
#include "sim/process.hh"
@@ -149,13 +149,27 @@ Process::startup()
if (execContexts.empty())
fatal("Process %s is not associated with any CPUs!\n", name());
- initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
-
// first exec context for this process... initialize & enable
ExecContext *xc = execContexts[0];
// mark this context as active so it will start ticking.
xc->activate(0);
+
+ // Here we are grabbing the memory port of the CPU hosting the
+ // initial execution context for initialization. In the long run
+ // this is not what we want, since it means that all
+ // initialization accesses (e.g., loading object file sections)
+ // will be done a cache block at a time through the CPU's cache.
+ // We really want something more like:
+ //
+ // memport = system->physmem->getPort();
+ // myPort.setPeer(memport);
+ // memport->setPeer(&myPort);
+ // initVirtMem = new TranslatingPort(myPort, pTable);
+ //
+ // but we need our own dummy port "myPort" that doesn't exist.
+ // In the short term it works just fine though.
+ initVirtMem = xc->getMemPort();
}
void
@@ -245,15 +259,15 @@ copyStringArray(vector<string> &strings, Addr array_ptr, Addr data_ptr,
Addr data_ptr_swap;
for (int i = 0; i < strings.size(); ++i) {
data_ptr_swap = htog(data_ptr);
- memPort->writeBlobFunctional(array_ptr, (uint8_t*)&data_ptr_swap, sizeof(Addr));
- memPort->writeStringFunctional(data_ptr, strings[i].c_str());
+ memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap, sizeof(Addr));
+ memPort->writeString(data_ptr, strings[i].c_str());
array_ptr += sizeof(Addr);
data_ptr += strings[i].size() + 1;
}
// add NULL terminator
data_ptr = 0;
- memPort->writeBlobFunctional(array_ptr, (uint8_t*)&data_ptr, sizeof(Addr));
+ memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(Addr));
}
LiveProcess::LiveProcess(const string &nm, ObjectFile *_objFile,
@@ -336,7 +350,7 @@ LiveProcess::startup()
// write contents to stack
uint64_t argc = argv.size();
argc = htog(argc);
- initVirtMem->writeBlobFunctional(stack_min, (uint8_t*)&argc, sizeof(uint64_t));
+ initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, sizeof(uint64_t));
copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
@@ -367,6 +381,7 @@ LiveProcess::syscall(ExecContext *xc)
desc->doSyscall(callnum, this, xc);
}
+
LiveProcess *
LiveProcess::create(const string &nm, System *system,
int stdin_fd, int stdout_fd, int stderr_fd,
diff --git a/sim/process.hh b/sim/process.hh
index ffdca819e..68312f115 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -40,27 +40,18 @@
#include <vector>
-#include "arch/isa_traits.hh"
#include "base/statistics.hh"
-#include "base/trace.hh"
-#include "mem/memory.hh"
-//#include "mem/mem_interface.hh"
-#include "mem/page_table.hh"
#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-#include "arch/isa_traits.hh"
class CPUExecContext;
class ExecContext;
class SyscallDesc;
+class PageTable;
class TranslatingPort;
class System;
class Process : public SimObject
{
- protected:
- typedef TheISA::RegFile RegFile;
- typedef TheISA::MachInst MachInst;
public:
/// Pointer to object representing the system this process is
@@ -198,8 +189,7 @@ class LiveProcess : public Process
virtual void syscall(ExecContext *xc);
- virtual SyscallDesc* getDesc(int callnum) { panic("Must be implemented."); }
-
+ virtual SyscallDesc* getDesc(int callnum) = 0;
};
diff --git a/sim/syscall_emul.cc b/sim/syscall_emul.cc
index 6c24b6dc5..3dedb7c5e 100644
--- a/sim/syscall_emul.cc
+++ b/sim/syscall_emul.cc
@@ -193,7 +193,7 @@ unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return (TheISA::IntReg)-EFAULT;
int result = unlink(path.c_str());
@@ -205,12 +205,12 @@ renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string old_name;
- if (!xc->getMemPort()->tryReadStringFunctional(old_name, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(old_name, xc->getSyscallArg(0)))
return -EFAULT;
string new_name;
- if (!xc->getMemPort()->tryReadStringFunctional(new_name, xc->getSyscallArg(1)))
+ if (!xc->getMemPort()->tryReadString(new_name, xc->getSyscallArg(1)))
return -EFAULT;
int64_t result = rename(old_name.c_str(), new_name.c_str());
@@ -222,7 +222,7 @@ truncateFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
off_t length = xc->getSyscallArg(1);
@@ -250,7 +250,7 @@ chownFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
/* XXX endianess */
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 60e06b294..9554ab318 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -48,7 +48,7 @@
#include "base/intmath.hh" // for RoundUp
#include "mem/translating_port.hh"
#include "arch/isa_traits.hh" // for Addr
-
+#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
@@ -109,7 +109,7 @@ class BaseBufferArg {
//
virtual bool copyIn(TranslatingPort *memport)
{
- memport->readBlobFunctional(addr, bufPtr, size);
+ memport->readBlob(addr, bufPtr, size);
return true; // no EFAULT detection for now
}
@@ -118,7 +118,7 @@ class BaseBufferArg {
//
virtual bool copyOut(TranslatingPort *memport)
{
- memport->writeBlobFunctional(addr, bufPtr, size);
+ memport->writeBlob(addr, bufPtr, size);
return true; // no EFAULT detection for now
}
@@ -370,7 +370,7 @@ openFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
if (path == "/dev/sysdev0") {
@@ -417,7 +417,7 @@ chmodFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
uint32_t mode = xc->getSyscallArg(1);
@@ -470,7 +470,7 @@ statFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
struct stat hostBuf;
@@ -522,7 +522,7 @@ lstatFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
struct stat hostBuf;
@@ -544,7 +544,7 @@ lstat64Func(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
#if BSD_HOST
@@ -596,7 +596,7 @@ statfsFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
struct statfs hostBuf;
@@ -646,18 +646,20 @@ writevFunc(SyscallDesc *desc, int callnum, Process *process,
return -EBADF;
}
+ TranslatingPort *p = xc->getMemPort();
uint64_t tiov_base = xc->getSyscallArg(1);
size_t count = xc->getSyscallArg(2);
struct iovec hiov[count];
for (int i = 0; i < count; ++i)
{
typename OS::tgt_iovec tiov;
- xc->getMemPort()->readBlobFunctional(tiov_base + i*sizeof(typename OS::tgt_iovec),(uint8_t*)
- &tiov, sizeof(typename OS::tgt_iovec));
+
+ p->readBlob(tiov_base + i*sizeof(typename OS::tgt_iovec),
+ (uint8_t*)&tiov, sizeof(typename OS::tgt_iovec));
hiov[i].iov_len = gtoh(tiov.iov_len);
hiov[i].iov_base = new char [hiov[i].iov_len];
- xc->getMemPort()->readBlobFunctional(gtoh(tiov.iov_base),
- (uint8_t *)hiov[i].iov_base, hiov[i].iov_len);
+ p->readBlob(gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
+ hiov[i].iov_len);
}
int result = writev(process->sim_fd(fd), hiov, count);
@@ -770,7 +772,7 @@ utimesFunc(SyscallDesc *desc, int callnum, Process *process,
{
std::string path;
- if (!xc->getMemPort()->tryReadStringFunctional(path, xc->getSyscallArg(0)))
+ if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
return -EFAULT;
TypedBufferArg<typename OS::timeval [2]> tp(xc->getSyscallArg(1));
diff --git a/sim/system.cc b/sim/system.cc
index 05b41e32b..409e41ead 100644
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -1,12 +1,12 @@
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh"
-#include "mem/memory.hh"
#include "sim/builder.hh"
#include "arch/isa_traits.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
#include "base/trace.hh"
+#include "mem/mem_object.hh"
#if FULL_SYSTEM
#include "base/remote_gdb.hh"
#include "kern/kernel_stats.hh"
@@ -228,7 +228,7 @@ DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
- SimObjectParam<Memory *> physmem;
+ SimObjectParam<MemObject *> physmem;
END_DECLARE_SIM_OBJECT_PARAMS(System)
diff --git a/sim/system.hh b/sim/system.hh
index a0ba4f141..0f82f81f5 100644
--- a/sim/system.hh
+++ b/sim/system.hh
@@ -45,7 +45,7 @@ class BaseCPU;
class ExecContext;
class MemoryController;
class ObjectFile;
-class Memory;
+class MemObject;
#if FULL_SYSTEM
class Platform;
@@ -57,7 +57,7 @@ namespace Kernel { class Binning; }
class System : public SimObject
{
public:
- Memory *physmem;
+ MemObject *physmem;
PCEventQueue pcEventQueue;
std::vector<ExecContext *> execContexts;
@@ -146,7 +146,7 @@ class System : public SimObject
struct Params
{
std::string name;
- Memory *physmem;
+ MemObject *physmem;
#if FULL_SYSTEM
Tick boot_cpu_frequency;
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-01 18:24:21 +0000