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-rw-r--r--src/arch/x86/bios/SConscript27
-rw-r--r--src/arch/x86/interrupts.cc1
-rw-r--r--src/arch/x86/interrupts.hh1
-rw-r--r--src/arch/x86/mmapped_ipr.hh9
-rw-r--r--src/arch/x86/remote_gdb.cc1
-rw-r--r--src/arch/x86/tlb.cc17
-rw-r--r--src/arch/x86/tlb.hh6
-rw-r--r--src/arch/x86/utility.cc17
-rw-r--r--src/arch/x86/utility.hh18
-rw-r--r--src/arch/x86/vtophys.cc7
10 files changed, 22 insertions, 82 deletions
diff --git a/src/arch/x86/bios/SConscript b/src/arch/x86/bios/SConscript
index 16a413ed0..abc734ef4 100644
--- a/src/arch/x86/bios/SConscript
+++ b/src/arch/x86/bios/SConscript
@@ -40,20 +40,19 @@
Import('*')
if env['TARGET_ISA'] == 'x86':
- if env['FULL_SYSTEM']:
- # The table generated by the bootloader using the BIOS and passed to
- # the operating system which maps out physical memory.
- SimObject('E820.py')
- Source('e820.cc')
+ # The table generated by the bootloader using the BIOS and passed to
+ # the operating system which maps out physical memory.
+ SimObject('E820.py')
+ Source('e820.cc')
- # The DMI tables.
- SimObject('SMBios.py')
- Source('smbios.cc')
+ # The DMI tables.
+ SimObject('SMBios.py')
+ Source('smbios.cc')
- # Intel Multiprocessor Specification Configuration Table
- SimObject('IntelMP.py')
- Source('intelmp.cc')
+ # Intel Multiprocessor Specification Configuration Table
+ SimObject('IntelMP.py')
+ Source('intelmp.cc')
- # ACPI system description tables
- SimObject('ACPI.py')
- Source('acpi.cc')
+ # ACPI system description tables
+ SimObject('ACPI.py')
+ Source('acpi.cc')
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 38b966dbe..994e9bce4 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -40,6 +40,7 @@
#include "arch/x86/regs/apic.hh"
#include "arch/x86/interrupts.hh"
#include "arch/x86/intmessage.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "debug/LocalApic.hh"
#include "dev/x86/i82094aa.hh"
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 03b4c97b3..389eb4f42 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -44,7 +44,6 @@
#include "arch/x86/faults.hh"
#include "arch/x86/intmessage.hh"
#include "base/bitfield.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "dev/x86/intdev.hh"
#include "dev/io_device.hh"
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 525f54bfb..054f280a8 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -47,7 +47,6 @@
*/
#include "arch/x86/regs/misc.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
@@ -57,25 +56,18 @@ namespace X86ISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data = htog(xc->readMiscReg(index));
// Make sure we don't trot off the end of data.
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->setData(((uint8_t *)&data) + offset);
-#endif
return xc->getCpuPtr()->ticks(1);
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
Addr offset = pkt->getAddr() & mask(3);
MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
MiscReg data;
@@ -84,7 +76,6 @@ namespace X86ISA
assert(offset + pkt->getSize() <= sizeof(MiscReg));
pkt->writeData(((uint8_t *)&data) + offset);
xc->setMiscReg(index, gtoh(data));
-#endif
return xc->getCpuPtr()->ticks(1);
}
};
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 8db7a6088..c7bce59bf 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -47,7 +47,6 @@
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
using namespace std;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ff30697e5..53f7f978e 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -49,7 +49,6 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
@@ -406,28 +405,12 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(fault, req, tc, mode);
}
-#if FULL_SYSTEM
-
-Tick
-TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
-{
- return tc->getCpuPtr()->ticks(1);
-}
-
-Tick
-TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
-{
- return tc->getCpuPtr()->ticks(1);
-}
-
Walker *
TLB::getWalker()
{
return walker;
}
-#endif
-
void
TLB::serialize(std::ostream &os)
{
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e82784900..449ca19ce 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -46,7 +46,6 @@
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
-#include "config/full_system.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
@@ -116,11 +115,6 @@ namespace X86ISA
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
-#if FULL_SYSTEM
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
-
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 29c770f3d..678467672 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -38,11 +38,7 @@
* Authors: Gabe Black
*/
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
#include "arch/x86/interrupts.hh"
-#endif
#include "arch/x86/registers.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/utility.hh"
@@ -55,15 +51,10 @@ namespace X86ISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
panic("getArgument() not implemented for x86!\n");
-#else
- panic("getArgument() only implemented for FULL_SYSTEM\n");
M5_DUMMY_RETURN
-#endif
}
-# if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
@@ -193,12 +184,9 @@ void initCPU(ThreadContext *tc, int cpuId)
tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
}
-#endif
-
void startupCPU(ThreadContext *tc, int cpuId)
{
-#if FULL_SYSTEM
- if (cpuId == 0) {
+ if (cpuId == 0 || !FullSystem) {
tc->activate(0);
} else {
// This is an application processor (AP). It should be initialized to
@@ -206,9 +194,6 @@ void startupCPU(ThreadContext *tc, int cpuId)
// a halted state.
tc->suspend(0);
}
-#else
- tc->activate(0);
-#endif
}
void
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 4cfbe77db..f120ea6c7 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -45,9 +45,9 @@
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
class ThreadContext;
@@ -68,12 +68,12 @@ namespace X86ISA
static inline bool
inUserMode(ThreadContext *tc)
{
-#if FULL_SYSTEM
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- return m5reg.cpl == 3;
-#else
- return true;
-#endif
+ if (!FullSystem) {
+ return true;
+ } else {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ return m5reg.cpl == 3;
+ }
}
/**
@@ -83,12 +83,8 @@ namespace X86ISA
template <class TC>
void zeroRegisters(TC *tc);
-#if FULL_SYSTEM
-
void initCPU(ThreadContext *tc, int cpuId);
-#endif
-
void startupCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index 60ce37131..e4abfca59 100644
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -43,7 +43,6 @@
#include "arch/x86/tlb.hh"
#include "arch/x86/vtophys.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "sim/fault_fwd.hh"
@@ -55,16 +54,12 @@ namespace X86ISA
Addr
vtophys(Addr vaddr)
{
-#if FULL_SYSTEM
panic("Need access to page tables\n");
-#endif
- return vaddr;
}
Addr
vtophys(ThreadContext *tc, Addr vaddr)
{
-#if FULL_SYSTEM
Walker *walker = tc->getDTBPtr()->getWalker();
Addr size;
Addr addr = vaddr;
@@ -75,7 +70,5 @@ namespace X86ISA
Addr paddr = addr | masked_addr;
DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
return paddr;
-#endif
- return vaddr;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 12:16:35 +0000