diff options
| -rw-r--r-- | src/arch/x86/isa/decoder/one_byte_opcodes.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py | 14 |
2 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index 23ba243fb..483e750b2 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -463,7 +463,7 @@ 0x0: UD2(); default: WarnUnimpl::salc(); } - 0x7: WarnUnimpl::xlat(); + 0x7: XLAT(); } ##include "x87.isa" 0x1C: decode OPCODE_OP_BOTTOM3 { diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py index bb286b976..c2ccb9d19 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py @@ -53,8 +53,12 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class XLAT(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop XLAT { + zext t1, rax, 8 + # Here, t1 can be used directly. The value of al is supposed to be treated + # as unsigned. Since we zero extended it from 8 bits above and the address + # size has to be at least 16 bits, t1 will not be sign extended. + ld rax, seg, [1, rbx, t1], dataSize=1 +}; +''' |